* [PATCH v2 0/3] target/m68k: MacOS related fixes
@ 2021-03-08 12:11 Mark Cave-Ayland
2021-03-08 12:11 ` [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Mark Cave-Ayland @ 2021-03-08 12:11 UTC (permalink / raw)
To: qemu-devel, laurent
Here are a couple of extra target/m68k patches taken from my attempts to try
and boot MacOS.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
v2:
- Add R-B tags from Laurent
- Add patch 2 to facilitate longer feature names and descriptions
- Rename M68K_FEATURE_NO_DALIGN to M68K_FEATURE_UNALIGNED_DATA as suggested by Richard
Mark Cave-Ayland (3):
target/m68k: don't set SSW ATC bit for physical bus errors
target/m68k: reformat m68k_features enum
target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature
target/m68k/cpu.c | 1 +
target/m68k/cpu.h | 68 ++++++++++++++++++++++++++++-------------
target/m68k/op_helper.c | 17 +++++++++--
3 files changed, 62 insertions(+), 24 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors 2021-03-08 12:11 [PATCH v2 0/3] target/m68k: MacOS related fixes Mark Cave-Ayland @ 2021-03-08 12:11 ` Mark Cave-Ayland 2021-03-09 19:46 ` Laurent Vivier 2021-03-08 12:11 ` [PATCH v2 2/3] target/m68k: reformat m68k_features enum Mark Cave-Ayland 2021-03-08 12:11 ` [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Mark Cave-Ayland 2 siblings, 1 reply; 10+ messages in thread From: Mark Cave-Ayland @ 2021-03-08 12:11 UTC (permalink / raw) To: qemu-devel, laurent If a NuBus slot doesn't contain a card, the Quadra hardware generates a physical bus error if the CPU attempts to access the slot address space. Both Linux and MacOS use a separate bus error handler during NuBus accesses in order to detect and recover when addressing empty slots. According to the MC68040 users manual the ATC bit of the SSW is used to distinguish between ATC faults and physical bus errors. MacOS specifically checks the stack frame generated by a NuBus error and panics if the SSW ATC bit is set. Update m68k_cpu_transaction_failed() so that the SSW ATC bit is not set if the memory API returns MEMTX_DECODE_ERROR which will be used to indicate that an access to an empty NuBus slot occurred. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> --- target/m68k/op_helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 202498deb5..59a6448296 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -468,7 +468,17 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, if (m68k_feature(env, M68K_FEATURE_M68040)) { env->mmu.mmusr = 0; - env->mmu.ssw |= M68K_ATC_040; + + /* + * According to the MC68040 users manual the ATC bit of the SSW is + * used to distinguish between ATC faults and physical bus errors. + * In the case of a bus error e.g. during nubus read from an empty + * slot this bit should not be set + */ + if (response != MEMTX_DECODE_ERROR) { + env->mmu.ssw |= M68K_ATC_040; + } + /* FIXME: manage MMU table access error */ env->mmu.ssw &= ~M68K_TM_040; if (env->sr & SR_S) { /* SUPERVISOR */ -- 2.20.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors 2021-03-08 12:11 ` [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland @ 2021-03-09 19:46 ` Laurent Vivier 0 siblings, 0 replies; 10+ messages in thread From: Laurent Vivier @ 2021-03-09 19:46 UTC (permalink / raw) To: Mark Cave-Ayland, qemu-devel Le 08/03/2021 à 13:11, Mark Cave-Ayland a écrit : > If a NuBus slot doesn't contain a card, the Quadra hardware generates a physical > bus error if the CPU attempts to access the slot address space. Both Linux and > MacOS use a separate bus error handler during NuBus accesses in order to detect > and recover when addressing empty slots. > > According to the MC68040 users manual the ATC bit of the SSW is used to > distinguish between ATC faults and physical bus errors. MacOS specifically checks > the stack frame generated by a NuBus error and panics if the SSW ATC bit is set. > > Update m68k_cpu_transaction_failed() so that the SSW ATC bit is not set if the > memory API returns MEMTX_DECODE_ERROR which will be used to indicate that an > access to an empty NuBus slot occurred. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Reviewed-by: Laurent Vivier <laurent@vivier.eu> > --- > target/m68k/op_helper.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c > index 202498deb5..59a6448296 100644 > --- a/target/m68k/op_helper.c > +++ b/target/m68k/op_helper.c > @@ -468,7 +468,17 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, > > if (m68k_feature(env, M68K_FEATURE_M68040)) { > env->mmu.mmusr = 0; > - env->mmu.ssw |= M68K_ATC_040; > + > + /* > + * According to the MC68040 users manual the ATC bit of the SSW is > + * used to distinguish between ATC faults and physical bus errors. > + * In the case of a bus error e.g. during nubus read from an empty > + * slot this bit should not be set > + */ > + if (response != MEMTX_DECODE_ERROR) { > + env->mmu.ssw |= M68K_ATC_040; > + } > + > /* FIXME: manage MMU table access error */ > env->mmu.ssw &= ~M68K_TM_040; > if (env->sr & SR_S) { /* SUPERVISOR */ > Applied to my m68k-for-6.0 branch Thanks, Laurent ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] target/m68k: reformat m68k_features enum 2021-03-08 12:11 [PATCH v2 0/3] target/m68k: MacOS related fixes Mark Cave-Ayland 2021-03-08 12:11 ` [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland @ 2021-03-08 12:11 ` Mark Cave-Ayland 2021-03-08 17:33 ` Laurent Vivier ` (2 more replies) 2021-03-08 12:11 ` [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Mark Cave-Ayland 2 siblings, 3 replies; 10+ messages in thread From: Mark Cave-Ayland @ 2021-03-08 12:11 UTC (permalink / raw) To: qemu-devel, laurent Move the feature comment from after the feature name to the preceding line to allow for longer feature names and descriptions without hitting the 80 character line limit. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> --- target/m68k/cpu.h | 66 +++++++++++++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 22 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7c3feeaf8a..ce558e9b03 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -475,36 +475,58 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); */ enum m68k_features { - M68K_FEATURE_M68000, /* Base m68k instruction set */ + /* Base m68k instruction set */ + M68K_FEATURE_M68000, M68K_FEATURE_M68010, M68K_FEATURE_M68020, M68K_FEATURE_M68030, M68K_FEATURE_M68040, M68K_FEATURE_M68060, - M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ - M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ - M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ - M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ + /* Base Coldfire set Rev A. */ + M68K_FEATURE_CF_ISA_A, + /* (ISA B or C). */ + M68K_FEATURE_CF_ISA_B, + /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ + M68K_FEATURE_CF_ISA_APLUSC, + /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ + M68K_FEATURE_BRAL, M68K_FEATURE_CF_FPU, M68K_FEATURE_CF_MAC, M68K_FEATURE_CF_EMAC, - M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ - M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/ - M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */ - M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ - M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ - M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ - M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ - M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ - M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */ - M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ - M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ - M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ - M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ - M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ - M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ - M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ - M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ + /* Revision B EMAC (dual accumulate). */ + M68K_FEATURE_CF_EMAC_B, + /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ + M68K_FEATURE_USP, + /* Master Stack Pointer. (680[234]0) */ + M68K_FEATURE_MSP, + /* 68020+ full extension word. */ + M68K_FEATURE_EXT_FULL, + /* word sized address index registers. */ + M68K_FEATURE_WORD_INDEX, + /* scaled address index registers. */ + M68K_FEATURE_SCALED_INDEX, + /* 32 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_LONG_MULDIV, + /* 64 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_QUAD_MULDIV, + /* Bcc with Long branches. (680[2346]0, and CPU32) */ + M68K_FEATURE_BCCL, + /* BFxxx Bit field insns. (680[2346]0) */ + M68K_FEATURE_BITFIELD, + /* fpu insn. (680[46]0) */ + M68K_FEATURE_FPU, + /* CAS/CAS2[WL] insns. (680[2346]0) */ + M68K_FEATURE_CAS, + /* BKPT insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_BKPT, + /* RTD insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_RTD, + /* CHK2 insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_CHK2, + /* MOVEP insn. (680[01234]0, and CPU32) */ + M68K_FEATURE_MOVEP, + /* MOVEC insn. (from 68010) */ + M68K_FEATURE_MOVEC, }; static inline int m68k_feature(CPUM68KState *env, int feature) -- 2.20.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] target/m68k: reformat m68k_features enum 2021-03-08 12:11 ` [PATCH v2 2/3] target/m68k: reformat m68k_features enum Mark Cave-Ayland @ 2021-03-08 17:33 ` Laurent Vivier 2021-03-09 14:21 ` Richard Henderson 2021-03-09 19:46 ` Laurent Vivier 2 siblings, 0 replies; 10+ messages in thread From: Laurent Vivier @ 2021-03-08 17:33 UTC (permalink / raw) To: Mark Cave-Ayland, qemu-devel Le 08/03/2021 à 13:11, Mark Cave-Ayland a écrit : > Move the feature comment from after the feature name to the preceding line to > allow for longer feature names and descriptions without hitting the 80 > character line limit. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > --- > target/m68k/cpu.h | 66 +++++++++++++++++++++++++++++++---------------- > 1 file changed, 44 insertions(+), 22 deletions(-) > > diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h > index 7c3feeaf8a..ce558e9b03 100644 > --- a/target/m68k/cpu.h > +++ b/target/m68k/cpu.h > @@ -475,36 +475,58 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); > */ > > enum m68k_features { > - M68K_FEATURE_M68000, /* Base m68k instruction set */ > + /* Base m68k instruction set */ > + M68K_FEATURE_M68000, > M68K_FEATURE_M68010, > M68K_FEATURE_M68020, > M68K_FEATURE_M68030, > M68K_FEATURE_M68040, > M68K_FEATURE_M68060, > - M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ > - M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ > - M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ > - M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ > + /* Base Coldfire set Rev A. */ > + M68K_FEATURE_CF_ISA_A, > + /* (ISA B or C). */ > + M68K_FEATURE_CF_ISA_B, > + /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ > + M68K_FEATURE_CF_ISA_APLUSC, > + /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ > + M68K_FEATURE_BRAL, > M68K_FEATURE_CF_FPU, > M68K_FEATURE_CF_MAC, > M68K_FEATURE_CF_EMAC, > - M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ > - M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/ > - M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */ > - M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ > - M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ > - M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ > - M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ > - M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ > - M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */ > - M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ > - M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ > - M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ > - M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ > - M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ > - M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ > - M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ > - M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ > + /* Revision B EMAC (dual accumulate). */ > + M68K_FEATURE_CF_EMAC_B, > + /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ > + M68K_FEATURE_USP, > + /* Master Stack Pointer. (680[234]0) */ > + M68K_FEATURE_MSP, > + /* 68020+ full extension word. */ > + M68K_FEATURE_EXT_FULL, > + /* word sized address index registers. */ > + M68K_FEATURE_WORD_INDEX, > + /* scaled address index registers. */ > + M68K_FEATURE_SCALED_INDEX, > + /* 32 bit mul/div. (680[2346]0, and CPU32) */ > + M68K_FEATURE_LONG_MULDIV, > + /* 64 bit mul/div. (680[2346]0, and CPU32) */ > + M68K_FEATURE_QUAD_MULDIV, > + /* Bcc with Long branches. (680[2346]0, and CPU32) */ > + M68K_FEATURE_BCCL, > + /* BFxxx Bit field insns. (680[2346]0) */ > + M68K_FEATURE_BITFIELD, > + /* fpu insn. (680[46]0) */ > + M68K_FEATURE_FPU, > + /* CAS/CAS2[WL] insns. (680[2346]0) */ > + M68K_FEATURE_CAS, > + /* BKPT insn. (680[12346]0, and CPU32) */ > + M68K_FEATURE_BKPT, > + /* RTD insn. (680[12346]0, and CPU32) */ > + M68K_FEATURE_RTD, > + /* CHK2 insn. (680[2346]0, and CPU32) */ > + M68K_FEATURE_CHK2, > + /* MOVEP insn. (680[01234]0, and CPU32) */ > + M68K_FEATURE_MOVEP, > + /* MOVEC insn. (from 68010) */ > + M68K_FEATURE_MOVEC, > }; > > static inline int m68k_feature(CPUM68KState *env, int feature) > Reviewed-by: Laurent Vivier <laurent@vivier.eu> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] target/m68k: reformat m68k_features enum 2021-03-08 12:11 ` [PATCH v2 2/3] target/m68k: reformat m68k_features enum Mark Cave-Ayland 2021-03-08 17:33 ` Laurent Vivier @ 2021-03-09 14:21 ` Richard Henderson 2021-03-09 19:46 ` Laurent Vivier 2 siblings, 0 replies; 10+ messages in thread From: Richard Henderson @ 2021-03-09 14:21 UTC (permalink / raw) To: Mark Cave-Ayland, qemu-devel, laurent On 3/8/21 4:11 AM, Mark Cave-Ayland wrote: > Move the feature comment from after the feature name to the preceding line to > allow for longer feature names and descriptions without hitting the 80 > character line limit. > > Signed-off-by: Mark Cave-Ayland<mark.cave-ayland@ilande.co.uk> > --- Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] target/m68k: reformat m68k_features enum 2021-03-08 12:11 ` [PATCH v2 2/3] target/m68k: reformat m68k_features enum Mark Cave-Ayland 2021-03-08 17:33 ` Laurent Vivier 2021-03-09 14:21 ` Richard Henderson @ 2021-03-09 19:46 ` Laurent Vivier 2 siblings, 0 replies; 10+ messages in thread From: Laurent Vivier @ 2021-03-09 19:46 UTC (permalink / raw) To: Mark Cave-Ayland, qemu-devel Le 08/03/2021 à 13:11, Mark Cave-Ayland a écrit : > Move the feature comment from after the feature name to the preceding line to > allow for longer feature names and descriptions without hitting the 80 > character line limit. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > --- > target/m68k/cpu.h | 66 +++++++++++++++++++++++++++++++---------------- > 1 file changed, 44 insertions(+), 22 deletions(-) > > diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h > index 7c3feeaf8a..ce558e9b03 100644 > --- a/target/m68k/cpu.h > +++ b/target/m68k/cpu.h > @@ -475,36 +475,58 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); > */ > > enum m68k_features { > - M68K_FEATURE_M68000, /* Base m68k instruction set */ > + /* Base m68k instruction set */ > + M68K_FEATURE_M68000, > M68K_FEATURE_M68010, > M68K_FEATURE_M68020, > M68K_FEATURE_M68030, > M68K_FEATURE_M68040, > M68K_FEATURE_M68060, > - M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ > - M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ > - M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ > - M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ > + /* Base Coldfire set Rev A. */ > + M68K_FEATURE_CF_ISA_A, > + /* (ISA B or C). */ > + M68K_FEATURE_CF_ISA_B, > + /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ > + M68K_FEATURE_CF_ISA_APLUSC, > + /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ > + M68K_FEATURE_BRAL, > M68K_FEATURE_CF_FPU, > M68K_FEATURE_CF_MAC, > M68K_FEATURE_CF_EMAC, > - M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ > - M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/ > - M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */ > - M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ > - M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ > - M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ > - M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ > - M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ > - M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */ > - M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ > - M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ > - M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ > - M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ > - M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ > - M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ > - M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ > - M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ > + /* Revision B EMAC (dual accumulate). */ > + M68K_FEATURE_CF_EMAC_B, > + /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ > + M68K_FEATURE_USP, > + /* Master Stack Pointer. (680[234]0) */ > + M68K_FEATURE_MSP, > + /* 68020+ full extension word. */ > + M68K_FEATURE_EXT_FULL, > + /* word sized address index registers. */ > + M68K_FEATURE_WORD_INDEX, > + /* scaled address index registers. */ > + M68K_FEATURE_SCALED_INDEX, > + /* 32 bit mul/div. (680[2346]0, and CPU32) */ > + M68K_FEATURE_LONG_MULDIV, > + /* 64 bit mul/div. (680[2346]0, and CPU32) */ > + M68K_FEATURE_QUAD_MULDIV, > + /* Bcc with Long branches. (680[2346]0, and CPU32) */ > + M68K_FEATURE_BCCL, > + /* BFxxx Bit field insns. (680[2346]0) */ > + M68K_FEATURE_BITFIELD, > + /* fpu insn. (680[46]0) */ > + M68K_FEATURE_FPU, > + /* CAS/CAS2[WL] insns. (680[2346]0) */ > + M68K_FEATURE_CAS, > + /* BKPT insn. (680[12346]0, and CPU32) */ > + M68K_FEATURE_BKPT, > + /* RTD insn. (680[12346]0, and CPU32) */ > + M68K_FEATURE_RTD, > + /* CHK2 insn. (680[2346]0, and CPU32) */ > + M68K_FEATURE_CHK2, > + /* MOVEP insn. (680[01234]0, and CPU32) */ > + M68K_FEATURE_MOVEP, > + /* MOVEC insn. (from 68010) */ > + M68K_FEATURE_MOVEC, > }; > > static inline int m68k_feature(CPUM68KState *env, int feature) > Applied to my m68k-for-6.0 branch Thanks, Laurent ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature 2021-03-08 12:11 [PATCH v2 0/3] target/m68k: MacOS related fixes Mark Cave-Ayland 2021-03-08 12:11 ` [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland 2021-03-08 12:11 ` [PATCH v2 2/3] target/m68k: reformat m68k_features enum Mark Cave-Ayland @ 2021-03-08 12:11 ` Mark Cave-Ayland 2021-03-09 14:21 ` Richard Henderson 2021-03-09 19:47 ` Laurent Vivier 2 siblings, 2 replies; 10+ messages in thread From: Mark Cave-Ayland @ 2021-03-08 12:11 UTC (permalink / raw) To: qemu-devel, laurent According to the M68040UM Appendix D the requirement for data accesses to be word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the 68020 onwards will allow unaligned data accesses but at the cost of being less efficient. Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are not required to be word aligned, and don't perform the alignment on the stack pointer when taking an exception if this feature is not selected. This is required because the MacOS DAFB driver attempts to call an A-trap with a byte-aligned stack pointer during initialisation and without this the stack pointer is off by one when the A-trap returns. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> --- target/m68k/cpu.c | 1 + target/m68k/cpu.h | 2 ++ target/m68k/op_helper.c | 5 ++++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc7..a14874b4da 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -161,6 +161,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CAS); m68k_set_feature(env, M68K_FEATURE_CHK2); m68k_set_feature(env, M68K_FEATURE_MSP); + m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); } /* diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ce558e9b03..402c86c876 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -527,6 +527,8 @@ enum m68k_features { M68K_FEATURE_MOVEP, /* MOVEC insn. (from 68010) */ M68K_FEATURE_MOVEC, + /* Unaligned data accesses (680[2346]0) */ + M68K_FEATURE_UNALIGNED_DATA, }; static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 59a6448296..3fa7b7e19e 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -348,7 +348,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) cpu_m68k_set_sr(env, sr); sp = env->aregs[7]; - sp &= ~1; + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { + sp &= ~1; + } + if (cs->exception_index == EXCP_ACCESS) { if (env->mmu.fault) { cpu_abort(cs, "DOUBLE MMU FAULT\n"); -- 2.20.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature 2021-03-08 12:11 ` [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Mark Cave-Ayland @ 2021-03-09 14:21 ` Richard Henderson 2021-03-09 19:47 ` Laurent Vivier 1 sibling, 0 replies; 10+ messages in thread From: Richard Henderson @ 2021-03-09 14:21 UTC (permalink / raw) To: Mark Cave-Ayland, qemu-devel, laurent On 3/8/21 4:11 AM, Mark Cave-Ayland wrote: > According to the M68040UM Appendix D the requirement for data accesses to be > word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the > 68020 onwards will allow unaligned data accesses but at the cost of being less > efficient. > > Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are > not required to be word aligned, and don't perform the alignment on the stack > pointer when taking an exception if this feature is not selected. > > This is required because the MacOS DAFB driver attempts to call an A-trap > with a byte-aligned stack pointer during initialisation and without this the > stack pointer is off by one when the A-trap returns. > > Signed-off-by: Mark Cave-Ayland<mark.cave-ayland@ilande.co.uk> > Reviewed-by: Laurent Vivier<laurent@vivier.eu> > --- Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature 2021-03-08 12:11 ` [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Mark Cave-Ayland 2021-03-09 14:21 ` Richard Henderson @ 2021-03-09 19:47 ` Laurent Vivier 1 sibling, 0 replies; 10+ messages in thread From: Laurent Vivier @ 2021-03-09 19:47 UTC (permalink / raw) To: Mark Cave-Ayland, qemu-devel Le 08/03/2021 à 13:11, Mark Cave-Ayland a écrit : > According to the M68040UM Appendix D the requirement for data accesses to be > word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the > 68020 onwards will allow unaligned data accesses but at the cost of being less > efficient. > > Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are > not required to be word aligned, and don't perform the alignment on the stack > pointer when taking an exception if this feature is not selected. > > This is required because the MacOS DAFB driver attempts to call an A-trap > with a byte-aligned stack pointer during initialisation and without this the > stack pointer is off by one when the A-trap returns. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Reviewed-by: Laurent Vivier <laurent@vivier.eu> > --- > target/m68k/cpu.c | 1 + > target/m68k/cpu.h | 2 ++ > target/m68k/op_helper.c | 5 ++++- > 3 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c > index 37d2ed9dc7..a14874b4da 100644 > --- a/target/m68k/cpu.c > +++ b/target/m68k/cpu.c > @@ -161,6 +161,7 @@ static void m68020_cpu_initfn(Object *obj) > m68k_set_feature(env, M68K_FEATURE_CAS); > m68k_set_feature(env, M68K_FEATURE_CHK2); > m68k_set_feature(env, M68K_FEATURE_MSP); > + m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); > } > > /* > diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h > index ce558e9b03..402c86c876 100644 > --- a/target/m68k/cpu.h > +++ b/target/m68k/cpu.h > @@ -527,6 +527,8 @@ enum m68k_features { > M68K_FEATURE_MOVEP, > /* MOVEC insn. (from 68010) */ > M68K_FEATURE_MOVEC, > + /* Unaligned data accesses (680[2346]0) */ > + M68K_FEATURE_UNALIGNED_DATA, > }; > > static inline int m68k_feature(CPUM68KState *env, int feature) > diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c > index 59a6448296..3fa7b7e19e 100644 > --- a/target/m68k/op_helper.c > +++ b/target/m68k/op_helper.c > @@ -348,7 +348,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) > cpu_m68k_set_sr(env, sr); > sp = env->aregs[7]; > > - sp &= ~1; > + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { > + sp &= ~1; > + } > + > if (cs->exception_index == EXCP_ACCESS) { > if (env->mmu.fault) { > cpu_abort(cs, "DOUBLE MMU FAULT\n"); > Applied to my m68k-for-6.0 branch Thanks, Laurent ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-03-09 20:42 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-08 12:11 [PATCH v2 0/3] target/m68k: MacOS related fixes Mark Cave-Ayland 2021-03-08 12:11 ` [PATCH v2 1/3] target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland 2021-03-09 19:46 ` Laurent Vivier 2021-03-08 12:11 ` [PATCH v2 2/3] target/m68k: reformat m68k_features enum Mark Cave-Ayland 2021-03-08 17:33 ` Laurent Vivier 2021-03-09 14:21 ` Richard Henderson 2021-03-09 19:46 ` Laurent Vivier 2021-03-08 12:11 ` [PATCH v2 3/3] target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Mark Cave-Ayland 2021-03-09 14:21 ` Richard Henderson 2021-03-09 19:47 ` Laurent Vivier
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