From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Fredrik Noring" <noring@nocrew.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [RFC PATCH v2 21/22] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()
Date: Tue, 9 Mar 2021 15:56:52 +0100 [thread overview]
Message-ID: <20210309145653.743937-22-f4bug@amsat.org> (raw)
In-Reply-To: <20210309145653.743937-1-f4bug@amsat.org>
Now than SQ is properly implemented, we can move the RDHWR
kludge required to have usermode working with recent glibc.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: { RDHWR_user } (rth)
---
target/mips/tx79.decode | 5 +++-
target/mips/translate.c | 56 ------------------------------------
target/mips/tx79_translate.c | 31 ++++++++++++++++++++
3 files changed, 35 insertions(+), 57 deletions(-)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index f1cb7ebfa3c..4e8acb7ab9a 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -73,4 +73,7 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
# SPECIAL
LQ 011110 ..... ..... ................ @ldst
-SQ 011111 ..... ..... ................ @ldst
+{
+ RDHWR_user 011111 00000 ..... ..... 00000 111011 @rt_rd
+ SQ 011111 ..... ..... ................ @ldst
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0d20a0e3b84..b01022a6ad7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1167,7 +1167,6 @@ enum {
enum {
MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
- MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
/*
@@ -24428,53 +24427,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
}
}
-static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
-{
- gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
-}
-
-/*
- * The TX79-specific instruction Store Quadword
- *
- * +--------+-------+-------+------------------------+
- * | 011111 | base | rt | offset | SQ
- * +--------+-------+-------+------------------------+
- * 6 5 5 16
- *
- * has the same opcode as the Read Hardware Register instruction
- *
- * +--------+-------+-------+-------+-------+--------+
- * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
- * +--------+-------+-------+-------+-------+--------+
- * 6 5 5 5 5 6
- *
- * that is required, trapped and emulated by the Linux kernel. However, all
- * RDHWR encodings yield address error exceptions on the TX79 since the SQ
- * offset is odd. Therefore all valid SQ instructions can execute normally.
- * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
- * between SQ and RDHWR, as the Linux kernel does.
- */
-static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
-{
- int base = extract32(ctx->opcode, 21, 5);
- int rt = extract32(ctx->opcode, 16, 5);
- int offset = extract32(ctx->opcode, 0, 16);
-
-#ifdef CONFIG_USER_ONLY
- uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
- uint32_t op2 = extract32(ctx->opcode, 6, 5);
-
- if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
- int rd = extract32(ctx->opcode, 11, 5);
-
- gen_rdhwr(ctx, rt, rd, 0);
- return;
- }
-#endif
-
- gen_mmi_sq(ctx, base, rt, offset);
-}
-
#endif
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
@@ -24664,15 +24616,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special2_legacy(env, ctx);
break;
case OPC_SPECIAL3:
-#if defined(TARGET_MIPS64)
- if (ctx->insn_flags & INSN_R5900) {
- decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
- } else {
- decode_opc_special3(env, ctx);
- }
-#else
decode_opc_special3(env, ctx);
-#endif
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index e32c6218852..5e69783420a 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -396,6 +396,37 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a)
return true;
}
+/*
+ * The TX79-specific instruction Store Quadword
+ *
+ * +--------+-------+-------+------------------------+
+ * | 011111 | base | rt | offset | SQ
+ * +--------+-------+-------+------------------------+
+ * 6 5 5 16
+ *
+ * has the same opcode as the Read Hardware Register instruction
+ *
+ * +--------+-------+-------+-------+-------+--------+
+ * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
+ * +--------+-------+-------+-------+-------+--------+
+ * 6 5 5 5 5 6
+ *
+ * that is required, trapped and emulated by the Linux kernel. However, all
+ * RDHWR encodings yield address error exceptions on the TX79 since the SQ
+ * offset is odd. Therefore all valid SQ instructions can execute normally.
+ * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
+ * between SQ and RDHWR, as the Linux kernel does.
+ */
+static bool trans_RDHWR_user(DisasContext *ctx, arg_rtype *a)
+{
+#if defined(CONFIG_USER_ONLY)
+ gen_rdhwr(ctx, a->rt, a->rd, 0);
+ return true;
+#else
+ return false;
+#endif
+}
+
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
--
2.26.2
next prev parent reply other threads:[~2021-03-09 15:47 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-09 14:56 [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing) Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 01/22] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 02/22] target/mips/tx79: Move MTHI1 / MTLO1 " Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 03/22] target/mips/translate: Make gen_rdhwr() public Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 04/22] target/mips/translate: Simplify PCPYH using deposit_i64() Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 05/22] target/mips/tx79: Move PCPYH opcode to decodetree Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 06/22] target/mips/tx79: Move PCPYLD / PCPYUD opcodes " Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 07/22] target/mips: Remove 'C790 Multimedia Instructions' dead code Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 08/22] target/mips/tx79: Salvage instructions description comment Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 09/22] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 10/22] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Philippe Mathieu-Daudé
2021-03-13 14:04 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 11/22] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Philippe Mathieu-Daudé
2021-03-13 14:04 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 12/22] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) Philippe Mathieu-Daudé
2021-03-13 14:08 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 13/22] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Philippe Mathieu-Daudé
2021-03-13 14:09 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 14/22] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Philippe Mathieu-Daudé
2021-03-13 14:10 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 15/22] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 16/22] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) Philippe Mathieu-Daudé
2021-03-13 14:11 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 17/22] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even) Philippe Mathieu-Daudé
2021-03-13 14:13 ` Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 18/22] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 19/22] target/mips/tx79: Introduce LQ opcode (Load Quadword) Philippe Mathieu-Daudé
2021-03-09 14:56 ` [RFC PATCH v2 20/22] target/mips/tx79: Introduce SQ opcode (Store Quadword) Philippe Mathieu-Daudé
2021-03-09 14:56 ` Philippe Mathieu-Daudé [this message]
2021-03-13 15:21 ` [RFC PATCH v2 21/22] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() Richard Henderson
2021-03-09 14:56 ` [RFC PATCH v2 22/22] target/mips: Reintroduce the R5900 CPU Philippe Mathieu-Daudé
2021-03-12 0:01 ` [RFC PATCH v2 00/22] target/mips: Reintroduce the R5900 CPU (without testing) Philippe Mathieu-Daudé
2021-07-11 20:27 ` Philippe Mathieu-Daudé
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