From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 7/7] target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
Date: Sun, 14 Mar 2021 14:55:13 +0100 [thread overview]
Message-ID: <20210314135513.1369871-8-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20210314135513.1369871-1-kbastian@mail.uni-paderborn.de>
if width was 0 we would run into the assertion:
qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o
The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 5b7ed70e39..2a814263de 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7000,6 +7000,11 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RRPW_EXTR:
+ if (width == 0) {
+ tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
+ break;
+ }
+
if (pos + width <= 32) {
/* optimize special cases */
if ((pos == 0) && (width == 8)) {
--
2.30.1
next prev parent reply other threads:[~2021-03-14 14:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-14 13:55 [PULL 0/7] tricore queue Bastian Koppelmann
2021-03-14 13:55 ` [PULL 1/7] tricore: added triboard with tc27x_soc Bastian Koppelmann
2021-03-14 13:55 ` [PULL 2/7] target/tricore: Replace magic value by MMU_DATA_LOAD definition Bastian Koppelmann
2021-03-14 13:55 ` [PULL 3/7] target/tricore: Pass MMUAccessType to get_physical_address() Bastian Koppelmann
2021-03-14 13:55 ` [PULL 4/7] target/tricore: Remove unused definitions Bastian Koppelmann
2021-03-14 13:55 ` [PULL 5/7] tricore: fixed faulty conditions for extr and imask Bastian Koppelmann
2021-03-14 13:55 ` [PULL 6/7] target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 Bastian Koppelmann
2021-03-14 13:55 ` Bastian Koppelmann [this message]
2021-03-15 16:53 ` [PULL 0/7] tricore queue Peter Maydell
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