* [PATCH V4] target/riscv: Align the data type of reset vector address
@ 2021-03-29 3:38 Dylan Jhong
2021-03-30 18:29 ` Alistair Francis
0 siblings, 1 reply; 2+ messages in thread
From: Dylan Jhong @ 2021-03-29 3:38 UTC (permalink / raw)
To: qemu-riscv, qemu-devel, kbastian, sagark, Alistair.Francis, palmer
Cc: peter.maydell, alankao, Dylan Jhong, x5710999x, ruinland, bmeng.cn
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
---
target/riscv/cpu.c | 5 +++--
target/riscv/cpu.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..268945d8a9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
env->features |= (1ULL << feature);
}
-static void set_resetvec(CPURISCVState *env, int resetvec)
+static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
env->resetvec = resetvec;
@@ -554,7 +554,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+ DEFINE_PROP_UNSIGNED("resetvec", RISCVCPU, cfg.resetvec,
+ DEFAULT_RSTVEC, qdev_prop_uint64, target_ulong),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba..d9d7891666 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -303,7 +303,7 @@ struct RISCVCPU {
uint16_t elen;
bool mmu;
bool pmp;
- uint64_t resetvec;
+ target_ulong resetvec;
} cfg;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH V4] target/riscv: Align the data type of reset vector address
2021-03-29 3:38 [PATCH V4] target/riscv: Align the data type of reset vector address Dylan Jhong
@ 2021-03-30 18:29 ` Alistair Francis
0 siblings, 0 replies; 2+ messages in thread
From: Alistair Francis @ 2021-03-30 18:29 UTC (permalink / raw)
To: Dylan Jhong
Cc: Peter Maydell, open list:RISC-V, Alan Quey-Liang Kao((((((((((),
Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis, x5710999x,
Ruinland Chuan-Tzu Tsa((((((((((),
Palmer Dabbelt, Bin Meng
On Sun, Mar 28, 2021 at 11:39 PM Dylan Jhong <dylan@andestech.com> wrote:
>
> Use target_ulong to instead of uint64_t on reset vector address
> to adapt on both 32/64 machine.
>
> Signed-off-by: Dylan Jhong <dylan@andestech.com>
> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 5 +++--
> target/riscv/cpu.h | 2 +-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7d6ed80f6b..268945d8a9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
> env->features |= (1ULL << feature);
> }
>
> -static void set_resetvec(CPURISCVState *env, int resetvec)
> +static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
> {
> #ifndef CONFIG_USER_ONLY
> env->resetvec = resetvec;
> @@ -554,7 +554,8 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> + DEFINE_PROP_UNSIGNED("resetvec", RISCVCPU, cfg.resetvec,
> + DEFAULT_RSTVEC, qdev_prop_uint64, target_ulong),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0a33d387ba..d9d7891666 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -303,7 +303,7 @@ struct RISCVCPU {
> uint16_t elen;
> bool mmu;
> bool pmp;
> - uint64_t resetvec;
> + target_ulong resetvec;
> } cfg;
> };
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-03-30 18:32 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-29 3:38 [PATCH V4] target/riscv: Align the data type of reset vector address Dylan Jhong
2021-03-30 18:29 ` Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).