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* [PULL for-6.0 0/2] tcg patch queue
@ 2021-04-05 14:40 Richard Henderson
  2021-04-05 14:40 ` [PULL for-6.0 1/2] tcg/mips: Fix SoftTLB comparison on mips backend Richard Henderson
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Richard Henderson @ 2021-04-05 14:40 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell

Folding in a target/alpha patch since both queues
are singletons this time.


r~


The following changes since commit 25d75c99b2e5941c67049ee776efdb226414f4c6:

  Merge remote-tracking branch 'remotes/xtensa/tags/20210403-xtensa' into staging (2021-04-04 21:48:45 +0100)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210405

for you to fetch changes up to ef951ee33fba780dd6c2b7f8ff25c84c3f87a6b8:

  target/alpha: fix icount handling for timer instructions (2021-04-05 07:32:56 -0700)

----------------------------------------------------------------
tcg/mips tlb lookup fix
target/alpha icount fix

----------------------------------------------------------------
Kele Huang (1):
      tcg/mips: Fix SoftTLB comparison on mips backend

Pavel Dovgalyuk (1):
      target/alpha: fix icount handling for timer instructions

 target/alpha/translate.c  | 9 +++++++--
 tcg/mips/tcg-target.c.inc | 2 +-
 2 files changed, 8 insertions(+), 3 deletions(-)


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PULL for-6.0 1/2] tcg/mips: Fix SoftTLB comparison on mips backend
  2021-04-05 14:40 [PULL for-6.0 0/2] tcg patch queue Richard Henderson
@ 2021-04-05 14:40 ` Richard Henderson
  2021-04-05 14:40 ` [PULL for-6.0 2/2] target/alpha: fix icount handling for timer instructions Richard Henderson
  2021-04-05 21:14 ` [PULL for-6.0 0/2] tcg patch queue Peter Maydell
  2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2021-04-05 14:40 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Alex Bennée, Kele Huang, Philippe Mathieu-Daudé

From: Kele Huang <kele.hwang@gmail.com>

The addrl used to compare with SoftTLB entry should be sign-extended
in common case, and it will cause constant failing in SoftTLB
comparisons for the addrl whose address is over 0x80000000 on the
emulation of 32-bit guest on 64-bit host.

This is an important performance bug fix. Spec2000 gzip rate increase
from ~45 to ~140 on Loongson 3A4000 (MIPS compatible platform).

Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210401100457.191458-1-kele.hwang@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/mips/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 8738a3a581..8b16726242 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1201,13 +1201,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
            load the tlb addend for the fast path.  */
         tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
     }
-    tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
 
     /* Zero extend a 32-bit guest address for a 64-bit host. */
     if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
         tcg_out_ext32u(s, base, addrl);
         addrl = base;
     }
+    tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
 
     label_ptr[0] = s->code_ptr;
     tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
-- 
2.25.1



^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PULL for-6.0 2/2] target/alpha: fix icount handling for timer instructions
  2021-04-05 14:40 [PULL for-6.0 0/2] tcg patch queue Richard Henderson
  2021-04-05 14:40 ` [PULL for-6.0 1/2] tcg/mips: Fix SoftTLB comparison on mips backend Richard Henderson
@ 2021-04-05 14:40 ` Richard Henderson
  2021-04-05 21:14 ` [PULL for-6.0 0/2] tcg patch queue Peter Maydell
  2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2021-04-05 14:40 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Pavel Dovgalyuk

From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>

This patch handles icount mode for timer read/write instructions,
because it is required to call gen_io_start in such cases.

Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <161700373035.1135822.16451510827008616793.stgit@pasha-ThinkPad-X280>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/translate.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index a02b4e70b7..f454adea5e 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -1330,7 +1330,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
     case 249: /* VMTIME */
         helper = gen_helper_get_vmtime;
     do_helper:
-        if (icount_enabled()) {
+        if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
             gen_io_start();
             helper(va);
             return DISAS_PC_STALE;
@@ -1366,6 +1366,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
 static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
 {
     int data;
+    DisasJumpType ret = DISAS_NEXT;
 
     switch (regno) {
     case 255:
@@ -1395,6 +1396,10 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
 
     case 251:
         /* ALARM */
+        if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+            gen_io_start();
+            ret = DISAS_PC_STALE;
+        }
         gen_helper_set_alarm(cpu_env, vb);
         break;
 
@@ -1434,7 +1439,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
         break;
     }
 
-    return DISAS_NEXT;
+    return ret;
 }
 #endif /* !USER_ONLY*/
 
-- 
2.25.1



^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PULL for-6.0 0/2] tcg patch queue
  2021-04-05 14:40 [PULL for-6.0 0/2] tcg patch queue Richard Henderson
  2021-04-05 14:40 ` [PULL for-6.0 1/2] tcg/mips: Fix SoftTLB comparison on mips backend Richard Henderson
  2021-04-05 14:40 ` [PULL for-6.0 2/2] target/alpha: fix icount handling for timer instructions Richard Henderson
@ 2021-04-05 21:14 ` Peter Maydell
  2 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2021-04-05 21:14 UTC (permalink / raw)
  To: Richard Henderson; +Cc: QEMU Developers

On Mon, 5 Apr 2021 at 15:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Folding in a target/alpha patch since both queues
> are singletons this time.
>
>
> r~
>
>
> The following changes since commit 25d75c99b2e5941c67049ee776efdb226414f4c6:
>
>   Merge remote-tracking branch 'remotes/xtensa/tags/20210403-xtensa' into staging (2021-04-04 21:48:45 +0100)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210405
>
> for you to fetch changes up to ef951ee33fba780dd6c2b7f8ff25c84c3f87a6b8:
>
>   target/alpha: fix icount handling for timer instructions (2021-04-05 07:32:56 -0700)
>
> ----------------------------------------------------------------
> tcg/mips tlb lookup fix
> target/alpha icount fix


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-04-05 21:16 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-05 14:40 [PULL for-6.0 0/2] tcg patch queue Richard Henderson
2021-04-05 14:40 ` [PULL for-6.0 1/2] tcg/mips: Fix SoftTLB comparison on mips backend Richard Henderson
2021-04-05 14:40 ` [PULL for-6.0 2/2] target/alpha: fix icount handling for timer instructions Richard Henderson
2021-04-05 21:14 ` [PULL for-6.0 0/2] tcg patch queue Peter Maydell

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