From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Kumar Gala <kumar.gala@linaro.org>,
Kevin Townsend <kevin.townsend@linaro.org>
Subject: [PATCH 2/3] hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
Date: Mon, 12 Apr 2021 14:43:16 +0100 [thread overview]
Message-ID: <20210412134317.12501-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210412134317.12501-1-peter.maydell@linaro.org>
On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
* a device property scc-cfg0 so the board can specify the
initial value of the CFG0 register
* an outbound GPIO line which tracks bit 0 and which the board
can wire up to provide the remapping
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/mps2-scc.h | 9 +++++++++
hw/misc/mps2-scc.c | 13 ++++++++++---
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
index ea261ea30d6..3b2d13ac9c3 100644
--- a/include/hw/misc/mps2-scc.h
+++ b/include/hw/misc/mps2-scc.h
@@ -18,8 +18,14 @@
* + QOM property "scc-cfg4": value of the read-only CFG4 register
* + QOM property "scc-aid": value of the read-only SCC_AID register
* + QOM property "scc-id": value of the read-only SCC_ID register
+ * + QOM property "scc-cfg0": reset value of the CFG0 register
* + QOM property array "oscclk": reset values of the OSCCLK registers
* (which are accessed via the SYS_CFG channel provided by this device)
+ * + named GPIO output "remap": this tracks the value of CFG0 register
+ * bit 0. Boards where this bit controls memory remapping should
+ * connect this GPIO line to a function performing that mapping.
+ * Boards where bit 0 has no special function should leave the GPIO
+ * output disconnected.
*/
#ifndef MPS2_SCC_H
#define MPS2_SCC_H
@@ -55,6 +61,9 @@ struct MPS2SCC {
uint32_t num_oscclk;
uint32_t *oscclk;
uint32_t *oscclk_reset;
+ uint32_t cfg0_reset;
+
+ qemu_irq remap;
};
#endif
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index c56aca86ad5..b3b42a792cd 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -23,6 +23,7 @@
#include "qemu/bitops.h"
#include "trace.h"
#include "hw/sysbus.h"
+#include "hw/irq.h"
#include "migration/vmstate.h"
#include "hw/registerfields.h"
#include "hw/misc/mps2-scc.h"
@@ -186,10 +187,13 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
switch (offset) {
case A_CFG0:
/*
- * TODO on some boards bit 0 controls RAM remapping;
- * on others bit 1 is CPU_WAIT.
+ * On some boards bit 0 controls board-specific remapping;
+ * we always reflect bit 0 in the 'remap' GPIO output line,
+ * and let the board wire it up or not as it chooses.
+ * TODO on some boards bit 1 is CPU_WAIT.
*/
s->cfg0 = value;
+ qemu_set_irq(s->remap, s->cfg0 & 1);
break;
case A_CFG1:
s->cfg1 = value;
@@ -283,7 +287,7 @@ static void mps2_scc_reset(DeviceState *dev)
int i;
trace_mps2_scc_reset();
- s->cfg0 = 0;
+ s->cfg0 = s->cfg0_reset;
s->cfg1 = 0;
s->cfg2 = 0;
s->cfg5 = 0;
@@ -308,6 +312,7 @@ static void mps2_scc_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
+ qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1);
}
static void mps2_scc_realize(DeviceState *dev, Error **errp)
@@ -353,6 +358,8 @@ static Property mps2_scc_properties[] = {
DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
+ /* Reset value for CFG0 register */
+ DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0),
/*
* These are the initial settings for the source clocks on the board.
* In hardware they can be configured via a config file read by the
--
2.20.1
next prev parent reply other threads:[~2021-04-12 13:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 13:43 [PATCH 0/3] mps3-an524: support memory remapping Peter Maydell
2021-04-12 13:43 ` [PATCH 1/3] hw/misc/mps2-scc: Add "QEMU interface" comment Peter Maydell
2021-04-12 13:43 ` Peter Maydell [this message]
2021-04-13 16:30 ` [PATCH 2/3] hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping Philippe Mathieu-Daudé
2021-04-12 13:43 ` [PATCH 3/3] hw/arm/mps2-tz: Implement AN524 memory remapping via machine property Peter Maydell
2021-04-13 16:51 ` Philippe Mathieu-Daudé
2021-04-12 14:37 ` [PATCH 0/3] mps3-an524: support memory remapping Philippe Mathieu-Daudé
2021-04-12 14:48 ` Peter Maydell
2021-04-13 16:29 ` Philippe Mathieu-Daudé
2021-04-13 16:33 ` Philippe Mathieu-Daudé
2021-04-12 18:39 ` Richard Henderson
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