From: Luis Pires <luis.pires@eldorado.org.br>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: richard.henderson@linaro.org, f4bug@amsat.org,
Luis Pires <luis.pires@eldorado.org.br>,
lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br,
matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH 5/5] target/ppc: Implement paddi and replace addi insns
Date: Tue, 13 Apr 2021 18:11:29 -0300 [thread overview]
Message-ID: <20210413211129.457272-6-luis.pires@eldorado.org.br> (raw)
In-Reply-To: <20210413211129.457272-1-luis.pires@eldorado.org.br>
This implements the Power ISA 3.1 prefixed (64-bit) paddi
instruction, while also replacing the legacy addi implementation.
Both using the decode tree.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/ppc.decode | 8 +++++++
target/ppc/translate.c | 15 +------------
target/ppc/translate/fixedpoint-impl.c.inc | 26 ++++++++++++++++++++++
3 files changed, 35 insertions(+), 14 deletions(-)
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
diff --git a/target/ppc/ppc.decode b/target/ppc/ppc.decode
index 84bb73ac19..c87174dc20 100644
--- a/target/ppc/ppc.decode
+++ b/target/ppc/ppc.decode
@@ -16,3 +16,11 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+%p_D8_SI 32:s18 0:16
+
+# Fixed-Point Facility Instructions
+&addi r rt ra si
+
+paddi 000001 10 0 -- r:1 -- .................. 001110 rt:5 ra:5 ................ si=%p_D8_SI &addi
+addi 001110 rt:5 ra:5 si:s16 &addi r=0
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0f123f7b80..2ff192c9e5 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -945,19 +945,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
/* addze addze. addzeo addzeo.*/
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addi */
-static void gen_addi(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* li case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm);
- }
-}
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
@@ -6967,6 +6954,7 @@ static target_ulong ppc_peek_next_insn_size(DisasContext *ctx)
}
#include "decode-ppc.c.inc"
+#include "translate/fixedpoint-impl.c.inc"
#include "translate/fp-impl.c.inc"
@@ -7091,7 +7079,6 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
new file mode 100644
index 0000000000..8620954b57
--- /dev/null
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -0,0 +1,26 @@
+static bool trans_paddi(DisasContext *ctx, arg_paddi *a)
+{
+ if (a->r == 0) {
+ if (a->ra == 0) {
+ /* li case */
+ tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
+ } else {
+ tcg_gen_addi_tl(cpu_gpr[a->rt],
+ cpu_gpr[a->ra], a->si);
+ }
+ } else {
+ if (a->ra == 0) {
+ tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_nip, a->si);
+ } else {
+ /* invalid form */
+ gen_invalid(ctx);
+ }
+ }
+
+ return true;
+}
+
+static bool trans_addi(DisasContext *ctx, arg_addi *a)
+{
+ return trans_paddi(ctx, a);
+}
--
2.25.1
next prev parent reply other threads:[~2021-04-13 21:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-13 21:11 [PATCH 0/5] Base for adding PowerPC 64-bit instructions Luis Pires
2021-04-13 21:11 ` [PATCH 1/5] decodetree: Add support for " Luis Pires
2021-04-13 21:11 ` [PATCH 2/5] decodetree: Fix empty input files for varinsnwidth Luis Pires
2021-04-14 19:47 ` Richard Henderson
2021-04-13 21:11 ` [PATCH 3/5] decodetree: Allow custom var width load functions Luis Pires
2021-04-13 21:11 ` [PATCH 4/5] target/ppc: Base changes to allow 32/64-bit insns Luis Pires
2021-04-14 15:26 ` Richard Henderson
2021-04-14 16:09 ` Richard Henderson
2021-04-14 16:10 ` Richard Henderson
2021-04-13 21:11 ` Luis Pires [this message]
2021-04-13 22:41 ` [PATCH 5/5] target/ppc: Implement paddi and replace addi insns Philippe Mathieu-Daudé
2021-04-14 13:00 ` Luis Fernando Fujita Pires
2021-04-14 19:11 ` Richard Henderson
2021-04-14 23:07 ` Richard Henderson
2021-04-15 16:59 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210413211129.457272-6-luis.pires@eldorado.org.br \
--to=luis.pires@eldorado.org.br \
--cc=bruno.larsen@eldorado.org.br \
--cc=david@gibson.dropbear.id.au \
--cc=f4bug@amsat.org \
--cc=lagarcia@br.ibm.com \
--cc=matheus.ferst@eldorado.org.br \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).