From: Alessandro Di Federico via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng,
nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org,
Alessandro Di Federico <ale@rev.ng>
Subject: [PATCH v4 06/12] target/hexagon: introduce new helper functions
Date: Thu, 15 Apr 2021 18:34:49 +0200 [thread overview]
Message-ID: <20210415163455.3839169-7-ale.qemu@rev.ng> (raw)
In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng>
From: Niccolò Izzo <nizzo@rev.ng>
These helpers will be employed by the idef-parser generated code.
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Niccolò Izzo <nizzo@rev.ng>
---
target/hexagon/genptr.c | 188 ++++++++++++++++++++++++++++++++++++++++
target/hexagon/genptr.h | 22 +++++
target/hexagon/macros.h | 9 ++
3 files changed, 219 insertions(+)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 1ddb4360f1..024419bf39 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -28,6 +28,12 @@
#include "gen_tcg.h"
#include "genptr.h"
+TCGv gen_read_reg(TCGv result, int num)
+{
+ tcg_gen_mov_tl(result, hex_gpr[num]);
+ return result;
+}
+
TCGv gen_read_preg(TCGv pred, uint8_t num)
{
tcg_gen_mov_tl(pred, hex_pred[num]);
@@ -330,5 +336,187 @@ static inline void gen_store_conditional8(CPUHexagonState *env,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
+void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slot)
+{
+ tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+ tcg_gen_movi_tl(hex_store_width[slot], width);
+ tcg_gen_mov_tl(hex_store_val32[slot], src);
+}
+
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ unsigned slot)
+{
+ gen_store32(vaddr, src, 1, slot);
+ ctx->store_width[slot] = 1;
+}
+
+void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ unsigned slot)
+{
+ gen_store32(vaddr, src, 2, slot);
+ ctx->store_width[slot] = 2;
+}
+
+void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ unsigned slot)
+{
+ gen_store32(vaddr, src, 4, slot);
+ ctx->store_width[slot] = 4;
+}
+
+
+void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *ctx,
+ unsigned slot)
+{
+ tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+ tcg_gen_movi_tl(hex_store_width[slot], 8);
+ tcg_gen_mov_i64(hex_store_val64[slot], src);
+ ctx->store_width[slot] = 8;
+}
+
+void gen_set_usr_field(int field, TCGv val)
+{
+ tcg_gen_deposit_tl(hex_gpr[HEX_REG_USR], hex_gpr[HEX_REG_USR], val,
+ reg_field_info[field].offset,
+ reg_field_info[field].width);
+}
+
+void gen_set_usr_fieldi(int field, int x)
+{
+ TCGv val = tcg_const_tl(x);
+ gen_set_usr_field(field, val);
+ tcg_temp_free(val);
+}
+
+void gen_write_new_pc(TCGv addr)
+{
+ /* If there are multiple branches in a packet, ignore the second one */
+ TCGv zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero,
+ hex_next_PC, addr);
+ tcg_gen_movi_tl(hex_branch_taken, 1);
+ tcg_temp_free(zero);
+}
+
+void gen_sat_i32(TCGv dest, TCGv source, int width)
+{
+ TCGv max_val = tcg_const_i32((1 << (width - 1)) - 1);
+ TCGv min_val = tcg_const_i32(-(1 << (width - 1)));
+ tcg_gen_smin_tl(dest, source, max_val);
+ tcg_gen_smax_tl(dest, dest, min_val);
+ tcg_temp_free_i32(max_val);
+ tcg_temp_free_i32(min_val);
+}
+
+void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+ gen_sat_i32(dest, source, width);
+ TCGv zero = tcg_const_i32(0);
+ TCGv one = tcg_const_i32(1);
+ tcg_gen_movcond_i32(TCG_COND_NE, ovfl, source, dest, one, zero);
+ tcg_temp_free_i32(zero);
+ tcg_temp_free_i32(one);
+}
+
+void gen_satu_i32(TCGv dest, TCGv source, int width)
+{
+ TCGv max_val = tcg_const_i32((1 << width) - 1);
+ tcg_gen_movcond_i32(TCG_COND_GTU, dest, source, max_val, max_val, source);
+ TCGv_i32 zero = tcg_const_i32(0);
+ tcg_gen_movcond_i32(TCG_COND_LT, dest, source, zero, zero, dest);
+ tcg_temp_free_i32(max_val);
+ tcg_temp_free_i32(zero);
+}
+
+void gen_satu_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+ gen_satu_i32(dest, source, width);
+ TCGv zero = tcg_const_i32(0);
+ TCGv one = tcg_const_i32(1);
+ tcg_gen_movcond_i32(TCG_COND_NE, ovfl, dest, source, one, zero);
+ tcg_temp_free_i32(zero);
+ tcg_temp_free_i32(one);
+}
+
+void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 max_val = tcg_const_i64((1 << (width - 1)) - 1);
+ TCGv_i64 min_val = tcg_const_i64(-(1 << (width - 1)));
+ tcg_gen_smin_i64(dest, source, max_val);
+ tcg_gen_smax_i64(dest, dest, min_val);
+ tcg_temp_free_i64(max_val);
+ tcg_temp_free_i64(min_val);
+}
+
+void gen_sat_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ gen_sat_i64(dest, source, width);
+ TCGv_i64 ovfl_64 = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 one = tcg_const_i64(1);
+ tcg_gen_movcond_i64(TCG_COND_NE, ovfl_64, dest, source, one, zero);
+ tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
+ tcg_temp_free_i64(ovfl_64);
+ tcg_temp_free_i64(zero);
+ tcg_temp_free_i64(one);
+}
+
+void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 max_val = tcg_const_i64((1 << width) - 1);
+ tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val, max_val, source);
+ TCGv_i64 zero = tcg_const_i64(0);
+ tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest);
+ tcg_temp_free_i64(max_val);
+ tcg_temp_free_i64(zero);
+}
+
+void gen_satu_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ gen_sat_i64(dest, source, width);
+ TCGv_i64 ovfl_64 = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 one = tcg_const_i64(1);
+ tcg_gen_movcond_i64(TCG_COND_NE, ovfl_64, dest, source, one, zero);
+ tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
+ tcg_temp_free_i64(ovfl_64);
+ tcg_temp_free_i64(zero);
+ tcg_temp_free_i64(one);
+}
+
+void gen_fbrev(TCGv result, TCGv src)
+{
+ TCGv lo = tcg_temp_new();
+ TCGv tmp1 = tcg_temp_new();
+ TCGv tmp2 = tcg_temp_new();
+
+ /* Bit reversal of low 16 bits */
+ tcg_gen_extract_tl(lo, src, 0, 16);
+ tcg_gen_andi_tl(tmp1, lo, 0xaaaa);
+ tcg_gen_shri_tl(tmp1, tmp1, 1);
+ tcg_gen_andi_tl(tmp2, lo, 0x5555);
+ tcg_gen_shli_tl(tmp2, tmp2, 1);
+ tcg_gen_or_tl(lo, tmp1, tmp2);
+ tcg_gen_andi_tl(tmp1, lo, 0xcccc);
+ tcg_gen_shri_tl(tmp1, tmp1, 2);
+ tcg_gen_andi_tl(tmp2, lo, 0x3333);
+ tcg_gen_shli_tl(tmp2, tmp2, 2);
+ tcg_gen_or_tl(lo, tmp1, tmp2);
+ tcg_gen_andi_tl(tmp1, lo, 0xf0f0);
+ tcg_gen_shri_tl(tmp1, tmp1, 4);
+ tcg_gen_andi_tl(tmp2, lo, 0x0f0f);
+ tcg_gen_shli_tl(tmp2, tmp2, 4);
+ tcg_gen_or_tl(lo, tmp1, tmp2);
+ tcg_gen_bswap16_tl(lo, lo);
+
+ /* Final tweaks */
+ tcg_gen_deposit_tl(result, src, lo, 0, 16);
+ tcg_gen_or_tl(result, result, lo);
+
+ tcg_temp_free(lo);
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+}
+
#include "tcg_funcs_generated.c.inc"
#include "tcg_func_table_generated.c.inc"
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index e1dcd24b0e..8ff74a4aa8 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -24,8 +24,30 @@
extern const SemanticInsn opcode_genptr[];
+TCGv gen_read_reg(TCGv result, int num);
TCGv gen_read_preg(TCGv pred, uint8_t num);
void gen_log_reg_write(int rnum, TCGv val);
void gen_log_pred_write(int pnum, TCGv val);
+void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slot);
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ unsigned slot);
+void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ unsigned slot);
+void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+ unsigned slot);
+void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *ctx,
+ unsigned slot);
+void gen_write_new_pc(TCGv addr);
+void gen_set_usr_field(int field, TCGv val);
+void gen_set_usr_fieldi(int field, int x);
+void gen_sat_i32(TCGv dest, TCGv source, int width);
+void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width);
+void gen_satu_i32(TCGv dest, TCGv source, int width);
+void gen_satu_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width);
+void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_sat_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_satu_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_fbrev(TCGv result, TCGv src);
#endif
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index d9473c8823..94357c3e42 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -149,7 +149,16 @@
#define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
#endif
+#ifdef QEMU_GENERATE
+static inline void gen_cancel(unsigned slot)
+{
+ tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
+}
+
+#define CANCEL gen_cancel(slot);
+#else
#define CANCEL cancel_slot(env, slot)
+#endif
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
--
2.31.1
next prev parent reply other threads:[~2021-04-15 16:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-15 16:34 [PATCH v4 00/12] target/hexagon: introduce idef-parser Alessandro Di Federico via
2021-04-15 16:34 ` [PATCH v4 01/12] tcg: expose TCGCond manipulation routines Alessandro Di Federico via
2021-04-18 20:57 ` Richard Henderson
2021-04-15 16:34 ` [PATCH v4 02/12] target/hexagon: update MAINTAINERS for idef-parser Alessandro Di Federico via
2021-04-18 20:58 ` Richard Henderson
2021-04-15 16:34 ` [PATCH v4 03/12] target/hexagon: import README " Alessandro Di Federico via
2021-04-15 16:34 ` [PATCH v4 04/12] target/hexagon: make slot number an unsigned Alessandro Di Federico via
2021-04-18 21:10 ` Richard Henderson
2021-04-15 16:34 ` [PATCH v4 05/12] target/hexagon: make helper functions non-static Alessandro Di Federico via
2021-04-18 21:11 ` Richard Henderson
2021-04-15 16:34 ` Alessandro Di Federico via [this message]
2021-04-18 21:31 ` [PATCH v4 06/12] target/hexagon: introduce new helper functions Richard Henderson
2021-04-19 15:00 ` Taylor Simpson
2021-04-20 6:39 ` Alessandro Di Federico via
2021-04-15 16:34 ` [PATCH v4 07/12] target/hexagon: expose next PC in DisasContext Alessandro Di Federico via
2021-04-18 21:34 ` Richard Henderson
2021-04-15 16:34 ` [PATCH v4 08/12] target/hexagon: prepare input for the idef-parser Alessandro Di Federico via
2021-04-18 21:43 ` Richard Henderson
2021-04-15 16:34 ` [PATCH v4 09/12] target/hexagon: import lexer for idef-parser Alessandro Di Federico via
2021-04-27 2:01 ` Taylor Simpson
2021-04-28 10:25 ` Paolo Montesel
2021-04-28 15:55 ` Taylor Simpson
2021-04-29 10:53 ` Paolo Montesel
2021-04-15 16:34 ` [PATCH v4 10/12] target/hexagon: import parser " Alessandro Di Federico via
2021-04-15 16:34 ` [PATCH v4 11/12] target/hexagon: call idef-parser functions Alessandro Di Federico via
2021-04-29 15:59 ` Taylor Simpson
2021-04-15 16:34 ` [PATCH v4 12/12] target/hexagon: import additional tests Alessandro Di Federico via
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210415163455.3839169-7-ale.qemu@rev.ng \
--to=qemu-devel@nongnu.org \
--cc=ale.qemu@rev.ng \
--cc=ale@rev.ng \
--cc=babush@rev.ng \
--cc=bcain@quicinc.com \
--cc=nizzo@rev.ng \
--cc=philmd@redhat.com \
--cc=richard.henderson@linaro.org \
--cc=tsimpson@quicinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).