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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 07/29] target/mips: Turn printfpr() macro into a proper function
Date: Mon, 19 Apr 2021 00:50:36 +0200	[thread overview]
Message-ID: <20210418225058.1257014-8-f4bug@amsat.org> (raw)
In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org>

Turn printfpr() macro into a proper function: fpu_dump_fpr().

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.c | 48 ++++++++++++++++++++++-------------------------
 1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 232f701b836..90ae232c8b8 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,44 +145,40 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 
 #endif /* !CONFIG_USER_ONLY */
 
+static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
+{
+    if (is_fpu64) {
+        qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
+                     fpr->w[FP_ENDIAN_IDX], fpr->d,
+                     (double)fpr->fd,
+                     (double)fpr->fs[FP_ENDIAN_IDX],
+                     (double)fpr->fs[!FP_ENDIAN_IDX]);
+    } else {
+        fpr_t tmp;
+
+        tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
+        tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
+        qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
+                     tmp.w[FP_ENDIAN_IDX], tmp.d,
+                     (double)tmp.fd,
+                     (double)tmp.fs[FP_ENDIAN_IDX],
+                     (double)tmp.fs[!FP_ENDIAN_IDX]);
+    }
+}
+
 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
 {
     int i;
     int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
 
-#define printfpr(fp)                                                    \
-    do {                                                                \
-        if (is_fpu64)                                                   \
-            qemu_fprintf(f, "w:%08x d:%016" PRIx64                      \
-                         " fd:%13g fs:%13g psu: %13g\n",                \
-                         (fp)->w[FP_ENDIAN_IDX], (fp)->d,               \
-                         (double)(fp)->fd,                              \
-                         (double)(fp)->fs[FP_ENDIAN_IDX],               \
-                         (double)(fp)->fs[!FP_ENDIAN_IDX]);             \
-        else {                                                          \
-            fpr_t tmp;                                                  \
-            tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];              \
-            tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];       \
-            qemu_fprintf(f, "w:%08x d:%016" PRIx64                      \
-                         " fd:%13g fs:%13g psu:%13g\n",                 \
-                         tmp.w[FP_ENDIAN_IDX], tmp.d,                   \
-                         (double)tmp.fd,                                \
-                         (double)tmp.fs[FP_ENDIAN_IDX],                 \
-                         (double)tmp.fs[!FP_ENDIAN_IDX]);               \
-        }                                                               \
-    } while (0)
-
-
     qemu_fprintf(f,
                  "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
                  env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
                  get_float_exception_flags(&env->active_fpu.fp_status));
     for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
         qemu_fprintf(f, "%3s: ", fregnames[i]);
-        printfpr(&env->active_fpu.fpr[i]);
+        fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64);
     }
-
-#undef printfpr
 }
 
 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-- 
2.26.3



  parent reply	other threads:[~2021-04-18 22:53 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-18 22:50 [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 01/29] target/mips: Simplify meson TCG rules Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 03/29] target/mips: Move msa_reset() " Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 04/29] target/mips: Make CPU/FPU regnames[] arrays global Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 05/29] target/mips: Optimize CPU/FPU regnames[] arrays Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` Philippe Mathieu-Daudé [this message]
2021-04-18 22:50 ` [PATCH v2 08/29] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h" Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 09/29] target/mips: Extract load/store helpers to ldst_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 10/29] meson: Introduce meson_user_arch source set for arch-specific user-mode Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 11/29] target/mips: Introduce tcg-internal.h for TCG specific declarations Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 12/29] target/mips: Add simple user-mode mips_cpu_do_interrupt() Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 13/29] target/mips: Add simple user-mode mips_cpu_tlb_fill() Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 14/29] target/mips: Move cpu_signal_handler definition around Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 15/29] target/mips: Move sysemu specific files under sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 16/29] target/mips: Move physical addressing code to sysemu/physaddr.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 17/29] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 18/29] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 19/29] target/mips: Restrict mmu_init() to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 20/29] target/mips: Move tlb_helper.c to tcg/sysemu/ Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 21/29] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 22/29] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 23/29] target/mips: Move helper_cache() " Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 24/29] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 25/29] target/mips: Move exception management code to exception.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 26/29] target/mips: Move CP0 helpers to sysemu/cp0.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 27/29] target/mips: Move TCG source files under tcg/ sub directory Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 28/29] hw/mips: Restrict non-virtualized machines to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 29/29] gitlab-ci: Add KVM mips64el cross-build jobs Philippe Mathieu-Daudé
2021-04-19 10:25   ` Thomas Huth
2021-04-18 23:03 ` [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds no-reply

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