From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base
Date: Fri, 30 Apr 2021 11:34:11 +0100 [thread overview]
Message-ID: <20210430103437.4140-18-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Now that we have all of the proper macros defined, expanding
the CPUARMTBFlags structure and populating the two TB fields
is relatively simple.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 49 ++++++++++++++++++++++++------------------
target/arm/translate.h | 2 +-
target/arm/helper.c | 10 +++++----
3 files changed, 35 insertions(+), 26 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 79af9a7c628..a8da7c55a6b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -228,6 +228,7 @@ typedef struct ARMPACKey {
/* See the commentary above the TBFLAG field definitions. */
typedef struct CPUARMTBFlags {
uint32_t flags;
+ target_ulong flags2;
} CPUARMTBFlags;
typedef struct CPUARMState {
@@ -3381,20 +3382,26 @@ typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
/*
- * Bit usage in the TB flags field: bit 31 indicates whether we are
- * in 32 or 64 bit mode. The meaning of the other bits depends on that.
- * We put flags which are shared between 32 and 64 bit mode at the top
- * of the word, and flags which apply to only one mode at the bottom.
+ * We have more than 32-bits worth of state per TB, so we split the data
+ * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
+ * We collect these two parts in CPUARMTBFlags where they are named
+ * flags and flags2 respectively.
*
- * 31 20 18 14 9 0
- * +--------------+-----+-----+----------+--------------+
- * | | | TBFLAG_A32 | |
- * | | +-----+----------+ TBFLAG_AM32 |
- * | TBFLAG_ANY | |TBFLAG_M32| |
- * | +-----------+----------+--------------|
- * | | TBFLAG_A64 |
- * +--------------+-------------------------------------+
- * 31 20 0
+ * The flags that are shared between all execution modes, TBFLAG_ANY,
+ * are stored in flags. The flags that are specific to a given mode
+ * are stores in flags2. Since cs_base is sized on the configured
+ * address size, flags2 always has 64-bits for A64, and a minimum of
+ * 32-bits for A32 and M32.
+ *
+ * The bits for 32-bit A-profile and M-profile partially overlap:
+ *
+ * 18 9 0
+ * +----------------+--------------+
+ * | TBFLAG_A32 | |
+ * +-----+----------+ TBFLAG_AM32 |
+ * | |TBFLAG_M32| |
+ * +-----+----------+--------------+
+ * 14 9 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3472,19 +3479,19 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
(DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
#define DP_TBFLAG_A64(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
#define DP_TBFLAG_A32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
#define DP_TBFLAG_M32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
-#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH)
-#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH)
-#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH)
-#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH)
+#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
+#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
+#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
+#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
/**
* cpu_mmu_index:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index f30287e5546..50c2aba0667 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -402,7 +402,7 @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
*/
static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
{
- return (CPUARMTBFlags){ tb->flags };
+ return (CPUARMTBFlags){ tb->flags, tb->cs_base };
}
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f564e59084a..4aa7650d3a7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13256,9 +13256,11 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
CPUARMTBFlags c = env->hflags;
CPUARMTBFlags r = rebuild_hflags_internal(env);
- if (unlikely(c.flags != r.flags)) {
- fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
- c.flags, r.flags);
+ if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
+ fprintf(stderr, "TCG hflags mismatch "
+ "(current:(0x%08x,0x" TARGET_FMT_lx ")"
+ " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
+ c.flags, c.flags2, r.flags, r.flags2);
abort();
}
#endif
@@ -13269,7 +13271,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
{
CPUARMTBFlags flags;
- *cs_base = 0;
assert_hflags_rebuild_correctly(env);
flags = env->hflags;
@@ -13338,6 +13339,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
}
*pflags = flags.flags;
+ *cs_base = flags.flags2;
}
#ifdef TARGET_AARCH64
--
2.20.1
next prev parent reply other threads:[~2021-04-30 10:45 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 10:33 [PULL 00/43] target-arm queue Peter Maydell
2021-04-30 10:33 ` [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule Peter Maydell
2021-04-30 10:33 ` [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111 Peter Maydell
2021-04-30 10:33 ` [PULL 03/43] target/arm: Fix mte_checkN Peter Maydell
2021-04-30 10:33 ` [PULL 04/43] target/arm: Split out mte_probe_int Peter Maydell
2021-04-30 10:33 ` [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1 Peter Maydell
2021-04-30 10:34 ` [PULL 06/43] test/tcg/aarch64: Add mte-5 Peter Maydell
2021-04-30 10:34 ` [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1 Peter Maydell
2021-04-30 10:34 ` [PULL 08/43] target/arm: Merge mte_check1, mte_checkN Peter Maydell
2021-04-30 10:34 ` [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe Peter Maydell
2021-04-30 10:34 ` [PULL 10/43] target/arm: Simplify sve mte checking Peter Maydell
2021-04-30 10:34 ` [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN Peter Maydell
2021-04-30 10:34 ` [PULL 12/43] target/arm: Fix decode of align in VLDST_single Peter Maydell
2021-04-30 10:34 ` [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B Peter Maydell
2021-04-30 10:34 ` [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS Peter Maydell
2021-04-30 10:34 ` [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags Peter Maydell
2021-04-30 10:34 ` [PULL 16/43] target/arm: Introduce CPUARMTBFlags Peter Maydell
2021-04-30 10:34 ` Peter Maydell [this message]
2021-04-30 10:34 ` [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top Peter Maydell
2021-04-30 10:34 ` [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom Peter Maydell
2021-04-30 10:34 ` [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY Peter Maydell
2021-04-30 10:34 ` [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Peter Maydell
2021-04-30 10:34 ` [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Peter Maydell
2021-04-30 10:34 ` [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Peter Maydell
2021-04-30 10:34 ` [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Peter Maydell
2021-04-30 10:34 ` [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD Peter Maydell
2021-04-30 10:34 ` [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Peter Maydell
2021-04-30 10:34 ` [PULL 27/43] target/arm: Enforce alignment for LDM/STM Peter Maydell
2021-04-30 10:34 ` [PULL 28/43] target/arm: Enforce alignment for RFE Peter Maydell
2021-04-30 10:34 ` [PULL 29/43] target/arm: Enforce alignment for SRS Peter Maydell
2021-04-30 10:34 ` [PULL 30/43] target/arm: Enforce alignment for VLDM/VSTM Peter Maydell
2021-04-30 10:34 ` [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR Peter Maydell
2021-04-30 10:34 ` [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes) Peter Maydell
2021-04-30 10:34 ` [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple) Peter Maydell
2021-04-30 10:34 ` [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single) Peter Maydell
2021-04-30 10:34 ` [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store Peter Maydell
2021-04-30 10:34 ` [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store Peter Maydell
2021-04-30 10:34 ` [PULL 37/43] target/arm: Enforce alignment for aa64 load-acq/store-rel Peter Maydell
2021-04-30 10:34 ` [PULL 38/43] target/arm: Use MemOp for size + endian in aa64 vector ld/st Peter Maydell
2021-04-30 10:34 ` [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Peter Maydell
2021-04-30 10:34 ` [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Peter Maydell
2021-04-30 10:34 ` [PULL 41/43] target/arm: Enforce alignment for sve LD1R Peter Maydell
2021-04-30 10:34 ` [PULL 42/43] hw: add compat machines for 6.1 Peter Maydell
2021-04-30 10:34 ` [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows Peter Maydell
2021-04-30 11:18 ` [PULL 00/43] target-arm queue no-reply
2021-04-30 12:45 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210430103437.4140-18-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).