From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1
Date: Fri, 30 Apr 2021 11:34:01 +0100 [thread overview]
Message-ID: <20210430103437.4140-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
After recent changes, mte_checkN does not use ESIZE,
and mte_check1 never used TSIZE. We can combine the
two into a single field: SIZEM1.
Choose to pass size - 1 because size == 0 is never used,
our immediate need in mte_probe_int is for the address
of the last byte (ptr + size - 1), and since almost all
operations are powers of 2, this makes the immediate
constant one bit smaller.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 4 ++--
target/arm/mte_helper.c | 18 ++++++++----------
target/arm/translate-a64.c | 5 ++---
target/arm/translate-sve.c | 5 ++---
4 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f11bd326962..2c77f2d50f0 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -26,6 +26,7 @@
#define TARGET_ARM_INTERNALS_H
#include "hw/registerfields.h"
+#include "tcg/tcg-gvec-desc.h"
#include "syndrome.h"
/* register banks for CPU modes */
@@ -1142,8 +1143,7 @@ FIELD(MTEDESC, MIDX, 0, 4)
FIELD(MTEDESC, TBI, 4, 2)
FIELD(MTEDESC, TCMA, 6, 2)
FIELD(MTEDESC, WRITE, 8, 1)
-FIELD(MTEDESC, ESIZE, 9, 5)
-FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */
+FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */
bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr);
uint64_t mte_check1(CPUARMState *env, uint32_t desc,
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 0ee0397eb26..804057d3f6e 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -692,13 +692,13 @@ static int checkN(uint8_t *mem, int odd, int cmp, int count)
* Return positive on success with tbi enabled.
*/
static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr,
- uintptr_t ra, uint32_t total, uint64_t *fault)
+ uintptr_t ra, uint64_t *fault)
{
int mmu_idx, ptr_tag, bit55;
uint64_t ptr_last, prev_page, next_page;
uint64_t tag_first, tag_last;
uint64_t tag_byte_first, tag_byte_last;
- uint32_t tag_count, tag_size, n, c;
+ uint32_t sizem1, tag_count, tag_size, n, c;
uint8_t *mem1, *mem2;
MMUAccessType type;
@@ -718,9 +718,10 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr,
mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD;
+ sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1);
/* Find the addr of the end of the access */
- ptr_last = ptr + total - 1;
+ ptr_last = ptr + sizem1;
/* Round the bounds to the tag granule, and compute the number of tags. */
tag_first = QEMU_ALIGN_DOWN(ptr, TAG_GRANULE);
@@ -738,7 +739,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr,
if (likely(tag_last - prev_page <= TARGET_PAGE_SIZE)) {
/* Memory access stays on one page. */
tag_size = ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)) + 1;
- mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, total,
+ mem1 = allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1,
MMU_DATA_LOAD, tag_size, ra);
if (!mem1) {
return 1;
@@ -792,8 +793,7 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
uint64_t ptr, uintptr_t ra)
{
uint64_t fault;
- uint32_t total = FIELD_EX32(desc, MTEDESC, TSIZE);
- int ret = mte_probe_int(env, desc, ptr, ra, total, &fault);
+ int ret = mte_probe_int(env, desc, ptr, ra, &fault);
if (unlikely(ret == 0)) {
mte_check_fail(env, desc, fault, ra);
@@ -812,8 +812,7 @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc,
uint64_t ptr, uintptr_t ra)
{
uint64_t fault;
- uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE);
- int ret = mte_probe_int(env, desc, ptr, ra, total, &fault);
+ int ret = mte_probe_int(env, desc, ptr, ra, &fault);
if (unlikely(ret == 0)) {
mte_check_fail(env, desc, fault, ra);
@@ -837,8 +836,7 @@ uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr)
bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr)
{
uint64_t fault;
- uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE);
- int ret = mte_probe_int(env, desc, ptr, 0, total, &fault);
+ int ret = mte_probe_int(env, desc, ptr, 0, &fault);
return ret != 0;
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 0b42e53500e..3af00ae90ef 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -272,7 +272,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
- desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size);
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
tcg_desc = tcg_const_i32(desc);
ret = new_tmp_a64(s);
@@ -306,8 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
- desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_esize);
- desc = FIELD_DP32(desc, MTEDESC, TSIZE, total_size);
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1);
tcg_desc = tcg_const_i32(desc);
ret = new_tmp_a64(s);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 0eefb612144..5179c1f8363 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4509,8 +4509,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
- desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);
- desc = FIELD_DP32(desc, MTEDESC, TSIZE, mte_n << msz);
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
desc <<= SVE_MTEDESC_SHIFT;
} else {
addr = clean_data_tbi(s, addr);
@@ -5189,7 +5188,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
- desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
desc <<= SVE_MTEDESC_SHIFT;
}
desc = simd_desc(vsz, vsz, desc | scale);
--
2.20.1
next prev parent reply other threads:[~2021-04-30 10:43 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 10:33 [PULL 00/43] target-arm queue Peter Maydell
2021-04-30 10:33 ` [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule Peter Maydell
2021-04-30 10:33 ` [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111 Peter Maydell
2021-04-30 10:33 ` [PULL 03/43] target/arm: Fix mte_checkN Peter Maydell
2021-04-30 10:33 ` [PULL 04/43] target/arm: Split out mte_probe_int Peter Maydell
2021-04-30 10:33 ` [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1 Peter Maydell
2021-04-30 10:34 ` [PULL 06/43] test/tcg/aarch64: Add mte-5 Peter Maydell
2021-04-30 10:34 ` Peter Maydell [this message]
2021-04-30 10:34 ` [PULL 08/43] target/arm: Merge mte_check1, mte_checkN Peter Maydell
2021-04-30 10:34 ` [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe Peter Maydell
2021-04-30 10:34 ` [PULL 10/43] target/arm: Simplify sve mte checking Peter Maydell
2021-04-30 10:34 ` [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN Peter Maydell
2021-04-30 10:34 ` [PULL 12/43] target/arm: Fix decode of align in VLDST_single Peter Maydell
2021-04-30 10:34 ` [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B Peter Maydell
2021-04-30 10:34 ` [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS Peter Maydell
2021-04-30 10:34 ` [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags Peter Maydell
2021-04-30 10:34 ` [PULL 16/43] target/arm: Introduce CPUARMTBFlags Peter Maydell
2021-04-30 10:34 ` [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base Peter Maydell
2021-04-30 10:34 ` [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top Peter Maydell
2021-04-30 10:34 ` [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom Peter Maydell
2021-04-30 10:34 ` [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY Peter Maydell
2021-04-30 10:34 ` [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Peter Maydell
2021-04-30 10:34 ` [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Peter Maydell
2021-04-30 10:34 ` [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Peter Maydell
2021-04-30 10:34 ` [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Peter Maydell
2021-04-30 10:34 ` [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD Peter Maydell
2021-04-30 10:34 ` [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Peter Maydell
2021-04-30 10:34 ` [PULL 27/43] target/arm: Enforce alignment for LDM/STM Peter Maydell
2021-04-30 10:34 ` [PULL 28/43] target/arm: Enforce alignment for RFE Peter Maydell
2021-04-30 10:34 ` [PULL 29/43] target/arm: Enforce alignment for SRS Peter Maydell
2021-04-30 10:34 ` [PULL 30/43] target/arm: Enforce alignment for VLDM/VSTM Peter Maydell
2021-04-30 10:34 ` [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR Peter Maydell
2021-04-30 10:34 ` [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes) Peter Maydell
2021-04-30 10:34 ` [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple) Peter Maydell
2021-04-30 10:34 ` [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single) Peter Maydell
2021-04-30 10:34 ` [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store Peter Maydell
2021-04-30 10:34 ` [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store Peter Maydell
2021-04-30 10:34 ` [PULL 37/43] target/arm: Enforce alignment for aa64 load-acq/store-rel Peter Maydell
2021-04-30 10:34 ` [PULL 38/43] target/arm: Use MemOp for size + endian in aa64 vector ld/st Peter Maydell
2021-04-30 10:34 ` [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Peter Maydell
2021-04-30 10:34 ` [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Peter Maydell
2021-04-30 10:34 ` [PULL 41/43] target/arm: Enforce alignment for sve LD1R Peter Maydell
2021-04-30 10:34 ` [PULL 42/43] hw: add compat machines for 6.1 Peter Maydell
2021-04-30 10:34 ` [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows Peter Maydell
2021-04-30 11:18 ` [PULL 00/43] target-arm queue no-reply
2021-04-30 12:45 ` Peter Maydell
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