* [PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model @ 2021-05-01 7:24 Nicholas Piggin 2021-05-01 7:24 ` [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Nicholas Piggin 2021-05-01 7:24 ` [PATCH 2/2] target/ppc: Add POWER10 exception model Nicholas Piggin 0 siblings, 2 replies; 5+ messages in thread From: Nicholas Piggin @ 2021-05-01 7:24 UTC (permalink / raw) To: qemu-ppc Cc: Fabiano Rosas, Cédric Le Goater, qemu-devel, Nicholas Piggin, David Gibson Here are the last 2 patches of this series rebased on the ppc-for-6.1 tree. I've tidied up the comments and control flow around the reserved values of AIL, so different behaviours/reasons are treated individually which hopefully addresses David's comments. On real hardware, setting LPCR[AIL] to a reserved value (e.g., 1 on POWER9) causes the register to retain that value but it's treated like 0, which matches what the patch does. Thanks, Nick Nicholas Piggin (2): target/ppc: rework AIL logic in interrupt delivery target/ppc: Add POWER10 exception model hw/ppc/spapr_hcall.c | 8 +- target/ppc/cpu-qom.h | 2 + target/ppc/cpu.h | 13 +- target/ppc/excp_helper.c | 217 +++++++++++++++++++++++--------- target/ppc/translate.c | 3 +- target/ppc/translate_init.c.inc | 4 +- 6 files changed, 171 insertions(+), 76 deletions(-) -- 2.23.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery 2021-05-01 7:24 [PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model Nicholas Piggin @ 2021-05-01 7:24 ` Nicholas Piggin 2021-05-03 3:41 ` David Gibson 2021-05-01 7:24 ` [PATCH 2/2] target/ppc: Add POWER10 exception model Nicholas Piggin 1 sibling, 1 reply; 5+ messages in thread From: Nicholas Piggin @ 2021-05-01 7:24 UTC (permalink / raw) To: qemu-ppc Cc: Fabiano Rosas, qemu-devel, Nicholas Piggin, Cédric Le Goater, Cédric Le Goater, David Gibson The AIL logic is becoming unmanageable spread all over powerpc_excp(), and it is slated to get even worse with POWER10 support. Move it all to a new helper function. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- hw/ppc/spapr_hcall.c | 3 +- target/ppc/cpu.h | 8 -- target/ppc/excp_helper.c | 165 ++++++++++++++++++++------------ target/ppc/translate_init.c.inc | 2 +- 4 files changed, 108 insertions(+), 70 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..2fbe04a689 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1395,7 +1395,8 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, return H_P4; } - if (mflags == AIL_RESERVED) { + if (mflags == 1) { + /* AIL=1 is reserved */ return H_UNSUPPORTED_FLAG; } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8c18bb0762..be24a501fc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2405,14 +2405,6 @@ enum { HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23), }; -/* Alternate Interrupt Location (AIL) */ -enum { - AIL_NONE = 0, - AIL_RESERVED = 1, - AIL_0001_8000 = 2, - AIL_C000_0000_0000_4000 = 3, -}; - /*****************************************************************************/ #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 344af66f66..73360bb872 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -136,25 +136,111 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, return POWERPC_EXCP_RESET; } -static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail) +/* + * AIL - Alternate Interrupt Location, a mode that allows interrupts to be + * taken with the MMU on, and which uses an alternate location (e.g., so the + * kernel/hv can map the vectors there with an effective address). + * + * An interrupt is considered to be taken "with AIL" or "AIL applies" if they + * are delivered in this way. AIL requires the LPCR to be set to enable this + * mode, and then a number of conditions have to be true for AIL to apply. + * + * First of all, SRESET, MCE, and HMI are always delivered without AIL, because + * they specifically want to be in real mode (e.g., the MCE might be signaling + * a SLB multi-hit which requires SLB flush before the MMU can be enabled). + * + * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV], + * whether or not the interrupt changes MSR[HV] from 0 to 1, and the current + * radix mode (LPCR[HR]). + * + * POWER8, POWER9 with LPCR[HR]=0 + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+-------------+---------+-------------+-----+ + * | a | 00/01/10 | x | x | 0 | + * | a | 11 | 0 | 1 | 0 | + * | a | 11 | 1 | 1 | a | + * | a | 11 | 0 | 0 | a | + * +-------------------------------------------------------+ + * + * POWER9 with LPCR[HR]=1 + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+-------------+---------+-------------+-----+ + * | a | 00/01/10 | x | x | 0 | + * | a | 11 | x | x | a | + * +-------------------------------------------------------+ + * + * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to + * the hypervisor in AIL mode if the guest is radix. + */ +static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, + target_ulong msr, + target_ulong *new_msr, + target_ulong *vector) { - uint64_t offset = 0; +#if defined(TARGET_PPC64) + CPUPPCState *env = &cpu->env; + bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); + bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB); + int ail = 0; + + if (excp == POWERPC_EXCP_MCHECK || + excp == POWERPC_EXCP_RESET || + excp == POWERPC_EXCP_HV_MAINT) { + /* SRESET, MCE, HMI never apply AIL */ + return; + } - switch (ail) { - case AIL_NONE: - break; - case AIL_0001_8000: - offset = 0x18000; - break; - case AIL_C000_0000_0000_4000: - offset = 0xc000000000004000ull; - break; - default: - cpu_abort(cs, "Invalid AIL combination %d\n", ail); - break; + if (excp_model == POWERPC_EXCP_POWER8 || + excp_model == POWERPC_EXCP_POWER9) { + if (!mmu_all_on) { + /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */ + return; + } + if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { + /* + * AIL does not work if there is a MSR[HV] 0->1 transition and the + * partition is in HPT mode. For radix guests, such interrupts are + * allowed to be delivered to the hypervisor in ail mode. + */ + return; + } + + ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + if (ail == 0) { + return; + } + if (ail == 1) { + /* AIL=1 is reserved, treat it like AIL=0 */ + return; + } + } else { + /* Other processors do not support AIL */ + return; } - return offset; + /* + * AIL applies, so the new MSR gets IR and DR set, and an offset applied + * to the new IP. + */ + *new_msr |= (1 << MSR_IR) | (1 << MSR_DR); + + if (excp != POWERPC_EXCP_SYSCALL_VECTORED) { + if (ail == 2) { + *vector |= 0x0000000000018000ull; + } else if (ail == 3) { + *vector |= 0xc000000000004000ull; + } + } else { + /* + * scv AIL is a little different. AIL=2 does not change the address, + * only the MSR. AIL=3 replaces the 0x17000 base with 0xc...3000. + */ + if (ail == 3) { + *vector &= ~0x0000000000017000ull; /* Un-apply the base offset */ + *vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */ + } + } +#endif } static inline void powerpc_set_excp_state(PowerPCCPU *cpu, @@ -197,7 +283,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1, asrr0, asrr1, lev = -1, ail; + int srr0, srr1, asrr0, asrr1, lev = -1; bool lpes0; qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx @@ -238,25 +324,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) * * On anything else, we behave as if LPES0 is 1 * (externals don't alter MSR:HV) - * - * AIL is initialized here but can be cleared by - * selected exceptions */ #if defined(TARGET_PPC64) if (excp_model == POWERPC_EXCP_POWER7 || excp_model == POWERPC_EXCP_POWER8 || excp_model == POWERPC_EXCP_POWER9) { lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); - if (excp_model != POWERPC_EXCP_POWER7) { - ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; - } else { - ail = 0; - } } else #endif /* defined(TARGET_PPC64) */ { lpes0 = true; - ail = 0; } /* @@ -315,7 +392,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) */ new_msr |= (target_ulong)MSR_HVB; } - ail = 0; /* machine check exceptions don't have ME set */ new_msr &= ~((target_ulong)1 << MSR_ME); @@ -519,7 +595,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) "exception %d with no HV support\n", excp); } } - ail = 0; break; case POWERPC_EXCP_DSEG: /* Data segment exception */ case POWERPC_EXCP_ISEG: /* Instruction segment exception */ @@ -790,24 +865,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } #endif - /* - * AIL only works if MSR[IR] and MSR[DR] are both enabled. - */ - if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) { - ail = 0; - } - - /* - * AIL does not work if there is a MSR[HV] 0->1 transition and the - * partition is in HPT mode. For radix guests, such interrupts are - * allowed to be delivered to the hypervisor in ail mode. - */ - if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) { - if (!(env->spr[SPR_LPCR] & LPCR_HR)) { - ail = 0; - } - } - vector = env->excp_vectors[excp]; if (vector == (target_ulong)-1ULL) { cpu_abort(cs, "Raised an exception without defined vector %d\n", @@ -848,23 +905,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Save MSR */ env->spr[srr1] = msr; - /* Handle AIL */ - if (ail) { - new_msr |= (1 << MSR_IR) | (1 << MSR_DR); - vector |= ppc_excp_vector_offset(cs, ail); - } - #if defined(TARGET_PPC64) } else { - /* scv AIL is a little different */ - if (ail) { - new_msr |= (1 << MSR_IR) | (1 << MSR_DR); - } - if (ail == AIL_C000_0000_0000_4000) { - vector |= 0xc000000000003000ull; - } else { - vector |= 0x0000000000017000ull; - } vector += lev * 0x20; env->lr = env->nip; @@ -872,6 +914,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) #endif } + /* This can update new_msr and vector if AIL applies */ + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); + powerpc_set_excp_state(cpu, vector, new_msr); } diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 9ab2c32cc4..01fa76e4a0 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -3457,7 +3457,7 @@ static void init_excp_POWER9(CPUPPCState *env) #if !defined(CONFIG_USER_ONLY) env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; - env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; #endif } -- 2.23.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery 2021-05-01 7:24 ` [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Nicholas Piggin @ 2021-05-03 3:41 ` David Gibson 0 siblings, 0 replies; 5+ messages in thread From: David Gibson @ 2021-05-03 3:41 UTC (permalink / raw) To: Nicholas Piggin Cc: Cédric Le Goater, Cédric Le Goater, qemu-ppc, qemu-devel, Fabiano Rosas [-- Attachment #1: Type: text/plain, Size: 11917 bytes --] On Sat, May 01, 2021 at 05:24:34PM +1000, Nicholas Piggin wrote: > The AIL logic is becoming unmanageable spread all over powerpc_excp(), > and it is slated to get even worse with POWER10 support. > > Move it all to a new helper function. > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > Tested-by: Cédric Le Goater <clg@kaod.org> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Applied to ppc-for-6.1, thanks. > --- > hw/ppc/spapr_hcall.c | 3 +- > target/ppc/cpu.h | 8 -- > target/ppc/excp_helper.c | 165 ++++++++++++++++++++------------ > target/ppc/translate_init.c.inc | 2 +- > 4 files changed, 108 insertions(+), 70 deletions(-) > > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > index 7b5cd3553c..2fbe04a689 100644 > --- a/hw/ppc/spapr_hcall.c > +++ b/hw/ppc/spapr_hcall.c > @@ -1395,7 +1395,8 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, > return H_P4; > } > > - if (mflags == AIL_RESERVED) { > + if (mflags == 1) { > + /* AIL=1 is reserved */ > return H_UNSUPPORTED_FLAG; > } > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 8c18bb0762..be24a501fc 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2405,14 +2405,6 @@ enum { > HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23), > }; > > -/* Alternate Interrupt Location (AIL) */ > -enum { > - AIL_NONE = 0, > - AIL_RESERVED = 1, > - AIL_0001_8000 = 2, > - AIL_C000_0000_0000_4000 = 3, > -}; > - > /*****************************************************************************/ > > #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 344af66f66..73360bb872 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -136,25 +136,111 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, > return POWERPC_EXCP_RESET; > } > > -static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail) > +/* > + * AIL - Alternate Interrupt Location, a mode that allows interrupts to be > + * taken with the MMU on, and which uses an alternate location (e.g., so the > + * kernel/hv can map the vectors there with an effective address). > + * > + * An interrupt is considered to be taken "with AIL" or "AIL applies" if they > + * are delivered in this way. AIL requires the LPCR to be set to enable this > + * mode, and then a number of conditions have to be true for AIL to apply. > + * > + * First of all, SRESET, MCE, and HMI are always delivered without AIL, because > + * they specifically want to be in real mode (e.g., the MCE might be signaling > + * a SLB multi-hit which requires SLB flush before the MMU can be enabled). > + * > + * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV], > + * whether or not the interrupt changes MSR[HV] from 0 to 1, and the current > + * radix mode (LPCR[HR]). > + * > + * POWER8, POWER9 with LPCR[HR]=0 > + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | > + * +-----------+-------------+---------+-------------+-----+ > + * | a | 00/01/10 | x | x | 0 | > + * | a | 11 | 0 | 1 | 0 | > + * | a | 11 | 1 | 1 | a | > + * | a | 11 | 0 | 0 | a | > + * +-------------------------------------------------------+ > + * > + * POWER9 with LPCR[HR]=1 > + * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | > + * +-----------+-------------+---------+-------------+-----+ > + * | a | 00/01/10 | x | x | 0 | > + * | a | 11 | x | x | a | > + * +-------------------------------------------------------+ > + * > + * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to > + * the hypervisor in AIL mode if the guest is radix. > + */ > +static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, > + target_ulong msr, > + target_ulong *new_msr, > + target_ulong *vector) > { > - uint64_t offset = 0; > +#if defined(TARGET_PPC64) > + CPUPPCState *env = &cpu->env; > + bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); > + bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB); > + int ail = 0; > + > + if (excp == POWERPC_EXCP_MCHECK || > + excp == POWERPC_EXCP_RESET || > + excp == POWERPC_EXCP_HV_MAINT) { > + /* SRESET, MCE, HMI never apply AIL */ > + return; > + } > > - switch (ail) { > - case AIL_NONE: > - break; > - case AIL_0001_8000: > - offset = 0x18000; > - break; > - case AIL_C000_0000_0000_4000: > - offset = 0xc000000000004000ull; > - break; > - default: > - cpu_abort(cs, "Invalid AIL combination %d\n", ail); > - break; > + if (excp_model == POWERPC_EXCP_POWER8 || > + excp_model == POWERPC_EXCP_POWER9) { > + if (!mmu_all_on) { > + /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */ > + return; > + } > + if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { > + /* > + * AIL does not work if there is a MSR[HV] 0->1 transition and the > + * partition is in HPT mode. For radix guests, such interrupts are > + * allowed to be delivered to the hypervisor in ail mode. > + */ > + return; > + } > + > + ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; > + if (ail == 0) { > + return; > + } > + if (ail == 1) { > + /* AIL=1 is reserved, treat it like AIL=0 */ > + return; > + } > + } else { > + /* Other processors do not support AIL */ > + return; > } > > - return offset; > + /* > + * AIL applies, so the new MSR gets IR and DR set, and an offset applied > + * to the new IP. > + */ > + *new_msr |= (1 << MSR_IR) | (1 << MSR_DR); > + > + if (excp != POWERPC_EXCP_SYSCALL_VECTORED) { > + if (ail == 2) { > + *vector |= 0x0000000000018000ull; > + } else if (ail == 3) { > + *vector |= 0xc000000000004000ull; > + } > + } else { > + /* > + * scv AIL is a little different. AIL=2 does not change the address, > + * only the MSR. AIL=3 replaces the 0x17000 base with 0xc...3000. > + */ > + if (ail == 3) { > + *vector &= ~0x0000000000017000ull; /* Un-apply the base offset */ > + *vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */ > + } > + } > +#endif > } > > static inline void powerpc_set_excp_state(PowerPCCPU *cpu, > @@ -197,7 +283,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > CPUState *cs = CPU(cpu); > CPUPPCState *env = &cpu->env; > target_ulong msr, new_msr, vector; > - int srr0, srr1, asrr0, asrr1, lev = -1, ail; > + int srr0, srr1, asrr0, asrr1, lev = -1; > bool lpes0; > > qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx > @@ -238,25 +324,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > * > * On anything else, we behave as if LPES0 is 1 > * (externals don't alter MSR:HV) > - * > - * AIL is initialized here but can be cleared by > - * selected exceptions > */ > #if defined(TARGET_PPC64) > if (excp_model == POWERPC_EXCP_POWER7 || > excp_model == POWERPC_EXCP_POWER8 || > excp_model == POWERPC_EXCP_POWER9) { > lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); > - if (excp_model != POWERPC_EXCP_POWER7) { > - ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; > - } else { > - ail = 0; > - } > } else > #endif /* defined(TARGET_PPC64) */ > { > lpes0 = true; > - ail = 0; > } > > /* > @@ -315,7 +392,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > */ > new_msr |= (target_ulong)MSR_HVB; > } > - ail = 0; > > /* machine check exceptions don't have ME set */ > new_msr &= ~((target_ulong)1 << MSR_ME); > @@ -519,7 +595,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > "exception %d with no HV support\n", excp); > } > } > - ail = 0; > break; > case POWERPC_EXCP_DSEG: /* Data segment exception */ > case POWERPC_EXCP_ISEG: /* Instruction segment exception */ > @@ -790,24 +865,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > } > #endif > > - /* > - * AIL only works if MSR[IR] and MSR[DR] are both enabled. > - */ > - if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) { > - ail = 0; > - } > - > - /* > - * AIL does not work if there is a MSR[HV] 0->1 transition and the > - * partition is in HPT mode. For radix guests, such interrupts are > - * allowed to be delivered to the hypervisor in ail mode. > - */ > - if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) { > - if (!(env->spr[SPR_LPCR] & LPCR_HR)) { > - ail = 0; > - } > - } > - > vector = env->excp_vectors[excp]; > if (vector == (target_ulong)-1ULL) { > cpu_abort(cs, "Raised an exception without defined vector %d\n", > @@ -848,23 +905,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > /* Save MSR */ > env->spr[srr1] = msr; > > - /* Handle AIL */ > - if (ail) { > - new_msr |= (1 << MSR_IR) | (1 << MSR_DR); > - vector |= ppc_excp_vector_offset(cs, ail); > - } > - > #if defined(TARGET_PPC64) > } else { > - /* scv AIL is a little different */ > - if (ail) { > - new_msr |= (1 << MSR_IR) | (1 << MSR_DR); > - } > - if (ail == AIL_C000_0000_0000_4000) { > - vector |= 0xc000000000003000ull; > - } else { > - vector |= 0x0000000000017000ull; > - } > vector += lev * 0x20; > > env->lr = env->nip; > @@ -872,6 +914,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > #endif > } > > + /* This can update new_msr and vector if AIL applies */ > + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector); > + > powerpc_set_excp_state(cpu, vector, new_msr); > } > > diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc > index 9ab2c32cc4..01fa76e4a0 100644 > --- a/target/ppc/translate_init.c.inc > +++ b/target/ppc/translate_init.c.inc > @@ -3457,7 +3457,7 @@ static void init_excp_POWER9(CPUPPCState *env) > > #if !defined(CONFIG_USER_ONLY) > env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; > - env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000; > + env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; > #endif > } > -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] target/ppc: Add POWER10 exception model 2021-05-01 7:24 [PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model Nicholas Piggin 2021-05-01 7:24 ` [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Nicholas Piggin @ 2021-05-01 7:24 ` Nicholas Piggin 2021-05-03 3:42 ` David Gibson 1 sibling, 1 reply; 5+ messages in thread From: Nicholas Piggin @ 2021-05-01 7:24 UTC (permalink / raw) To: qemu-ppc Cc: Fabiano Rosas, qemu-devel, Nicholas Piggin, Cédric Le Goater, Cédric Le Goater, David Gibson POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=0b10 mode. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- hw/ppc/spapr_hcall.c | 7 ++++- target/ppc/cpu-qom.h | 2 ++ target/ppc/cpu.h | 5 +-- target/ppc/excp_helper.c | 54 +++++++++++++++++++++++++++++++-- target/ppc/translate.c | 3 +- target/ppc/translate_init.c.inc | 2 +- 6 files changed, 65 insertions(+), 8 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 2fbe04a689..7275d0bba1 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, } if (mflags == 1) { - /* AIL=1 is reserved */ + /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ + return H_UNSUPPORTED_FLAG; + } + + if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { + /* AIL=2 is reserved in POWER10 (ISA v3.1) */ return H_UNSUPPORTED_FLAG; } diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 118baf8d41..06b6571bc9 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -116,6 +116,8 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER8, /* POWER9 exception model */ POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, }; /*****************************************************************************/ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index be24a501fc..8a076fab48 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,10 +354,11 @@ typedef struct ppc_v3_pate_t { #define LPCR_PECE_U_SHIFT (63 - 19) #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ -#define LPCR_RMLS_SHIFT (63 - 37) +#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */ #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) +#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */ #define LPCR_ILE PPC_BIT(38) -#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ +#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 73360bb872..5e30a5a056 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -170,7 +170,27 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, * +-------------------------------------------------------+ * * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to - * the hypervisor in AIL mode if the guest is radix. + * the hypervisor in AIL mode if the guest is radix. This is good for + * performance but allows the guest to influence the AIL of hypervisor + * interrupts using its MSR, and also the hypervisor must disallow guest + * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to + * use AIL for its MSR[HV] 0->1 interrupts. + * + * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to + * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and + * MSR[HV] 1->1). + * + * HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1. + * + * POWER10 behaviour is + * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | + * +-----------+------------+-------------+---------+-------------+-----+ + * | a | h | 00/01/10 | 0 | 0 | 0 | + * | a | h | 11 | 0 | 0 | a | + * | a | h | x | 0 | 1 | h | + * | a | h | 00/01/10 | 1 | 1 | 0 | + * | a | h | 11 | 1 | 1 | h | + * +--------------------------------------------------------------------+ */ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, target_ulong msr, @@ -213,6 +233,32 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, /* AIL=1 is reserved, treat it like AIL=0 */ return; } + + } else if (excp_model == POWERPC_EXCP_POWER10) { + if (!mmu_all_on && !hv_escalation) { + /* + * AIL works for HV interrupts even with guest MSR[IR/DR] disabled. + * Guest->guest and HV->HV interrupts do require MMU on. + */ + return; + } + + if (*new_msr & MSR_HVB) { + if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { + /* HV interrupts depend on LPCR[HAIL] */ + return; + } + ail = 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */ + } else { + ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; + } + if (ail == 0) { + return; + } + if (ail == 1 || ail == 2) { + /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */ + return; + } } else { /* Other processors do not support AIL */ return; @@ -328,7 +374,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) #if defined(TARGET_PPC64) if (excp_model == POWERPC_EXCP_POWER7 || excp_model == POWERPC_EXCP_POWER8 || - excp_model == POWERPC_EXCP_POWER9) { + excp_model == POWERPC_EXCP_POWER9 || + excp_model == POWERPC_EXCP_POWER10) { lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); } else #endif /* defined(TARGET_PPC64) */ @@ -848,7 +895,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) } else if (env->spr[SPR_LPCR] & LPCR_ILE) { new_msr |= (target_ulong)1 << MSR_LE; } - } else if (excp_model == POWERPC_EXCP_POWER9) { + } else if (excp_model == POWERPC_EXCP_POWER9 || + excp_model == POWERPC_EXCP_POWER10) { if (new_msr & MSR_HVB) { if (env->spr[SPR_HID0] & HID0_POWER9_HILE) { new_msr |= (target_ulong)1 << MSR_LE; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a53463b9b8..3bbd4cf6ac 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) #if defined(TARGET_PPC64) if (env->excp_model == POWERPC_EXCP_POWER7 || env->excp_model == POWERPC_EXCP_POWER8 || - env->excp_model == POWERPC_EXCP_POWER9) { + env->excp_model == POWERPC_EXCP_POWER9 || + env->excp_model == POWERPC_EXCP_POWER10) { qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 01fa76e4a0..78cd2243f4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -9317,7 +9317,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->radix_page_info = &POWER10_radix_page_info; pcc->lrg_decr_bits = 56; #endif - pcc->excp_model = POWERPC_EXCP_POWER9; + pcc->excp_model = POWERPC_EXCP_POWER10; pcc->bus_model = PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach = bfd_mach_ppc64; pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | -- 2.23.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] target/ppc: Add POWER10 exception model 2021-05-01 7:24 ` [PATCH 2/2] target/ppc: Add POWER10 exception model Nicholas Piggin @ 2021-05-03 3:42 ` David Gibson 0 siblings, 0 replies; 5+ messages in thread From: David Gibson @ 2021-05-03 3:42 UTC (permalink / raw) To: Nicholas Piggin Cc: Cédric Le Goater, Cédric Le Goater, qemu-ppc, qemu-devel, Fabiano Rosas [-- Attachment #1: Type: text/plain, Size: 8615 bytes --] On Sat, May 01, 2021 at 05:24:35PM +1000, Nicholas Piggin wrote: > POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], > and it removes support for the LPCR[AIL]=0b10 mode. > > Reviewed-by: Cédric Le Goater <clg@kaod.org> > Tested-by: Cédric Le Goater <clg@kaod.org> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Applied to ppc-for-6.1, thanks. > --- > hw/ppc/spapr_hcall.c | 7 ++++- > target/ppc/cpu-qom.h | 2 ++ > target/ppc/cpu.h | 5 +-- > target/ppc/excp_helper.c | 54 +++++++++++++++++++++++++++++++-- > target/ppc/translate.c | 3 +- > target/ppc/translate_init.c.inc | 2 +- > 6 files changed, 65 insertions(+), 8 deletions(-) > > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > index 2fbe04a689..7275d0bba1 100644 > --- a/hw/ppc/spapr_hcall.c > +++ b/hw/ppc/spapr_hcall.c > @@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, > } > > if (mflags == 1) { > - /* AIL=1 is reserved */ > + /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ > + return H_UNSUPPORTED_FLAG; > + } > + > + if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { > + /* AIL=2 is reserved in POWER10 (ISA v3.1) */ > return H_UNSUPPORTED_FLAG; > } > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > index 118baf8d41..06b6571bc9 100644 > --- a/target/ppc/cpu-qom.h > +++ b/target/ppc/cpu-qom.h > @@ -116,6 +116,8 @@ enum powerpc_excp_t { > POWERPC_EXCP_POWER8, > /* POWER9 exception model */ > POWERPC_EXCP_POWER9, > + /* POWER10 exception model */ > + POWERPC_EXCP_POWER10, > }; > > /*****************************************************************************/ > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index be24a501fc..8a076fab48 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -354,10 +354,11 @@ typedef struct ppc_v3_pate_t { > #define LPCR_PECE_U_SHIFT (63 - 19) > #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) > #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ > -#define LPCR_RMLS_SHIFT (63 - 37) > +#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */ > #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) > +#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */ > #define LPCR_ILE PPC_BIT(38) > -#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ > +#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ > #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) > #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ > #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 73360bb872..5e30a5a056 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -170,7 +170,27 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, > * +-------------------------------------------------------+ > * > * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to > - * the hypervisor in AIL mode if the guest is radix. > + * the hypervisor in AIL mode if the guest is radix. This is good for > + * performance but allows the guest to influence the AIL of hypervisor > + * interrupts using its MSR, and also the hypervisor must disallow guest > + * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to > + * use AIL for its MSR[HV] 0->1 interrupts. > + * > + * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to > + * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and > + * MSR[HV] 1->1). > + * > + * HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1. > + * > + * POWER10 behaviour is > + * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | > + * +-----------+------------+-------------+---------+-------------+-----+ > + * | a | h | 00/01/10 | 0 | 0 | 0 | > + * | a | h | 11 | 0 | 0 | a | > + * | a | h | x | 0 | 1 | h | > + * | a | h | 00/01/10 | 1 | 1 | 0 | > + * | a | h | 11 | 1 | 1 | h | > + * +--------------------------------------------------------------------+ > */ > static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, > target_ulong msr, > @@ -213,6 +233,32 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, > /* AIL=1 is reserved, treat it like AIL=0 */ > return; > } > + > + } else if (excp_model == POWERPC_EXCP_POWER10) { > + if (!mmu_all_on && !hv_escalation) { > + /* > + * AIL works for HV interrupts even with guest MSR[IR/DR] disabled. > + * Guest->guest and HV->HV interrupts do require MMU on. > + */ > + return; > + } > + > + if (*new_msr & MSR_HVB) { > + if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { > + /* HV interrupts depend on LPCR[HAIL] */ > + return; > + } > + ail = 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */ > + } else { > + ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; > + } > + if (ail == 0) { > + return; > + } > + if (ail == 1 || ail == 2) { > + /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */ > + return; > + } > } else { > /* Other processors do not support AIL */ > return; > @@ -328,7 +374,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > #if defined(TARGET_PPC64) > if (excp_model == POWERPC_EXCP_POWER7 || > excp_model == POWERPC_EXCP_POWER8 || > - excp_model == POWERPC_EXCP_POWER9) { > + excp_model == POWERPC_EXCP_POWER9 || > + excp_model == POWERPC_EXCP_POWER10) { > lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); > } else > #endif /* defined(TARGET_PPC64) */ > @@ -848,7 +895,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) > } else if (env->spr[SPR_LPCR] & LPCR_ILE) { > new_msr |= (target_ulong)1 << MSR_LE; > } > - } else if (excp_model == POWERPC_EXCP_POWER9) { > + } else if (excp_model == POWERPC_EXCP_POWER9 || > + excp_model == POWERPC_EXCP_POWER10) { > if (new_msr & MSR_HVB) { > if (env->spr[SPR_HID0] & HID0_POWER9_HILE) { > new_msr |= (target_ulong)1 << MSR_LE; > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index a53463b9b8..3bbd4cf6ac 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) > #if defined(TARGET_PPC64) > if (env->excp_model == POWERPC_EXCP_POWER7 || > env->excp_model == POWERPC_EXCP_POWER8 || > - env->excp_model == POWERPC_EXCP_POWER9) { > + env->excp_model == POWERPC_EXCP_POWER9 || > + env->excp_model == POWERPC_EXCP_POWER10) { > qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", > env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); > } > diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc > index 01fa76e4a0..78cd2243f4 100644 > --- a/target/ppc/translate_init.c.inc > +++ b/target/ppc/translate_init.c.inc > @@ -9317,7 +9317,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) > pcc->radix_page_info = &POWER10_radix_page_info; > pcc->lrg_decr_bits = 56; > #endif > - pcc->excp_model = POWERPC_EXCP_POWER9; > + pcc->excp_model = POWERPC_EXCP_POWER10; > pcc->bus_model = PPC_FLAGS_INPUT_POWER9; > pcc->bfd_mach = bfd_mach_ppc64; > pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-05-03 4:39 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-01 7:24 [PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model Nicholas Piggin 2021-05-01 7:24 ` [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Nicholas Piggin 2021-05-03 3:41 ` David Gibson 2021-05-01 7:24 ` [PATCH 2/2] target/ppc: Add POWER10 exception model Nicholas Piggin 2021-05-03 3:42 ` David Gibson
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