From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, groug@kaod.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags
Date: Tue, 4 May 2021 15:52:39 +1000 [thread overview]
Message-ID: <20210504055312.306823-14-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au>
From: Richard Henderson <richard.henderson@linaro.org>
Because these bits were not in hflags, the code generated
for single-stepping on BookE was essentially random.
Recompute hflags when storing to dbcr0.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-5-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper_regs.c | 24 +++++++++++++++++-------
target/ppc/misc_helper.c | 3 +++
target/ppc/translate.c | 11 -----------
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index df9673b90f..e345966b6b 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -114,13 +114,23 @@ void hreg_compute_hflags(CPUPPCState *env)
hflags |= le << MSR_LE;
}
- if (ppc_flags & POWERPC_FLAG_BE) {
- QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
- msr_mask |= 1 << MSR_BE;
- }
- if (ppc_flags & POWERPC_FLAG_SE) {
- QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
- msr_mask |= 1 << MSR_SE;
+ if (ppc_flags & POWERPC_FLAG_DE) {
+ target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
+ if (dbcr0 & DBCR0_ICMP) {
+ hflags |= 1 << HFLAGS_SE;
+ }
+ if (dbcr0 & DBCR0_BRT) {
+ hflags |= 1 << HFLAGS_BE;
+ }
+ } else {
+ if (ppc_flags & POWERPC_FLAG_BE) {
+ QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
+ msr_mask |= 1 << MSR_BE;
+ }
+ if (ppc_flags & POWERPC_FLAG_SE) {
+ QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
+ msr_mask |= 1 << MSR_SE;
+ }
}
if (msr_is_64bit(env, msr)) {
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index b04b4d7c6e..002958be26 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
{
+ /* Bits 26 & 27 affect single-stepping. */
+ hreg_compute_hflags(env);
+ /* Bits 28 & 29 affect reset or shutdown. */
store_40x_dbcr0(env, val);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a85b890bb0..7912495f28 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
if ((hflags >> HFLAGS_BE) & 1) {
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
}
- if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
- ctx->singlestep_enabled = 0;
- target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
- if (dbcr0 & DBCR0_ICMP) {
- ctx->singlestep_enabled |= CPU_SINGLE_STEP;
- }
- if (dbcr0 & DBCR0_BRT) {
- ctx->singlestep_enabled |= CPU_BRANCH_STEP;
- }
-
- }
if (unlikely(ctx->base.singlestep_enabled)) {
ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}
--
2.31.1
next prev parent reply other threads:[~2021-05-04 6:08 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-04 5:52 [PULL 00/46] ppc-for-6.1 queue 20210504 David Gibson
2021-05-04 5:52 ` [PULL 01/46] hw/ppc/mac_newworld: Restrict RAM to 2 GiB David Gibson
2021-05-04 5:52 ` [PULL 02/46] target/ppc: Move helper_regs.h functions out-of-line David Gibson
2021-05-04 5:52 ` [PULL 03/46] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags David Gibson
2021-05-04 5:52 ` [PULL 04/46] target/ppc: Properly sync cpu state with new msr in cpu_load_old David Gibson
2021-05-04 5:52 ` [PULL 05/46] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr David Gibson
2021-05-04 5:52 ` [PULL 06/46] target/ppc: Retain hflags_nmsr only for migration David Gibson
2021-05-04 5:52 ` [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1} David Gibson
2021-05-04 5:52 ` [PULL 08/46] hw/ppc/pnv_core: Update hflags after setting msr David Gibson
2021-05-04 5:52 ` [PULL 09/46] hw/ppc/spapr_rtas: " David Gibson
2021-05-04 5:52 ` [PULL 10/46] target/ppc: Extract post_load_update_msr David Gibson
2021-05-04 5:52 ` [PULL 11/46] target/ppc: Disconnect hflags from MSR David Gibson
2021-05-04 5:52 ` [PULL 12/46] target/ppc: Reduce env->hflags to uint32_t David Gibson
2021-05-04 5:52 ` David Gibson [this message]
2021-05-04 5:52 ` [PULL 14/46] target/ppc: Create helper_scv David Gibson
2021-05-04 5:52 ` [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags David Gibson
2021-05-04 5:52 ` [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags David Gibson
2021-05-04 5:52 ` [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx David Gibson
2021-05-04 5:52 ` [PULL 18/46] linux-user/ppc: Fix msr updates for signal handling David Gibson
2021-05-04 5:52 ` [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG David Gibson
2021-05-04 5:52 ` [PULL 20/46] vt82c686: QOM-ify superio related functionality David Gibson
2021-05-04 5:52 ` [PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO David Gibson
2021-05-04 5:52 ` [PULL 22/46] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it David Gibson
2021-05-04 5:52 ` [PULL 23/46] vt82c686: Add emulation of VT8231 south bridge David Gibson
2021-05-04 5:52 ` [PULL 24/46] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller David Gibson
2021-05-04 5:52 ` [PULL 25/46] hw/ppc: Add emulation of Genesi/bPlan Pegasos II David Gibson
2021-05-04 5:52 ` [PULL 26/46] spapr: Rename RTAS_MAX_ADDR to FDT_MAX_ADDR David Gibson
2021-05-04 5:52 ` [PULL 27/46] ppc/spapr: Add support for implement support for H_SCM_HEALTH David Gibson
2021-05-04 5:52 ` [PULL 28/46] roms/Makefile: Update ppce500 u-boot build directory name David Gibson
2021-05-04 5:52 ` [PULL 29/46] roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support David Gibson
2021-05-04 5:52 ` [PULL 30/46] docs/system: ppc: Add documentation for ppce500 machine David Gibson
2021-05-04 5:52 ` [PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour David Gibson
2021-05-04 5:52 ` [PULL 32/46] target/ppc: POWER10 supports scv David Gibson
2021-05-04 5:52 ` [PULL 33/46] ppc: Rename current DAWR macros and variables David Gibson
2021-05-04 5:53 ` [PULL 34/46] spapr.c: do not use MachineClass::max_cpus to limit CPUs David Gibson
2021-05-04 5:53 ` [PULL 35/46] spapr.h: increase FDT_MAX_SIZE David Gibson
2021-05-04 5:53 ` [PULL 36/46] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical() David Gibson
2021-05-04 5:53 ` [PULL 37/46] target/ppc: code motion from translate_init.c.inc to gdbstub.c David Gibson
2021-05-04 5:53 ` [PULL 38/46] target/ppc: move opcode table logic to translate.c David Gibson
2021-05-04 5:53 ` [PULL 39/46] target/ppc: rework AIL logic in interrupt delivery David Gibson
2021-05-04 5:53 ` [PULL 40/46] target/ppc: Add POWER10 exception model David Gibson
2021-05-04 5:53 ` [PULL 41/46] target/ppc: Clean up _spr_register et al David Gibson
2021-05-04 5:53 ` [PULL 42/46] target/ppc: Reduce the size of ppc_spr_t David Gibson
2021-05-04 5:53 ` [PULL 43/46] target/ppc: removed VSCR from SPR registration David Gibson
2021-05-04 5:53 ` [PULL 44/46] hw/intc/spapr_xive: Use device_cold_reset() instead of device_legacy_reset() David Gibson
2021-05-04 5:53 ` [PULL 45/46] hw/ppc/spapr_vio: Reset TCE table object with device_cold_reset() David Gibson
2021-05-04 5:53 ` [PULL 46/46] hw/ppc/pnv_psi: Use device_cold_reset() instead of device_legacy_reset() David Gibson
2021-05-06 17:54 ` [PULL 00/46] ppc-for-6.1 queue 20210504 Peter Maydell
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