From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH v6 04/17] target/riscv: rvb: logic-with-negate
Date: Thu, 6 May 2021 00:06:05 +0800 [thread overview]
Message-ID: <20210505160620.15723-5-frank.chang@sifive.com> (raw)
In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com>
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f7671872d2..a4d95ea6217 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -663,6 +663,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 4a5d271b438..b8676785c6f 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_andc_tl);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_orc_tl);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_eqv_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
next prev parent reply other threads:[~2021-05-05 16:29 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
2021-05-05 16:06 ` [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-05-05 16:06 ` [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-05-06 2:04 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 03/17] target/riscv: rvb: count bits set frank.chang
2021-05-05 16:06 ` frank.chang [this message]
2021-05-05 16:06 ` [PATCH v6 05/17] target/riscv: rvb: pack two words into one register frank.chang
2021-05-05 16:06 ` [PATCH v6 06/17] target/riscv: rvb: min/max instructions frank.chang
2021-05-05 16:06 ` [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions frank.chang
2021-05-05 16:06 ` [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-05-10 7:23 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 09/17] target/riscv: rvb: single-bit instructions frank.chang
2021-05-10 7:24 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 10/17] target/riscv: rvb: shift ones frank.chang
2021-05-10 7:26 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right) frank.chang
2021-05-20 7:11 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 12/17] target/riscv: rvb: generalized reverse frank.chang
2021-05-05 16:06 ` [PATCH v6 13/17] target/riscv: rvb: generalized or-combine frank.chang
2021-05-05 16:06 ` [PATCH v6 14/17] target/riscv: rvb: address calculation frank.chang
2021-05-05 16:06 ` [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-05-05 16:06 ` [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-05-05 16:06 ` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang
2021-05-27 22:05 ` Alistair Francis
2021-05-27 22:08 ` [PATCH v6 00/17] support subsets of bitmanip extension Alistair Francis
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