Re: [PATCH v6 09/17] target/riscv: rvb: single-bit instructions

[Alistair Francis <alistair23@gmail.com>]

On Thu, May 6, 2021 at 2:39 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn32.decode              | 17 +++++
>  target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
>  target/riscv/translate.c                | 61 ++++++++++++++++
>  3 files changed, 175 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 93619846349..433b601b934 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -676,6 +676,15 @@ min        0000101 .......... 100 ..... 0110011 @r
>  minu       0000101 .......... 101 ..... 0110011 @r
>  max        0000101 .......... 110 ..... 0110011 @r
>  maxu       0000101 .......... 111 ..... 0110011 @r
> +bset       0010100 .......... 001 ..... 0110011 @r
> +bclr       0100100 .......... 001 ..... 0110011 @r
> +binv       0110100 .......... 001 ..... 0110011 @r
> +bext       0100100 .......... 101 ..... 0110011 @r
> +
> +bseti      00101. ........... 001 ..... 0010011 @sh
> +bclri      01001. ........... 001 ..... 0010011 @sh
> +binvi      01101. ........... 001 ..... 0010011 @sh
> +bexti      01001. ........... 101 ..... 0010011 @sh
>
>  # *** RV64B Standard Extension (in addition to RV32B) ***
>  clzw       0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -684,3 +693,11 @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
>
>  packw      0000100 .......... 100 ..... 0111011 @r
>  packuw     0100100 .......... 100 ..... 0111011 @r
> +bsetw      0010100 .......... 001 ..... 0111011 @r
> +bclrw      0100100 .......... 001 ..... 0111011 @r
> +binvw      0110100 .......... 001 ..... 0111011 @r
> +bextw      0100100 .......... 101 ..... 0111011 @r
> +
> +bsetiw     0010100 .......... 001 ..... 0011011 @sh5
> +bclriw     0100100 .......... 001 ..... 0011011 @sh5
> +binviw     0110100 .......... 001 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 3d594e8cb40..69e5af44a18 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
>      return gen_unary(ctx, a, tcg_gen_ext16s_tl);
>  }
>
> +static bool trans_bset(DisasContext *ctx, arg_bset *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shift(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shifti(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shift(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shifti(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_binv(DisasContext *ctx, arg_binv *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shift(ctx, a, gen_binv);
> +}
> +
> +static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shifti(ctx, a, gen_binv);
> +}
> +
> +static bool trans_bext(DisasContext *ctx, arg_bext *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shift(ctx, a, gen_bext);
> +}
> +
> +static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> +{
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shifti(ctx, a, gen_bext);
> +}
> +
>  static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
>  {
>      REQUIRE_64BIT(ctx);
> @@ -141,3 +189,52 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
>      REQUIRE_EXT(ctx, RVB);
>      return gen_arith(ctx, a, gen_packuw);
>  }
> +
> +static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftw(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftiw(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftw(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftiw(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftw(ctx, a, gen_binv);
> +}
> +
> +static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftiw(ctx, a, gen_binv);
> +}
> +
> +static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_EXT(ctx, RVB);
> +    return gen_shiftw(ctx, a, gen_bext);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 292cf09932d..e12240d1255 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -571,6 +571,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
>      tcg_temp_free(t);
>  }
>
> +static void gen_sbop_mask(TCGv ret, TCGv shamt)
> +{
> +    tcg_gen_movi_tl(ret, 1);
> +    tcg_gen_shl_tl(ret, ret, shamt);
> +}
> +
> +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> +    TCGv t = tcg_temp_new();
> +
> +    gen_sbop_mask(t, shamt);
> +    tcg_gen_or_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}
> +
> +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> +    TCGv t = tcg_temp_new();
> +
> +    gen_sbop_mask(t, shamt);
> +    tcg_gen_andc_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}
> +
> +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> +    TCGv t = tcg_temp_new();
> +
> +    gen_sbop_mask(t, shamt);
> +    tcg_gen_xor_tl(ret, arg1, t);
> +
> +    tcg_temp_free(t);
> +}
> +
> +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> +    tcg_gen_shr_tl(ret, arg1, shamt);
> +    tcg_gen_andi_tl(ret, ret, 1);
> +}
> +
>  static void gen_ctzw(TCGv ret, TCGv arg1)
>  {
>      tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> @@ -673,6 +715,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
>      return true;
>  }
>
> +static bool gen_shiftw(DisasContext *ctx, arg_r *a,
> +                       void(*func)(TCGv, TCGv, TCGv))
> +{
> +    TCGv source1 = tcg_temp_new();
> +    TCGv source2 = tcg_temp_new();
> +
> +    gen_get_gpr(source1, a->rs1);
> +    gen_get_gpr(source2, a->rs2);
> +
> +    tcg_gen_andi_tl(source2, source2, 31);
> +    (*func)(source1, source1, source2);
> +    tcg_gen_ext32s_tl(source1, source1);
> +
> +    gen_set_gpr(a->rd, source1);
> +    tcg_temp_free(source1);
> +    tcg_temp_free(source2);
> +    return true;
> +}
> +
>  static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
>                          void(*func)(TCGv, TCGv, TCGv))
>  {
> --
> 2.17.1
>
>