* [PATCH v3 0/4] hw/ppc: code motion to compile without TCG
@ 2021-05-06 16:39 Lucas Mateus Castro (alqotel)
2021-05-06 16:39 ` [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu Lucas Mateus Castro (alqotel)
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Lucas Mateus Castro (alqotel) @ 2021-05-06 16:39 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: bruno.larsen, Lucas Mateus Castro (alqotel), farosas, david
After the feedback from v2 I changed:
* The name _tcg or _tcg_only to _softmmu in spapr_softmmu,
* Divided h_resize_hpt_prepare and h_resize_hpt_commit into a KVM and
softmmu parts,
* How to register some hypercalls in a !TCG environment in spapr_hcall.c,
* Where to move the functions ppc_hash64_filter_pagesizes and
ppc_store_lpcr,
* Changed registration verification in pnv_dt_core and spapr_dt_cpu.
This patch aims to move and change some functions to make some progress
toward enabling the disable-tcg option on PPC.
Lucas Mateus Castro (alqotel) (4):
hw/ppc: Moved hypercalls that depend on softmmu to new file
target/ppc: moved function out of mmu-hash64
target/ppc: moved ppc_store_lpcr to misc_helper.c
hw/ppc: Altered calls from oea_read to read
hw/ppc/meson.build | 3 +
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 4 +-
hw/ppc/spapr_caps.c | 59 ++++
hw/ppc/spapr_hcall.c | 608 ++-----------------------------------
hw/ppc/spapr_softmmu.c | 627 +++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 6 +
target/ppc/cpu.h | 1 +
target/ppc/misc_helper.c | 10 +
target/ppc/mmu-hash64.c | 67 -----
target/ppc/mmu-hash64.h | 4 -
11 files changed, 741 insertions(+), 650 deletions(-)
create mode 100644 hw/ppc/spapr_softmmu.c
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu
2021-05-06 16:39 [PATCH v3 0/4] hw/ppc: code motion to compile without TCG Lucas Mateus Castro (alqotel)
@ 2021-05-06 16:39 ` Lucas Mateus Castro (alqotel)
2021-05-07 3:12 ` David Gibson
2021-05-06 16:39 ` [PATCH v3 2/4] target/ppc: moved function out of mmu-hash64 Lucas Mateus Castro (alqotel)
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Lucas Mateus Castro (alqotel) @ 2021-05-06 16:39 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: bruno.larsen, Lucas Mateus Castro (alqotel), farosas, david
The hypercalls h_enter, h_remove, h_bulk_remove, h_protect, and h_read,
have been moved to spapr_softmmu.c with the functions they depend on. The
functions is_ram_address and push_sregs_to_kvm_pr are not static anymore
as functions on both spapr_hcall.c and spapr_softmmu.c depend on them.
The hypercalls h_resize_hpt_prepare and h_resize_hpt_commit have been
divided, the KVM part stayed in spapr_hcall.c while the softmmu part
was moved to spapr_softmmu.c
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
hw/ppc/meson.build | 3 +
hw/ppc/spapr_hcall.c | 608 +++------------------------------------
hw/ppc/spapr_softmmu.c | 627 +++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 6 +
4 files changed, 668 insertions(+), 576 deletions(-)
create mode 100644 hw/ppc/spapr_softmmu.c
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 86d6f379d1..597d974dd4 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -29,6 +29,9 @@ ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files(
'spapr_numa.c',
'pef.c',
))
+ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_TCG'], if_true: files(
+ 'spapr_softmmu.c',
+))
ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c'))
ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_LINUX'], if_true: files(
'spapr_pci_vfio.c',
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 7275d0bba1..62dd015b70 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -27,18 +27,7 @@ static bool has_spr(PowerPCCPU *cpu, int spr)
return cpu->env.spr_cb[spr].name != NULL;
}
-static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
-{
- /*
- * hash value/pteg group index is normalized by HPT mask
- */
- if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
- return false;
- }
- return true;
-}
-
-static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
+bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
{
MachineState *machine = MACHINE(spapr);
DeviceMemoryState *dms = machine->device_memory;
@@ -54,355 +43,6 @@ static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
return false;
}
-static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- target_ulong flags = args[0];
- target_ulong ptex = args[1];
- target_ulong pteh = args[2];
- target_ulong ptel = args[3];
- unsigned apshift;
- target_ulong raddr;
- target_ulong slot;
- const ppc_hash_pte64_t *hptes;
-
- apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
- if (!apshift) {
- /* Bad page size encoding */
- return H_PARAMETER;
- }
-
- raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
-
- if (is_ram_address(spapr, raddr)) {
- /* Regular RAM - should have WIMG=0010 */
- if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
- return H_PARAMETER;
- }
- } else {
- target_ulong wimg_flags;
- /* Looks like an IO address */
- /* FIXME: What WIMG combinations could be sensible for IO?
- * For now we allow WIMG=010x, but are there others? */
- /* FIXME: Should we check against registered IO addresses? */
- wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
-
- if (wimg_flags != HPTE64_R_I &&
- wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
- return H_PARAMETER;
- }
- }
-
- pteh &= ~0x60ULL;
-
- if (!valid_ptex(cpu, ptex)) {
- return H_PARAMETER;
- }
-
- slot = ptex & 7ULL;
- ptex = ptex & ~7ULL;
-
- if (likely((flags & H_EXACT) == 0)) {
- hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
- for (slot = 0; slot < 8; slot++) {
- if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
- break;
- }
- }
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
- if (slot == 8) {
- return H_PTEG_FULL;
- }
- } else {
- hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
- if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
- ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
- return H_PTEG_FULL;
- }
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
- }
-
- spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
-
- args[0] = ptex + slot;
- return H_SUCCESS;
-}
-
-typedef enum {
- REMOVE_SUCCESS = 0,
- REMOVE_NOT_FOUND = 1,
- REMOVE_PARM = 2,
- REMOVE_HW = 3,
-} RemoveResult;
-
-static RemoveResult remove_hpte(PowerPCCPU *cpu
- , target_ulong ptex,
- target_ulong avpn,
- target_ulong flags,
- target_ulong *vp, target_ulong *rp)
-{
- const ppc_hash_pte64_t *hptes;
- target_ulong v, r;
-
- if (!valid_ptex(cpu, ptex)) {
- return REMOVE_PARM;
- }
-
- hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
- v = ppc_hash64_hpte0(cpu, hptes, 0);
- r = ppc_hash64_hpte1(cpu, hptes, 0);
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
-
- if ((v & HPTE64_V_VALID) == 0 ||
- ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
- ((flags & H_ANDCOND) && (v & avpn) != 0)) {
- return REMOVE_NOT_FOUND;
- }
- *vp = v;
- *rp = r;
- spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
- ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
- return REMOVE_SUCCESS;
-}
-
-static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUPPCState *env = &cpu->env;
- target_ulong flags = args[0];
- target_ulong ptex = args[1];
- target_ulong avpn = args[2];
- RemoveResult ret;
-
- ret = remove_hpte(cpu, ptex, avpn, flags,
- &args[0], &args[1]);
-
- switch (ret) {
- case REMOVE_SUCCESS:
- check_tlb_flush(env, true);
- return H_SUCCESS;
-
- case REMOVE_NOT_FOUND:
- return H_NOT_FOUND;
-
- case REMOVE_PARM:
- return H_PARAMETER;
-
- case REMOVE_HW:
- return H_HARDWARE;
- }
-
- g_assert_not_reached();
-}
-
-#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
-#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
-#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
-#define H_BULK_REMOVE_END 0xc000000000000000ULL
-#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
-#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
-#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
-#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
-#define H_BULK_REMOVE_HW 0x3000000000000000ULL
-#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
-#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
-#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
-#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
-#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
-#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
-
-#define H_BULK_REMOVE_MAX_BATCH 4
-
-static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUPPCState *env = &cpu->env;
- int i;
- target_ulong rc = H_SUCCESS;
-
- for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
- target_ulong *tsh = &args[i*2];
- target_ulong tsl = args[i*2 + 1];
- target_ulong v, r, ret;
-
- if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
- break;
- } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
- return H_PARAMETER;
- }
-
- *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
- *tsh |= H_BULK_REMOVE_RESPONSE;
-
- if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
- *tsh |= H_BULK_REMOVE_PARM;
- return H_PARAMETER;
- }
-
- ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
- (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
- &v, &r);
-
- *tsh |= ret << 60;
-
- switch (ret) {
- case REMOVE_SUCCESS:
- *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
- break;
-
- case REMOVE_PARM:
- rc = H_PARAMETER;
- goto exit;
-
- case REMOVE_HW:
- rc = H_HARDWARE;
- goto exit;
- }
- }
- exit:
- check_tlb_flush(env, true);
-
- return rc;
-}
-
-static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUPPCState *env = &cpu->env;
- target_ulong flags = args[0];
- target_ulong ptex = args[1];
- target_ulong avpn = args[2];
- const ppc_hash_pte64_t *hptes;
- target_ulong v, r;
-
- if (!valid_ptex(cpu, ptex)) {
- return H_PARAMETER;
- }
-
- hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
- v = ppc_hash64_hpte0(cpu, hptes, 0);
- r = ppc_hash64_hpte1(cpu, hptes, 0);
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
-
- if ((v & HPTE64_V_VALID) == 0 ||
- ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
- return H_NOT_FOUND;
- }
-
- r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
- HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
- r |= (flags << 55) & HPTE64_R_PP0;
- r |= (flags << 48) & HPTE64_R_KEY_HI;
- r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
- spapr_store_hpte(cpu, ptex,
- (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
- ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
- /* Flush the tlb */
- check_tlb_flush(env, true);
- /* Don't need a memory barrier, due to qemu's global lock */
- spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
- return H_SUCCESS;
-}
-
-static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- target_ulong flags = args[0];
- target_ulong ptex = args[1];
- int i, ridx, n_entries = 1;
- const ppc_hash_pte64_t *hptes;
-
- if (!valid_ptex(cpu, ptex)) {
- return H_PARAMETER;
- }
-
- if (flags & H_READ_4) {
- /* Clear the two low order bits */
- ptex &= ~(3ULL);
- n_entries = 4;
- }
-
- hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries);
- for (i = 0, ridx = 0; i < n_entries; i++) {
- args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i);
- args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i);
- }
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries);
-
- return H_SUCCESS;
-}
-
-struct SpaprPendingHpt {
- /* These fields are read-only after initialization */
- int shift;
- QemuThread thread;
-
- /* These fields are protected by the BQL */
- bool complete;
-
- /* These fields are private to the preparation thread if
- * !complete, otherwise protected by the BQL */
- int ret;
- void *hpt;
-};
-
-static void free_pending_hpt(SpaprPendingHpt *pending)
-{
- if (pending->hpt) {
- qemu_vfree(pending->hpt);
- }
-
- g_free(pending);
-}
-
-static void *hpt_prepare_thread(void *opaque)
-{
- SpaprPendingHpt *pending = opaque;
- size_t size = 1ULL << pending->shift;
-
- pending->hpt = qemu_try_memalign(size, size);
- if (pending->hpt) {
- memset(pending->hpt, 0, size);
- pending->ret = H_SUCCESS;
- } else {
- pending->ret = H_NO_MEM;
- }
-
- qemu_mutex_lock_iothread();
-
- if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
- /* Ready to go */
- pending->complete = true;
- } else {
- /* We've been cancelled, clean ourselves up */
- free_pending_hpt(pending);
- }
-
- qemu_mutex_unlock_iothread();
- return NULL;
-}
-
-/* Must be called with BQL held */
-static void cancel_hpt_prepare(SpaprMachineState *spapr)
-{
- SpaprPendingHpt *pending = spapr->pending_hpt;
-
- /* Let the thread know it's cancelled */
- spapr->pending_hpt = NULL;
-
- if (!pending) {
- /* Nothing to do */
- return;
- }
-
- if (!pending->complete) {
- /* thread will clean itself up */
- return;
- }
-
- free_pending_hpt(pending);
-}
-
/* Convert a return code from the KVM ioctl()s implementing resize HPT
* into a PAPR hypercall return code */
static target_ulong resize_hpt_convert_rc(int ret)
@@ -448,7 +88,6 @@ static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
{
target_ulong flags = args[0];
int shift = args[1];
- SpaprPendingHpt *pending = spapr->pending_hpt;
uint64_t current_ram_size;
int rc;
@@ -485,182 +124,11 @@ static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
return resize_hpt_convert_rc(rc);
}
- if (pending) {
- /* something already in progress */
- if (pending->shift == shift) {
- /* and it's suitable */
- if (pending->complete) {
- return pending->ret;
- } else {
- return H_LONG_BUSY_ORDER_100_MSEC;
- }
- }
-
- /* not suitable, cancel and replace */
- cancel_hpt_prepare(spapr);
- }
-
- if (!shift) {
- /* nothing to do */
- return H_SUCCESS;
- }
-
- /* start new prepare */
-
- pending = g_new0(SpaprPendingHpt, 1);
- pending->shift = shift;
- pending->ret = H_HARDWARE;
-
- qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
- hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
-
- spapr->pending_hpt = pending;
-
- /* In theory we could estimate the time more accurately based on
- * the new size, but there's not much point */
- return H_LONG_BUSY_ORDER_100_MSEC;
-}
-
-static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
-{
- uint8_t *addr = htab;
-
- addr += pteg * HASH_PTEG_SIZE_64;
- addr += slot * HASH_PTE_SIZE_64;
- return ldq_p(addr);
-}
-
-static void new_hpte_store(void *htab, uint64_t pteg, int slot,
- uint64_t pte0, uint64_t pte1)
-{
- uint8_t *addr = htab;
-
- addr += pteg * HASH_PTEG_SIZE_64;
- addr += slot * HASH_PTE_SIZE_64;
-
- stq_p(addr, pte0);
- stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
-}
-
-static int rehash_hpte(PowerPCCPU *cpu,
- const ppc_hash_pte64_t *hptes,
- void *old_hpt, uint64_t oldsize,
- void *new_hpt, uint64_t newsize,
- uint64_t pteg, int slot)
-{
- uint64_t old_hash_mask = (oldsize >> 7) - 1;
- uint64_t new_hash_mask = (newsize >> 7) - 1;
- target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
- target_ulong pte1;
- uint64_t avpn;
- unsigned base_pg_shift;
- uint64_t hash, new_pteg, replace_pte0;
-
- if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
- return H_SUCCESS;
- }
-
- pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
-
- base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
- assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
- avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
-
- if (pte0 & HPTE64_V_SECONDARY) {
- pteg = ~pteg;
- }
-
- if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
- uint64_t offset, vsid;
-
- /* We only have 28 - 23 bits of offset in avpn */
- offset = (avpn & 0x1f) << 23;
- vsid = avpn >> 5;
- /* We can find more bits from the pteg value */
- if (base_pg_shift < 23) {
- offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
- }
-
- hash = vsid ^ (offset >> base_pg_shift);
- } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
- uint64_t offset, vsid;
-
- /* We only have 40 - 23 bits of seg_off in avpn */
- offset = (avpn & 0x1ffff) << 23;
- vsid = avpn >> 17;
- if (base_pg_shift < 23) {
- offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
- << base_pg_shift;
- }
-
- hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
- } else {
- error_report("rehash_pte: Bad segment size in HPTE");
+ if (kvm_enabled()) {
return H_HARDWARE;
}
- new_pteg = hash & new_hash_mask;
- if (pte0 & HPTE64_V_SECONDARY) {
- assert(~pteg == (hash & old_hash_mask));
- new_pteg = ~new_pteg;
- } else {
- assert(pteg == (hash & old_hash_mask));
- }
- assert((oldsize != newsize) || (pteg == new_pteg));
- replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
- /*
- * Strictly speaking, we don't need all these tests, since we only
- * ever rehash bolted HPTEs. We might in future handle non-bolted
- * HPTEs, though so make the logic correct for those cases as
- * well.
- */
- if (replace_pte0 & HPTE64_V_VALID) {
- assert(newsize < oldsize);
- if (replace_pte0 & HPTE64_V_BOLTED) {
- if (pte0 & HPTE64_V_BOLTED) {
- /* Bolted collision, nothing we can do */
- return H_PTEG_FULL;
- } else {
- /* Discard this hpte */
- return H_SUCCESS;
- }
- }
- }
-
- new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
- return H_SUCCESS;
-}
-
-static int rehash_hpt(PowerPCCPU *cpu,
- void *old_hpt, uint64_t oldsize,
- void *new_hpt, uint64_t newsize)
-{
- uint64_t n_ptegs = oldsize >> 7;
- uint64_t pteg;
- int slot;
- int rc;
-
- for (pteg = 0; pteg < n_ptegs; pteg++) {
- hwaddr ptex = pteg * HPTES_PER_GROUP;
- const ppc_hash_pte64_t *hptes
- = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
-
- if (!hptes) {
- return H_HARDWARE;
- }
-
- for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
- rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
- pteg, slot);
- if (rc != H_SUCCESS) {
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
- return rc;
- }
- }
- ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
- }
-
- return H_SUCCESS;
+ return softmmu_resize_hpt_prepare(cpu, spapr, shift);
}
static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
@@ -676,7 +144,7 @@ static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
}
}
-static void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
+void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
{
CPUState *cs;
@@ -701,9 +169,7 @@ static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
{
target_ulong flags = args[0];
target_ulong shift = args[1];
- SpaprPendingHpt *pending = spapr->pending_hpt;
int rc;
- size_t newsize;
if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
return H_AUTHORITY;
@@ -726,42 +192,14 @@ static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
return rc;
}
- if (flags != 0) {
- return H_PARAMETER;
- }
-
- if (!pending || (pending->shift != shift)) {
- /* no matching prepare */
- return H_CLOSED;
- }
-
- if (!pending->complete) {
- /* prepare has not completed */
- return H_BUSY;
+ if (kvm_enabled()) {
+ return H_HARDWARE;
}
- /* Shouldn't have got past PREPARE without an HPT */
- g_assert(spapr->htab_shift);
-
- newsize = 1ULL << pending->shift;
- rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
- pending->hpt, newsize);
- if (rc == H_SUCCESS) {
- qemu_vfree(spapr->htab);
- spapr->htab = pending->hpt;
- spapr->htab_shift = pending->shift;
-
- push_sregs_to_kvm_pr(spapr);
-
- pending->hpt = NULL; /* so it's not free()d */
- }
+ return softmmu_resize_hpt_commit(cpu, spapr, flags, shift);
+}
- /* Clean up */
- spapr->pending_hpt = NULL;
- free_pending_hpt(pending);
- return rc;
-}
static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong opcode, target_ulong *args)
@@ -2024,16 +1462,34 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
return H_FUNCTION;
}
-static void hypercall_register_types(void)
+#ifndef CONFIG_TCG
+static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ g_assert_not_reached();
+}
+
+static void hypercall_register_softmmu(void)
{
/* hcall-pft */
- spapr_register_hypercall(H_ENTER, h_enter);
- spapr_register_hypercall(H_REMOVE, h_remove);
- spapr_register_hypercall(H_PROTECT, h_protect);
- spapr_register_hypercall(H_READ, h_read);
+ spapr_register_hypercall(H_ENTER, h_softmmu);
+ spapr_register_hypercall(H_REMOVE, h_softmmu);
+ spapr_register_hypercall(H_PROTECT, h_softmmu);
+ spapr_register_hypercall(H_READ, h_softmmu);
/* hcall-bulk */
- spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
+ spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
+}
+#else
+static void hypercall_register_softmmu(void)
+{
+ /* DO NOTHING */
+}
+#endif
+
+static void hypercall_register_types(void)
+{
+ hypercall_register_softmmu();
/* hcall-hpt-resize */
spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
diff --git a/hw/ppc/spapr_softmmu.c b/hw/ppc/spapr_softmmu.c
new file mode 100644
index 0000000000..6c6b86dd3c
--- /dev/null
+++ b/hw/ppc/spapr_softmmu.c
@@ -0,0 +1,627 @@
+#include "qemu/osdep.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "sysemu/hw_accel.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "helper_regs.h"
+#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_cpu_core.h"
+#include "mmu-hash64.h"
+#include "cpu-models.h"
+#include "trace.h"
+#include "kvm_ppc.h"
+#include "hw/ppc/fdt.h"
+#include "hw/ppc/spapr_ovec.h"
+#include "mmu-book3s-v3.h"
+#include "hw/mem/memory-device.h"
+
+static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
+{
+ /*
+ * hash value/pteg group index is normalized by HPT mask
+ */
+ if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
+ return false;
+ }
+ return true;
+}
+
+static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ target_ulong flags = args[0];
+ target_ulong ptex = args[1];
+ target_ulong pteh = args[2];
+ target_ulong ptel = args[3];
+ unsigned apshift;
+ target_ulong raddr;
+ target_ulong slot;
+ const ppc_hash_pte64_t *hptes;
+
+ apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
+ if (!apshift) {
+ /* Bad page size encoding */
+ return H_PARAMETER;
+ }
+
+ raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
+
+ if (is_ram_address(spapr, raddr)) {
+ /* Regular RAM - should have WIMG=0010 */
+ if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
+ return H_PARAMETER;
+ }
+ } else {
+ target_ulong wimg_flags;
+ /* Looks like an IO address */
+ /* FIXME: What WIMG combinations could be sensible for IO?
+ * For now we allow WIMG=010x, but are there others? */
+ /* FIXME: Should we check against registered IO addresses? */
+ wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
+
+ if (wimg_flags != HPTE64_R_I &&
+ wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
+ return H_PARAMETER;
+ }
+ }
+
+ pteh &= ~0x60ULL;
+
+ if (!valid_ptex(cpu, ptex)) {
+ return H_PARAMETER;
+ }
+
+ slot = ptex & 7ULL;
+ ptex = ptex & ~7ULL;
+
+ if (likely((flags & H_EXACT) == 0)) {
+ hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
+ for (slot = 0; slot < 8; slot++) {
+ if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
+ break;
+ }
+ }
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
+ if (slot == 8) {
+ return H_PTEG_FULL;
+ }
+ } else {
+ hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
+ if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
+ return H_PTEG_FULL;
+ }
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
+ }
+
+ spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
+
+ args[0] = ptex + slot;
+ return H_SUCCESS;
+}
+
+typedef enum {
+ REMOVE_SUCCESS = 0,
+ REMOVE_NOT_FOUND = 1,
+ REMOVE_PARM = 2,
+ REMOVE_HW = 3,
+} RemoveResult;
+
+static RemoveResult remove_hpte(PowerPCCPU *cpu
+ , target_ulong ptex,
+ target_ulong avpn,
+ target_ulong flags,
+ target_ulong *vp, target_ulong *rp)
+{
+ const ppc_hash_pte64_t *hptes;
+ target_ulong v, r;
+
+ if (!valid_ptex(cpu, ptex)) {
+ return REMOVE_PARM;
+ }
+
+ hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
+ v = ppc_hash64_hpte0(cpu, hptes, 0);
+ r = ppc_hash64_hpte1(cpu, hptes, 0);
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
+
+ if ((v & HPTE64_V_VALID) == 0 ||
+ ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
+ ((flags & H_ANDCOND) && (v & avpn) != 0)) {
+ return REMOVE_NOT_FOUND;
+ }
+ *vp = v;
+ *rp = r;
+ spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
+ ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
+ return REMOVE_SUCCESS;
+}
+
+static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong ptex = args[1];
+ target_ulong avpn = args[2];
+ RemoveResult ret;
+
+ ret = remove_hpte(cpu, ptex, avpn, flags,
+ &args[0], &args[1]);
+
+ switch (ret) {
+ case REMOVE_SUCCESS:
+ check_tlb_flush(env, true);
+ return H_SUCCESS;
+
+ case REMOVE_NOT_FOUND:
+ return H_NOT_FOUND;
+
+ case REMOVE_PARM:
+ return H_PARAMETER;
+
+ case REMOVE_HW:
+ return H_HARDWARE;
+ }
+
+ g_assert_not_reached();
+}
+
+#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
+#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
+#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
+#define H_BULK_REMOVE_END 0xc000000000000000ULL
+#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
+#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
+#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
+#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
+#define H_BULK_REMOVE_HW 0x3000000000000000ULL
+#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
+#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
+#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
+#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
+#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
+#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
+
+#define H_BULK_REMOVE_MAX_BATCH 4
+
+static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ int i;
+ target_ulong rc = H_SUCCESS;
+
+ for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
+ target_ulong *tsh = &args[i*2];
+ target_ulong tsl = args[i*2 + 1];
+ target_ulong v, r, ret;
+
+ if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
+ break;
+ } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
+ return H_PARAMETER;
+ }
+
+ *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
+ *tsh |= H_BULK_REMOVE_RESPONSE;
+
+ if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
+ *tsh |= H_BULK_REMOVE_PARM;
+ return H_PARAMETER;
+ }
+
+ ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
+ (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
+ &v, &r);
+
+ *tsh |= ret << 60;
+
+ switch (ret) {
+ case REMOVE_SUCCESS:
+ *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
+ break;
+
+ case REMOVE_PARM:
+ rc = H_PARAMETER;
+ goto exit;
+
+ case REMOVE_HW:
+ rc = H_HARDWARE;
+ goto exit;
+ }
+ }
+ exit:
+ check_tlb_flush(env, true);
+
+ return rc;
+}
+
+static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong ptex = args[1];
+ target_ulong avpn = args[2];
+ const ppc_hash_pte64_t *hptes;
+ target_ulong v, r;
+
+ if (!valid_ptex(cpu, ptex)) {
+ return H_PARAMETER;
+ }
+
+ hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
+ v = ppc_hash64_hpte0(cpu, hptes, 0);
+ r = ppc_hash64_hpte1(cpu, hptes, 0);
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
+
+ if ((v & HPTE64_V_VALID) == 0 ||
+ ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
+ return H_NOT_FOUND;
+ }
+
+ r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
+ HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
+ r |= (flags << 55) & HPTE64_R_PP0;
+ r |= (flags << 48) & HPTE64_R_KEY_HI;
+ r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
+ spapr_store_hpte(cpu, ptex,
+ (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
+ ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
+ /* Flush the tlb */
+ check_tlb_flush(env, true);
+ /* Don't need a memory barrier, due to qemu's global lock */
+ spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
+ return H_SUCCESS;
+}
+
+static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ target_ulong flags = args[0];
+ target_ulong ptex = args[1];
+ int i, ridx, n_entries = 1;
+ const ppc_hash_pte64_t *hptes;
+
+ if (!valid_ptex(cpu, ptex)) {
+ return H_PARAMETER;
+ }
+
+ if (flags & H_READ_4) {
+ /* Clear the two low order bits */
+ ptex &= ~(3ULL);
+ n_entries = 4;
+ }
+
+ hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries);
+ for (i = 0, ridx = 0; i < n_entries; i++) {
+ args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i);
+ args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i);
+ }
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries);
+
+ return H_SUCCESS;
+}
+
+struct SpaprPendingHpt {
+ /* These fields are read-only after initialization */
+ int shift;
+ QemuThread thread;
+
+ /* These fields are protected by the BQL */
+ bool complete;
+
+ /* These fields are private to the preparation thread if
+ * !complete, otherwise protected by the BQL */
+ int ret;
+ void *hpt;
+};
+
+static void free_pending_hpt(SpaprPendingHpt *pending)
+{
+ if (pending->hpt) {
+ qemu_vfree(pending->hpt);
+ }
+
+ g_free(pending);
+}
+
+static void *hpt_prepare_thread(void *opaque)
+{
+ SpaprPendingHpt *pending = opaque;
+ size_t size = 1ULL << pending->shift;
+
+ pending->hpt = qemu_try_memalign(size, size);
+ if (pending->hpt) {
+ memset(pending->hpt, 0, size);
+ pending->ret = H_SUCCESS;
+ } else {
+ pending->ret = H_NO_MEM;
+ }
+
+ qemu_mutex_lock_iothread();
+
+ if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
+ /* Ready to go */
+ pending->complete = true;
+ } else {
+ /* We've been cancelled, clean ourselves up */
+ free_pending_hpt(pending);
+ }
+
+ qemu_mutex_unlock_iothread();
+ return NULL;
+}
+
+/* Must be called with BQL held */
+static void cancel_hpt_prepare(SpaprMachineState *spapr)
+{
+ SpaprPendingHpt *pending = spapr->pending_hpt;
+
+ /* Let the thread know it's cancelled */
+ spapr->pending_hpt = NULL;
+
+ if (!pending) {
+ /* Nothing to do */
+ return;
+ }
+
+ if (!pending->complete) {
+ /* thread will clean itself up */
+ return;
+ }
+
+ free_pending_hpt(pending);
+}
+
+target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong shift)
+{
+ SpaprPendingHpt *pending = spapr->pending_hpt;
+
+ if (pending) {
+ /* something already in progress */
+ if (pending->shift == shift) {
+ /* and it's suitable */
+ if (pending->complete) {
+ return pending->ret;
+ } else {
+ return H_LONG_BUSY_ORDER_100_MSEC;
+ }
+ }
+
+ /* not suitable, cancel and replace */
+ cancel_hpt_prepare(spapr);
+ }
+
+ if (!shift) {
+ /* nothing to do */
+ return H_SUCCESS;
+ }
+
+ /* start new prepare */
+
+ pending = g_new0(SpaprPendingHpt, 1);
+ pending->shift = shift;
+ pending->ret = H_HARDWARE;
+
+ qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
+ hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
+
+ spapr->pending_hpt = pending;
+
+ /* In theory we could estimate the time more accurately based on
+ * the new size, but there's not much point */
+ return H_LONG_BUSY_ORDER_100_MSEC;
+}
+
+static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
+{
+ uint8_t *addr = htab;
+
+ addr += pteg * HASH_PTEG_SIZE_64;
+ addr += slot * HASH_PTE_SIZE_64;
+ return ldq_p(addr);
+}
+
+static void new_hpte_store(void *htab, uint64_t pteg, int slot,
+ uint64_t pte0, uint64_t pte1)
+{
+ uint8_t *addr = htab;
+
+ addr += pteg * HASH_PTEG_SIZE_64;
+ addr += slot * HASH_PTE_SIZE_64;
+
+ stq_p(addr, pte0);
+ stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
+}
+
+static int rehash_hpte(PowerPCCPU *cpu,
+ const ppc_hash_pte64_t *hptes,
+ void *old_hpt, uint64_t oldsize,
+ void *new_hpt, uint64_t newsize,
+ uint64_t pteg, int slot)
+{
+ uint64_t old_hash_mask = (oldsize >> 7) - 1;
+ uint64_t new_hash_mask = (newsize >> 7) - 1;
+ target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
+ target_ulong pte1;
+ uint64_t avpn;
+ unsigned base_pg_shift;
+ uint64_t hash, new_pteg, replace_pte0;
+
+ if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
+ return H_SUCCESS;
+ }
+
+ pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
+
+ base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
+ assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
+ avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
+
+ if (pte0 & HPTE64_V_SECONDARY) {
+ pteg = ~pteg;
+ }
+
+ if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
+ uint64_t offset, vsid;
+
+ /* We only have 28 - 23 bits of offset in avpn */
+ offset = (avpn & 0x1f) << 23;
+ vsid = avpn >> 5;
+ /* We can find more bits from the pteg value */
+ if (base_pg_shift < 23) {
+ offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
+ }
+
+ hash = vsid ^ (offset >> base_pg_shift);
+ } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
+ uint64_t offset, vsid;
+
+ /* We only have 40 - 23 bits of seg_off in avpn */
+ offset = (avpn & 0x1ffff) << 23;
+ vsid = avpn >> 17;
+ if (base_pg_shift < 23) {
+ offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
+ << base_pg_shift;
+ }
+
+ hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
+ } else {
+ error_report("rehash_pte: Bad segment size in HPTE");
+ return H_HARDWARE;
+ }
+
+ new_pteg = hash & new_hash_mask;
+ if (pte0 & HPTE64_V_SECONDARY) {
+ assert(~pteg == (hash & old_hash_mask));
+ new_pteg = ~new_pteg;
+ } else {
+ assert(pteg == (hash & old_hash_mask));
+ }
+ assert((oldsize != newsize) || (pteg == new_pteg));
+ replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
+ /*
+ * Strictly speaking, we don't need all these tests, since we only
+ * ever rehash bolted HPTEs. We might in future handle non-bolted
+ * HPTEs, though so make the logic correct for those cases as
+ * well.
+ */
+ if (replace_pte0 & HPTE64_V_VALID) {
+ assert(newsize < oldsize);
+ if (replace_pte0 & HPTE64_V_BOLTED) {
+ if (pte0 & HPTE64_V_BOLTED) {
+ /* Bolted collision, nothing we can do */
+ return H_PTEG_FULL;
+ } else {
+ /* Discard this hpte */
+ return H_SUCCESS;
+ }
+ }
+ }
+
+ new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
+ return H_SUCCESS;
+}
+
+static int rehash_hpt(PowerPCCPU *cpu,
+ void *old_hpt, uint64_t oldsize,
+ void *new_hpt, uint64_t newsize)
+{
+ uint64_t n_ptegs = oldsize >> 7;
+ uint64_t pteg;
+ int slot;
+ int rc;
+
+ for (pteg = 0; pteg < n_ptegs; pteg++) {
+ hwaddr ptex = pteg * HPTES_PER_GROUP;
+ const ppc_hash_pte64_t *hptes
+ = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
+
+ if (!hptes) {
+ return H_HARDWARE;
+ }
+
+ for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
+ rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
+ pteg, slot);
+ if (rc != H_SUCCESS) {
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
+ return rc;
+ }
+ }
+ ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
+ }
+
+ return H_SUCCESS;
+}
+
+target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong flags,
+ target_ulong shift)
+{
+ SpaprPendingHpt *pending = spapr->pending_hpt;
+ int rc;
+ size_t newsize;
+
+ if (flags != 0) {
+ return H_PARAMETER;
+ }
+
+ if (!pending || (pending->shift != shift)) {
+ /* no matching prepare */
+ return H_CLOSED;
+ }
+
+ if (!pending->complete) {
+ /* prepare has not completed */
+ return H_BUSY;
+ }
+
+ /* Shouldn't have got past PREPARE without an HPT */
+ g_assert(spapr->htab_shift);
+
+ newsize = 1ULL << pending->shift;
+ rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
+ pending->hpt, newsize);
+ if (rc == H_SUCCESS) {
+ qemu_vfree(spapr->htab);
+ spapr->htab = pending->hpt;
+ spapr->htab_shift = pending->shift;
+
+ push_sregs_to_kvm_pr(spapr);
+
+ pending->hpt = NULL; /* so it's not free()d */
+ }
+
+ /* Clean up */
+ spapr->pending_hpt = NULL;
+ free_pending_hpt(pending);
+
+ return rc;
+}
+
+static void hypercall_register_types(void)
+{
+ /* hcall-pft */
+ spapr_register_hypercall(H_ENTER, h_enter);
+ spapr_register_hypercall(H_REMOVE, h_remove);
+ spapr_register_hypercall(H_PROTECT, h_protect);
+ spapr_register_hypercall(H_READ, h_read);
+
+ /* hcall-bulk */
+ spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
+
+}
+
+type_init(hypercall_register_types)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 7f40a158f4..d894a7a6b3 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -582,6 +582,12 @@ typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args);
+target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong shift);
+target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong flags, target_ulong shift);
+bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
+void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
/* Virtual Processor Area structure constants */
#define VPA_MIN_SIZE 640
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/4] target/ppc: moved function out of mmu-hash64
2021-05-06 16:39 [PATCH v3 0/4] hw/ppc: code motion to compile without TCG Lucas Mateus Castro (alqotel)
2021-05-06 16:39 ` [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu Lucas Mateus Castro (alqotel)
@ 2021-05-06 16:39 ` Lucas Mateus Castro (alqotel)
2021-05-07 3:13 ` David Gibson
2021-05-06 16:39 ` [PATCH v3 3/4] target/ppc: moved ppc_store_lpcr to misc_helper.c Lucas Mateus Castro (alqotel)
2021-05-06 16:39 ` [PATCH v3 4/4] hw/ppc: Altered calls from oea_read to read Lucas Mateus Castro (alqotel)
3 siblings, 1 reply; 9+ messages in thread
From: Lucas Mateus Castro (alqotel) @ 2021-05-06 16:39 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: bruno.larsen, Lucas Mateus Castro (alqotel), farosas, david
The function ppc_hash64_filter_pagesizes has been moved from a function
with prototype in mmu-hash64.h and implemented in mmu-hash64.c to
a static function in hw/ppc/spapr_caps.c as it's only used in that file.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
hw/ppc/spapr_caps.c | 59 +++++++++++++++++++++++++++++++++++++++++
target/ppc/mmu-hash64.c | 57 ---------------------------------------
target/ppc/mmu-hash64.h | 3 ---
3 files changed, 59 insertions(+), 60 deletions(-)
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 9ea7ddd1e9..d0c419b392 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -371,6 +371,65 @@ static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift,
return true;
}
+static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
+ bool (*cb)(void *, uint32_t, uint32_t),
+ void *opaque)
+{
+ PPCHash64Options *opts = cpu->hash64_opts;
+ int i;
+ int n = 0;
+ bool ci_largepage = false;
+
+ assert(opts);
+
+ n = 0;
+ for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
+ PPCHash64SegmentPageSizes *sps = &opts->sps[i];
+ int j;
+ int m = 0;
+
+ assert(n <= i);
+
+ if (!sps->page_shift) {
+ break;
+ }
+
+ for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
+ PPCHash64PageSize *ps = &sps->enc[j];
+
+ assert(m <= j);
+ if (!ps->page_shift) {
+ break;
+ }
+
+ if (cb(opaque, sps->page_shift, ps->page_shift)) {
+ if (ps->page_shift >= 16) {
+ ci_largepage = true;
+ }
+ sps->enc[m++] = *ps;
+ }
+ }
+
+ /* Clear rest of the row */
+ for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
+ memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
+ }
+
+ if (m) {
+ n++;
+ }
+ }
+
+ /* Clear the rest of the table */
+ for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
+ memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
+ }
+
+ if (!ci_largepage) {
+ opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
+ }
+}
+
static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr,
PowerPCCPU *cpu,
uint8_t val, Error **errp)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index d517a99832..be3596f27b 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1200,61 +1200,4 @@ const PPCHash64Options ppc_hash64_opts_POWER7 = {
}
};
-void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
- bool (*cb)(void *, uint32_t, uint32_t),
- void *opaque)
-{
- PPCHash64Options *opts = cpu->hash64_opts;
- int i;
- int n = 0;
- bool ci_largepage = false;
-
- assert(opts);
-
- n = 0;
- for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
- PPCHash64SegmentPageSizes *sps = &opts->sps[i];
- int j;
- int m = 0;
- assert(n <= i);
-
- if (!sps->page_shift) {
- break;
- }
-
- for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
- PPCHash64PageSize *ps = &sps->enc[j];
-
- assert(m <= j);
- if (!ps->page_shift) {
- break;
- }
-
- if (cb(opaque, sps->page_shift, ps->page_shift)) {
- if (ps->page_shift >= 16) {
- ci_largepage = true;
- }
- sps->enc[m++] = *ps;
- }
- }
-
- /* Clear rest of the row */
- for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
- memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
- }
-
- if (m) {
- n++;
- }
- }
-
- /* Clear the rest of the table */
- for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
- memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
- }
-
- if (!ci_largepage) {
- opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
- }
-}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 87729d48b3..5dfd7f8b93 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -18,9 +18,6 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
void ppc_hash64_init(PowerPCCPU *cpu);
void ppc_hash64_finalize(PowerPCCPU *cpu);
-void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
- bool (*cb)(void *, uint32_t, uint32_t),
- void *opaque);
#endif
/*
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/4] target/ppc: moved ppc_store_lpcr to misc_helper.c
2021-05-06 16:39 [PATCH v3 0/4] hw/ppc: code motion to compile without TCG Lucas Mateus Castro (alqotel)
2021-05-06 16:39 ` [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu Lucas Mateus Castro (alqotel)
2021-05-06 16:39 ` [PATCH v3 2/4] target/ppc: moved function out of mmu-hash64 Lucas Mateus Castro (alqotel)
@ 2021-05-06 16:39 ` Lucas Mateus Castro (alqotel)
2021-05-07 3:14 ` David Gibson
2021-05-06 16:39 ` [PATCH v3 4/4] hw/ppc: Altered calls from oea_read to read Lucas Mateus Castro (alqotel)
3 siblings, 1 reply; 9+ messages in thread
From: Lucas Mateus Castro (alqotel) @ 2021-05-06 16:39 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: bruno.larsen, Lucas Mateus Castro (alqotel), farosas, david
Moved the function ppc_store from mmu-hash64.c to misc_helper.c and the
prototype from mmu-hash64.h to cpu.h as it is a more appropriate place,
but it will have to have its implementation moved to a new file as
misc_helper.c should not be compiled in a !TCG environment.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
target/ppc/cpu.h | 1 +
target/ppc/misc_helper.c | 10 ++++++++++
target/ppc/mmu-hash64.c | 10 ----------
target/ppc/mmu-hash64.h | 1 -
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 733a2168c4..a976e7f7b0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1297,6 +1297,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr(CPUPPCState *env, target_ulong value);
+void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
void ppc_cpu_list(void);
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 002958be26..08a31da289 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -261,6 +261,16 @@ void ppc_store_msr(CPUPPCState *env, target_ulong value)
hreg_store_msr(env, value, 0);
}
+void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
+ /* The gtse bit affects hflags */
+ hreg_compute_hflags(env);
+}
+
/*
* This code is lifted from MacOnLinux. It is called whenever THRM1,2
* or 3 is read an fixes up the values in such a way that will make
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index be3596f27b..c4a4bc7cd2 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1120,16 +1120,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
}
-void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- CPUPPCState *env = &cpu->env;
-
- env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
- /* The gtse bit affects hflags */
- hreg_compute_hflags(env);
-}
-
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
{
PowerPCCPU *cpu = env_archcpu(env);
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 5dfd7f8b93..4b8b8e7950 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -15,7 +15,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
target_ulong pte0, target_ulong pte1);
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1);
-void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
void ppc_hash64_init(PowerPCCPU *cpu);
void ppc_hash64_finalize(PowerPCCPU *cpu);
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 4/4] hw/ppc: Altered calls from oea_read to read
2021-05-06 16:39 [PATCH v3 0/4] hw/ppc: code motion to compile without TCG Lucas Mateus Castro (alqotel)
` (2 preceding siblings ...)
2021-05-06 16:39 ` [PATCH v3 3/4] target/ppc: moved ppc_store_lpcr to misc_helper.c Lucas Mateus Castro (alqotel)
@ 2021-05-06 16:39 ` Lucas Mateus Castro (alqotel)
2021-05-07 3:17 ` David Gibson
3 siblings, 1 reply; 9+ messages in thread
From: Lucas Mateus Castro (alqotel) @ 2021-05-06 16:39 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: bruno.larsen, Lucas Mateus Castro (alqotel), farosas, david
Changed spapr.c and pnv.c from calls of ppc_spr_t.oea_read to
ppc_spr_t.name as oea_read is not available in !TCG builds.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 77af846cdf..06849b8802 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -199,7 +199,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
_FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
_FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
- if (env->spr_cb[SPR_PURR].oea_read) {
+ if (env->spr_cb[SPR_PURR].name) {
_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b37ceb8ee8..61653cbe2e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -705,10 +705,10 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
_FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
- if (env->spr_cb[SPR_PURR].oea_read) {
+ if (env->spr_cb[SPR_PURR].name) {
_FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
}
- if (env->spr_cb[SPR_SPURR].oea_read) {
+ if (env->spr_cb[SPR_SPURR].name) {
_FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
}
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu
2021-05-06 16:39 ` [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu Lucas Mateus Castro (alqotel)
@ 2021-05-07 3:12 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2021-05-07 3:12 UTC (permalink / raw)
To: Lucas Mateus Castro (alqotel); +Cc: bruno.larsen, qemu-ppc, qemu-devel, farosas
[-- Attachment #1: Type: text/plain, Size: 46056 bytes --]
On Thu, May 06, 2021 at 01:39:38PM -0300, Lucas Mateus Castro (alqotel) wrote:
> The hypercalls h_enter, h_remove, h_bulk_remove, h_protect, and h_read,
> have been moved to spapr_softmmu.c with the functions they depend on. The
> functions is_ram_address and push_sregs_to_kvm_pr are not static anymore
> as functions on both spapr_hcall.c and spapr_softmmu.c depend on them.
> The hypercalls h_resize_hpt_prepare and h_resize_hpt_commit have been
> divided, the KVM part stayed in spapr_hcall.c while the softmmu part
> was moved to spapr_softmmu.c
>
> Signed-off-by: Lucas Mateus Castro (alqotel)
> <lucas.araujo@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> hw/ppc/meson.build | 3 +
> hw/ppc/spapr_hcall.c | 608 +++------------------------------------
> hw/ppc/spapr_softmmu.c | 627 +++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/spapr.h | 6 +
> 4 files changed, 668 insertions(+), 576 deletions(-)
> create mode 100644 hw/ppc/spapr_softmmu.c
>
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index 86d6f379d1..597d974dd4 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -29,6 +29,9 @@ ppc_ss.add(when: 'CONFIG_PSERIES', if_true: files(
> 'spapr_numa.c',
> 'pef.c',
> ))
> +ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_TCG'], if_true: files(
> + 'spapr_softmmu.c',
> +))
> ppc_ss.add(when: 'CONFIG_SPAPR_RNG', if_true: files('spapr_rng.c'))
> ppc_ss.add(when: ['CONFIG_PSERIES', 'CONFIG_LINUX'], if_true: files(
> 'spapr_pci_vfio.c',
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 7275d0bba1..62dd015b70 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -27,18 +27,7 @@ static bool has_spr(PowerPCCPU *cpu, int spr)
> return cpu->env.spr_cb[spr].name != NULL;
> }
>
> -static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
> -{
> - /*
> - * hash value/pteg group index is normalized by HPT mask
> - */
> - if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
> - return false;
> - }
> - return true;
> -}
> -
> -static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
> +bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
> {
> MachineState *machine = MACHINE(spapr);
> DeviceMemoryState *dms = machine->device_memory;
> @@ -54,355 +43,6 @@ static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
> return false;
> }
>
> -static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - target_ulong flags = args[0];
> - target_ulong ptex = args[1];
> - target_ulong pteh = args[2];
> - target_ulong ptel = args[3];
> - unsigned apshift;
> - target_ulong raddr;
> - target_ulong slot;
> - const ppc_hash_pte64_t *hptes;
> -
> - apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
> - if (!apshift) {
> - /* Bad page size encoding */
> - return H_PARAMETER;
> - }
> -
> - raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
> -
> - if (is_ram_address(spapr, raddr)) {
> - /* Regular RAM - should have WIMG=0010 */
> - if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
> - return H_PARAMETER;
> - }
> - } else {
> - target_ulong wimg_flags;
> - /* Looks like an IO address */
> - /* FIXME: What WIMG combinations could be sensible for IO?
> - * For now we allow WIMG=010x, but are there others? */
> - /* FIXME: Should we check against registered IO addresses? */
> - wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
> -
> - if (wimg_flags != HPTE64_R_I &&
> - wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
> - return H_PARAMETER;
> - }
> - }
> -
> - pteh &= ~0x60ULL;
> -
> - if (!valid_ptex(cpu, ptex)) {
> - return H_PARAMETER;
> - }
> -
> - slot = ptex & 7ULL;
> - ptex = ptex & ~7ULL;
> -
> - if (likely((flags & H_EXACT) == 0)) {
> - hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
> - for (slot = 0; slot < 8; slot++) {
> - if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
> - break;
> - }
> - }
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
> - if (slot == 8) {
> - return H_PTEG_FULL;
> - }
> - } else {
> - hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
> - if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
> - return H_PTEG_FULL;
> - }
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
> - }
> -
> - spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
> -
> - args[0] = ptex + slot;
> - return H_SUCCESS;
> -}
> -
> -typedef enum {
> - REMOVE_SUCCESS = 0,
> - REMOVE_NOT_FOUND = 1,
> - REMOVE_PARM = 2,
> - REMOVE_HW = 3,
> -} RemoveResult;
> -
> -static RemoveResult remove_hpte(PowerPCCPU *cpu
> - , target_ulong ptex,
> - target_ulong avpn,
> - target_ulong flags,
> - target_ulong *vp, target_ulong *rp)
> -{
> - const ppc_hash_pte64_t *hptes;
> - target_ulong v, r;
> -
> - if (!valid_ptex(cpu, ptex)) {
> - return REMOVE_PARM;
> - }
> -
> - hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
> - v = ppc_hash64_hpte0(cpu, hptes, 0);
> - r = ppc_hash64_hpte1(cpu, hptes, 0);
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
> -
> - if ((v & HPTE64_V_VALID) == 0 ||
> - ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
> - ((flags & H_ANDCOND) && (v & avpn) != 0)) {
> - return REMOVE_NOT_FOUND;
> - }
> - *vp = v;
> - *rp = r;
> - spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
> - ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
> - return REMOVE_SUCCESS;
> -}
> -
> -static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUPPCState *env = &cpu->env;
> - target_ulong flags = args[0];
> - target_ulong ptex = args[1];
> - target_ulong avpn = args[2];
> - RemoveResult ret;
> -
> - ret = remove_hpte(cpu, ptex, avpn, flags,
> - &args[0], &args[1]);
> -
> - switch (ret) {
> - case REMOVE_SUCCESS:
> - check_tlb_flush(env, true);
> - return H_SUCCESS;
> -
> - case REMOVE_NOT_FOUND:
> - return H_NOT_FOUND;
> -
> - case REMOVE_PARM:
> - return H_PARAMETER;
> -
> - case REMOVE_HW:
> - return H_HARDWARE;
> - }
> -
> - g_assert_not_reached();
> -}
> -
> -#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
> -#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
> -#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
> -#define H_BULK_REMOVE_END 0xc000000000000000ULL
> -#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
> -#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
> -#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
> -#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
> -#define H_BULK_REMOVE_HW 0x3000000000000000ULL
> -#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
> -#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
> -#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
> -#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
> -#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
> -#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
> -
> -#define H_BULK_REMOVE_MAX_BATCH 4
> -
> -static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUPPCState *env = &cpu->env;
> - int i;
> - target_ulong rc = H_SUCCESS;
> -
> - for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
> - target_ulong *tsh = &args[i*2];
> - target_ulong tsl = args[i*2 + 1];
> - target_ulong v, r, ret;
> -
> - if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
> - break;
> - } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
> - return H_PARAMETER;
> - }
> -
> - *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
> - *tsh |= H_BULK_REMOVE_RESPONSE;
> -
> - if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
> - *tsh |= H_BULK_REMOVE_PARM;
> - return H_PARAMETER;
> - }
> -
> - ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
> - (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
> - &v, &r);
> -
> - *tsh |= ret << 60;
> -
> - switch (ret) {
> - case REMOVE_SUCCESS:
> - *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
> - break;
> -
> - case REMOVE_PARM:
> - rc = H_PARAMETER;
> - goto exit;
> -
> - case REMOVE_HW:
> - rc = H_HARDWARE;
> - goto exit;
> - }
> - }
> - exit:
> - check_tlb_flush(env, true);
> -
> - return rc;
> -}
> -
> -static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUPPCState *env = &cpu->env;
> - target_ulong flags = args[0];
> - target_ulong ptex = args[1];
> - target_ulong avpn = args[2];
> - const ppc_hash_pte64_t *hptes;
> - target_ulong v, r;
> -
> - if (!valid_ptex(cpu, ptex)) {
> - return H_PARAMETER;
> - }
> -
> - hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
> - v = ppc_hash64_hpte0(cpu, hptes, 0);
> - r = ppc_hash64_hpte1(cpu, hptes, 0);
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
> -
> - if ((v & HPTE64_V_VALID) == 0 ||
> - ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
> - return H_NOT_FOUND;
> - }
> -
> - r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
> - HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
> - r |= (flags << 55) & HPTE64_R_PP0;
> - r |= (flags << 48) & HPTE64_R_KEY_HI;
> - r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
> - spapr_store_hpte(cpu, ptex,
> - (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
> - ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
> - /* Flush the tlb */
> - check_tlb_flush(env, true);
> - /* Don't need a memory barrier, due to qemu's global lock */
> - spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
> - return H_SUCCESS;
> -}
> -
> -static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - target_ulong flags = args[0];
> - target_ulong ptex = args[1];
> - int i, ridx, n_entries = 1;
> - const ppc_hash_pte64_t *hptes;
> -
> - if (!valid_ptex(cpu, ptex)) {
> - return H_PARAMETER;
> - }
> -
> - if (flags & H_READ_4) {
> - /* Clear the two low order bits */
> - ptex &= ~(3ULL);
> - n_entries = 4;
> - }
> -
> - hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries);
> - for (i = 0, ridx = 0; i < n_entries; i++) {
> - args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i);
> - args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i);
> - }
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries);
> -
> - return H_SUCCESS;
> -}
> -
> -struct SpaprPendingHpt {
> - /* These fields are read-only after initialization */
> - int shift;
> - QemuThread thread;
> -
> - /* These fields are protected by the BQL */
> - bool complete;
> -
> - /* These fields are private to the preparation thread if
> - * !complete, otherwise protected by the BQL */
> - int ret;
> - void *hpt;
> -};
> -
> -static void free_pending_hpt(SpaprPendingHpt *pending)
> -{
> - if (pending->hpt) {
> - qemu_vfree(pending->hpt);
> - }
> -
> - g_free(pending);
> -}
> -
> -static void *hpt_prepare_thread(void *opaque)
> -{
> - SpaprPendingHpt *pending = opaque;
> - size_t size = 1ULL << pending->shift;
> -
> - pending->hpt = qemu_try_memalign(size, size);
> - if (pending->hpt) {
> - memset(pending->hpt, 0, size);
> - pending->ret = H_SUCCESS;
> - } else {
> - pending->ret = H_NO_MEM;
> - }
> -
> - qemu_mutex_lock_iothread();
> -
> - if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
> - /* Ready to go */
> - pending->complete = true;
> - } else {
> - /* We've been cancelled, clean ourselves up */
> - free_pending_hpt(pending);
> - }
> -
> - qemu_mutex_unlock_iothread();
> - return NULL;
> -}
> -
> -/* Must be called with BQL held */
> -static void cancel_hpt_prepare(SpaprMachineState *spapr)
> -{
> - SpaprPendingHpt *pending = spapr->pending_hpt;
> -
> - /* Let the thread know it's cancelled */
> - spapr->pending_hpt = NULL;
> -
> - if (!pending) {
> - /* Nothing to do */
> - return;
> - }
> -
> - if (!pending->complete) {
> - /* thread will clean itself up */
> - return;
> - }
> -
> - free_pending_hpt(pending);
> -}
> -
> /* Convert a return code from the KVM ioctl()s implementing resize HPT
> * into a PAPR hypercall return code */
> static target_ulong resize_hpt_convert_rc(int ret)
> @@ -448,7 +88,6 @@ static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
> {
> target_ulong flags = args[0];
> int shift = args[1];
> - SpaprPendingHpt *pending = spapr->pending_hpt;
> uint64_t current_ram_size;
> int rc;
>
> @@ -485,182 +124,11 @@ static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
> return resize_hpt_convert_rc(rc);
> }
>
> - if (pending) {
> - /* something already in progress */
> - if (pending->shift == shift) {
> - /* and it's suitable */
> - if (pending->complete) {
> - return pending->ret;
> - } else {
> - return H_LONG_BUSY_ORDER_100_MSEC;
> - }
> - }
> -
> - /* not suitable, cancel and replace */
> - cancel_hpt_prepare(spapr);
> - }
> -
> - if (!shift) {
> - /* nothing to do */
> - return H_SUCCESS;
> - }
> -
> - /* start new prepare */
> -
> - pending = g_new0(SpaprPendingHpt, 1);
> - pending->shift = shift;
> - pending->ret = H_HARDWARE;
> -
> - qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
> - hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
> -
> - spapr->pending_hpt = pending;
> -
> - /* In theory we could estimate the time more accurately based on
> - * the new size, but there's not much point */
> - return H_LONG_BUSY_ORDER_100_MSEC;
> -}
> -
> -static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
> -{
> - uint8_t *addr = htab;
> -
> - addr += pteg * HASH_PTEG_SIZE_64;
> - addr += slot * HASH_PTE_SIZE_64;
> - return ldq_p(addr);
> -}
> -
> -static void new_hpte_store(void *htab, uint64_t pteg, int slot,
> - uint64_t pte0, uint64_t pte1)
> -{
> - uint8_t *addr = htab;
> -
> - addr += pteg * HASH_PTEG_SIZE_64;
> - addr += slot * HASH_PTE_SIZE_64;
> -
> - stq_p(addr, pte0);
> - stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
> -}
> -
> -static int rehash_hpte(PowerPCCPU *cpu,
> - const ppc_hash_pte64_t *hptes,
> - void *old_hpt, uint64_t oldsize,
> - void *new_hpt, uint64_t newsize,
> - uint64_t pteg, int slot)
> -{
> - uint64_t old_hash_mask = (oldsize >> 7) - 1;
> - uint64_t new_hash_mask = (newsize >> 7) - 1;
> - target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
> - target_ulong pte1;
> - uint64_t avpn;
> - unsigned base_pg_shift;
> - uint64_t hash, new_pteg, replace_pte0;
> -
> - if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
> - return H_SUCCESS;
> - }
> -
> - pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
> -
> - base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
> - assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
> - avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
> -
> - if (pte0 & HPTE64_V_SECONDARY) {
> - pteg = ~pteg;
> - }
> -
> - if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
> - uint64_t offset, vsid;
> -
> - /* We only have 28 - 23 bits of offset in avpn */
> - offset = (avpn & 0x1f) << 23;
> - vsid = avpn >> 5;
> - /* We can find more bits from the pteg value */
> - if (base_pg_shift < 23) {
> - offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
> - }
> -
> - hash = vsid ^ (offset >> base_pg_shift);
> - } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
> - uint64_t offset, vsid;
> -
> - /* We only have 40 - 23 bits of seg_off in avpn */
> - offset = (avpn & 0x1ffff) << 23;
> - vsid = avpn >> 17;
> - if (base_pg_shift < 23) {
> - offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
> - << base_pg_shift;
> - }
> -
> - hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
> - } else {
> - error_report("rehash_pte: Bad segment size in HPTE");
> + if (kvm_enabled()) {
> return H_HARDWARE;
> }
>
> - new_pteg = hash & new_hash_mask;
> - if (pte0 & HPTE64_V_SECONDARY) {
> - assert(~pteg == (hash & old_hash_mask));
> - new_pteg = ~new_pteg;
> - } else {
> - assert(pteg == (hash & old_hash_mask));
> - }
> - assert((oldsize != newsize) || (pteg == new_pteg));
> - replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
> - /*
> - * Strictly speaking, we don't need all these tests, since we only
> - * ever rehash bolted HPTEs. We might in future handle non-bolted
> - * HPTEs, though so make the logic correct for those cases as
> - * well.
> - */
> - if (replace_pte0 & HPTE64_V_VALID) {
> - assert(newsize < oldsize);
> - if (replace_pte0 & HPTE64_V_BOLTED) {
> - if (pte0 & HPTE64_V_BOLTED) {
> - /* Bolted collision, nothing we can do */
> - return H_PTEG_FULL;
> - } else {
> - /* Discard this hpte */
> - return H_SUCCESS;
> - }
> - }
> - }
> -
> - new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
> - return H_SUCCESS;
> -}
> -
> -static int rehash_hpt(PowerPCCPU *cpu,
> - void *old_hpt, uint64_t oldsize,
> - void *new_hpt, uint64_t newsize)
> -{
> - uint64_t n_ptegs = oldsize >> 7;
> - uint64_t pteg;
> - int slot;
> - int rc;
> -
> - for (pteg = 0; pteg < n_ptegs; pteg++) {
> - hwaddr ptex = pteg * HPTES_PER_GROUP;
> - const ppc_hash_pte64_t *hptes
> - = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
> -
> - if (!hptes) {
> - return H_HARDWARE;
> - }
> -
> - for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
> - rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
> - pteg, slot);
> - if (rc != H_SUCCESS) {
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
> - return rc;
> - }
> - }
> - ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
> - }
> -
> - return H_SUCCESS;
> + return softmmu_resize_hpt_prepare(cpu, spapr, shift);
> }
>
> static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
> @@ -676,7 +144,7 @@ static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
> }
> }
>
> -static void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
> +void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
> {
> CPUState *cs;
>
> @@ -701,9 +169,7 @@ static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
> {
> target_ulong flags = args[0];
> target_ulong shift = args[1];
> - SpaprPendingHpt *pending = spapr->pending_hpt;
> int rc;
> - size_t newsize;
>
> if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
> return H_AUTHORITY;
> @@ -726,42 +192,14 @@ static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
> return rc;
> }
>
> - if (flags != 0) {
> - return H_PARAMETER;
> - }
> -
> - if (!pending || (pending->shift != shift)) {
> - /* no matching prepare */
> - return H_CLOSED;
> - }
> -
> - if (!pending->complete) {
> - /* prepare has not completed */
> - return H_BUSY;
> + if (kvm_enabled()) {
> + return H_HARDWARE;
> }
>
> - /* Shouldn't have got past PREPARE without an HPT */
> - g_assert(spapr->htab_shift);
> -
> - newsize = 1ULL << pending->shift;
> - rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
> - pending->hpt, newsize);
> - if (rc == H_SUCCESS) {
> - qemu_vfree(spapr->htab);
> - spapr->htab = pending->hpt;
> - spapr->htab_shift = pending->shift;
> -
> - push_sregs_to_kvm_pr(spapr);
> -
> - pending->hpt = NULL; /* so it's not free()d */
> - }
> + return softmmu_resize_hpt_commit(cpu, spapr, flags, shift);
> +}
>
> - /* Clean up */
> - spapr->pending_hpt = NULL;
> - free_pending_hpt(pending);
>
> - return rc;
> -}
>
> static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> @@ -2024,16 +1462,34 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
> return H_FUNCTION;
> }
>
> -static void hypercall_register_types(void)
> +#ifndef CONFIG_TCG
> +static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + g_assert_not_reached();
> +}
> +
> +static void hypercall_register_softmmu(void)
> {
> /* hcall-pft */
> - spapr_register_hypercall(H_ENTER, h_enter);
> - spapr_register_hypercall(H_REMOVE, h_remove);
> - spapr_register_hypercall(H_PROTECT, h_protect);
> - spapr_register_hypercall(H_READ, h_read);
> + spapr_register_hypercall(H_ENTER, h_softmmu);
> + spapr_register_hypercall(H_REMOVE, h_softmmu);
> + spapr_register_hypercall(H_PROTECT, h_softmmu);
> + spapr_register_hypercall(H_READ, h_softmmu);
>
> /* hcall-bulk */
> - spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
> + spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
> +}
> +#else
> +static void hypercall_register_softmmu(void)
> +{
> + /* DO NOTHING */
> +}
> +#endif
> +
> +static void hypercall_register_types(void)
> +{
> + hypercall_register_softmmu();
>
> /* hcall-hpt-resize */
> spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
> diff --git a/hw/ppc/spapr_softmmu.c b/hw/ppc/spapr_softmmu.c
> new file mode 100644
> index 0000000000..6c6b86dd3c
> --- /dev/null
> +++ b/hw/ppc/spapr_softmmu.c
> @@ -0,0 +1,627 @@
> +#include "qemu/osdep.h"
> +#include "qemu/cutils.h"
> +#include "qapi/error.h"
> +#include "sysemu/hw_accel.h"
> +#include "sysemu/runstate.h"
> +#include "qemu/log.h"
> +#include "qemu/main-loop.h"
> +#include "qemu/module.h"
> +#include "qemu/error-report.h"
> +#include "cpu.h"
> +#include "exec/exec-all.h"
> +#include "helper_regs.h"
> +#include "hw/ppc/spapr.h"
> +#include "hw/ppc/spapr_cpu_core.h"
> +#include "mmu-hash64.h"
> +#include "cpu-models.h"
> +#include "trace.h"
> +#include "kvm_ppc.h"
> +#include "hw/ppc/fdt.h"
> +#include "hw/ppc/spapr_ovec.h"
> +#include "mmu-book3s-v3.h"
> +#include "hw/mem/memory-device.h"
> +
> +static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
> +{
> + /*
> + * hash value/pteg group index is normalized by HPT mask
> + */
> + if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
> + return false;
> + }
> + return true;
> +}
> +
> +static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + target_ulong flags = args[0];
> + target_ulong ptex = args[1];
> + target_ulong pteh = args[2];
> + target_ulong ptel = args[3];
> + unsigned apshift;
> + target_ulong raddr;
> + target_ulong slot;
> + const ppc_hash_pte64_t *hptes;
> +
> + apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
> + if (!apshift) {
> + /* Bad page size encoding */
> + return H_PARAMETER;
> + }
> +
> + raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
> +
> + if (is_ram_address(spapr, raddr)) {
> + /* Regular RAM - should have WIMG=0010 */
> + if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
> + return H_PARAMETER;
> + }
> + } else {
> + target_ulong wimg_flags;
> + /* Looks like an IO address */
> + /* FIXME: What WIMG combinations could be sensible for IO?
> + * For now we allow WIMG=010x, but are there others? */
> + /* FIXME: Should we check against registered IO addresses? */
> + wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
> +
> + if (wimg_flags != HPTE64_R_I &&
> + wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
> + return H_PARAMETER;
> + }
> + }
> +
> + pteh &= ~0x60ULL;
> +
> + if (!valid_ptex(cpu, ptex)) {
> + return H_PARAMETER;
> + }
> +
> + slot = ptex & 7ULL;
> + ptex = ptex & ~7ULL;
> +
> + if (likely((flags & H_EXACT) == 0)) {
> + hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
> + for (slot = 0; slot < 8; slot++) {
> + if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
> + break;
> + }
> + }
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
> + if (slot == 8) {
> + return H_PTEG_FULL;
> + }
> + } else {
> + hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
> + if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
> + return H_PTEG_FULL;
> + }
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
> + }
> +
> + spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
> +
> + args[0] = ptex + slot;
> + return H_SUCCESS;
> +}
> +
> +typedef enum {
> + REMOVE_SUCCESS = 0,
> + REMOVE_NOT_FOUND = 1,
> + REMOVE_PARM = 2,
> + REMOVE_HW = 3,
> +} RemoveResult;
> +
> +static RemoveResult remove_hpte(PowerPCCPU *cpu
> + , target_ulong ptex,
> + target_ulong avpn,
> + target_ulong flags,
> + target_ulong *vp, target_ulong *rp)
> +{
> + const ppc_hash_pte64_t *hptes;
> + target_ulong v, r;
> +
> + if (!valid_ptex(cpu, ptex)) {
> + return REMOVE_PARM;
> + }
> +
> + hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
> + v = ppc_hash64_hpte0(cpu, hptes, 0);
> + r = ppc_hash64_hpte1(cpu, hptes, 0);
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
> +
> + if ((v & HPTE64_V_VALID) == 0 ||
> + ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
> + ((flags & H_ANDCOND) && (v & avpn) != 0)) {
> + return REMOVE_NOT_FOUND;
> + }
> + *vp = v;
> + *rp = r;
> + spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
> + ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
> + return REMOVE_SUCCESS;
> +}
> +
> +static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUPPCState *env = &cpu->env;
> + target_ulong flags = args[0];
> + target_ulong ptex = args[1];
> + target_ulong avpn = args[2];
> + RemoveResult ret;
> +
> + ret = remove_hpte(cpu, ptex, avpn, flags,
> + &args[0], &args[1]);
> +
> + switch (ret) {
> + case REMOVE_SUCCESS:
> + check_tlb_flush(env, true);
> + return H_SUCCESS;
> +
> + case REMOVE_NOT_FOUND:
> + return H_NOT_FOUND;
> +
> + case REMOVE_PARM:
> + return H_PARAMETER;
> +
> + case REMOVE_HW:
> + return H_HARDWARE;
> + }
> +
> + g_assert_not_reached();
> +}
> +
> +#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
> +#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
> +#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
> +#define H_BULK_REMOVE_END 0xc000000000000000ULL
> +#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
> +#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
> +#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
> +#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
> +#define H_BULK_REMOVE_HW 0x3000000000000000ULL
> +#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
> +#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
> +#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
> +#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
> +#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
> +#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
> +
> +#define H_BULK_REMOVE_MAX_BATCH 4
> +
> +static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUPPCState *env = &cpu->env;
> + int i;
> + target_ulong rc = H_SUCCESS;
> +
> + for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
> + target_ulong *tsh = &args[i*2];
> + target_ulong tsl = args[i*2 + 1];
> + target_ulong v, r, ret;
> +
> + if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
> + break;
> + } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
> + return H_PARAMETER;
> + }
> +
> + *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
> + *tsh |= H_BULK_REMOVE_RESPONSE;
> +
> + if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
> + *tsh |= H_BULK_REMOVE_PARM;
> + return H_PARAMETER;
> + }
> +
> + ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
> + (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
> + &v, &r);
> +
> + *tsh |= ret << 60;
> +
> + switch (ret) {
> + case REMOVE_SUCCESS:
> + *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
> + break;
> +
> + case REMOVE_PARM:
> + rc = H_PARAMETER;
> + goto exit;
> +
> + case REMOVE_HW:
> + rc = H_HARDWARE;
> + goto exit;
> + }
> + }
> + exit:
> + check_tlb_flush(env, true);
> +
> + return rc;
> +}
> +
> +static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUPPCState *env = &cpu->env;
> + target_ulong flags = args[0];
> + target_ulong ptex = args[1];
> + target_ulong avpn = args[2];
> + const ppc_hash_pte64_t *hptes;
> + target_ulong v, r;
> +
> + if (!valid_ptex(cpu, ptex)) {
> + return H_PARAMETER;
> + }
> +
> + hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
> + v = ppc_hash64_hpte0(cpu, hptes, 0);
> + r = ppc_hash64_hpte1(cpu, hptes, 0);
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
> +
> + if ((v & HPTE64_V_VALID) == 0 ||
> + ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
> + return H_NOT_FOUND;
> + }
> +
> + r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
> + HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
> + r |= (flags << 55) & HPTE64_R_PP0;
> + r |= (flags << 48) & HPTE64_R_KEY_HI;
> + r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
> + spapr_store_hpte(cpu, ptex,
> + (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
> + ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
> + /* Flush the tlb */
> + check_tlb_flush(env, true);
> + /* Don't need a memory barrier, due to qemu's global lock */
> + spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
> + return H_SUCCESS;
> +}
> +
> +static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + target_ulong flags = args[0];
> + target_ulong ptex = args[1];
> + int i, ridx, n_entries = 1;
> + const ppc_hash_pte64_t *hptes;
> +
> + if (!valid_ptex(cpu, ptex)) {
> + return H_PARAMETER;
> + }
> +
> + if (flags & H_READ_4) {
> + /* Clear the two low order bits */
> + ptex &= ~(3ULL);
> + n_entries = 4;
> + }
> +
> + hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries);
> + for (i = 0, ridx = 0; i < n_entries; i++) {
> + args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i);
> + args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i);
> + }
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries);
> +
> + return H_SUCCESS;
> +}
> +
> +struct SpaprPendingHpt {
> + /* These fields are read-only after initialization */
> + int shift;
> + QemuThread thread;
> +
> + /* These fields are protected by the BQL */
> + bool complete;
> +
> + /* These fields are private to the preparation thread if
> + * !complete, otherwise protected by the BQL */
> + int ret;
> + void *hpt;
> +};
> +
> +static void free_pending_hpt(SpaprPendingHpt *pending)
> +{
> + if (pending->hpt) {
> + qemu_vfree(pending->hpt);
> + }
> +
> + g_free(pending);
> +}
> +
> +static void *hpt_prepare_thread(void *opaque)
> +{
> + SpaprPendingHpt *pending = opaque;
> + size_t size = 1ULL << pending->shift;
> +
> + pending->hpt = qemu_try_memalign(size, size);
> + if (pending->hpt) {
> + memset(pending->hpt, 0, size);
> + pending->ret = H_SUCCESS;
> + } else {
> + pending->ret = H_NO_MEM;
> + }
> +
> + qemu_mutex_lock_iothread();
> +
> + if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
> + /* Ready to go */
> + pending->complete = true;
> + } else {
> + /* We've been cancelled, clean ourselves up */
> + free_pending_hpt(pending);
> + }
> +
> + qemu_mutex_unlock_iothread();
> + return NULL;
> +}
> +
> +/* Must be called with BQL held */
> +static void cancel_hpt_prepare(SpaprMachineState *spapr)
> +{
> + SpaprPendingHpt *pending = spapr->pending_hpt;
> +
> + /* Let the thread know it's cancelled */
> + spapr->pending_hpt = NULL;
> +
> + if (!pending) {
> + /* Nothing to do */
> + return;
> + }
> +
> + if (!pending->complete) {
> + /* thread will clean itself up */
> + return;
> + }
> +
> + free_pending_hpt(pending);
> +}
> +
> +target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu,
> + SpaprMachineState *spapr,
> + target_ulong shift)
> +{
> + SpaprPendingHpt *pending = spapr->pending_hpt;
> +
> + if (pending) {
> + /* something already in progress */
> + if (pending->shift == shift) {
> + /* and it's suitable */
> + if (pending->complete) {
> + return pending->ret;
> + } else {
> + return H_LONG_BUSY_ORDER_100_MSEC;
> + }
> + }
> +
> + /* not suitable, cancel and replace */
> + cancel_hpt_prepare(spapr);
> + }
> +
> + if (!shift) {
> + /* nothing to do */
> + return H_SUCCESS;
> + }
> +
> + /* start new prepare */
> +
> + pending = g_new0(SpaprPendingHpt, 1);
> + pending->shift = shift;
> + pending->ret = H_HARDWARE;
> +
> + qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
> + hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
> +
> + spapr->pending_hpt = pending;
> +
> + /* In theory we could estimate the time more accurately based on
> + * the new size, but there's not much point */
> + return H_LONG_BUSY_ORDER_100_MSEC;
> +}
> +
> +static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
> +{
> + uint8_t *addr = htab;
> +
> + addr += pteg * HASH_PTEG_SIZE_64;
> + addr += slot * HASH_PTE_SIZE_64;
> + return ldq_p(addr);
> +}
> +
> +static void new_hpte_store(void *htab, uint64_t pteg, int slot,
> + uint64_t pte0, uint64_t pte1)
> +{
> + uint8_t *addr = htab;
> +
> + addr += pteg * HASH_PTEG_SIZE_64;
> + addr += slot * HASH_PTE_SIZE_64;
> +
> + stq_p(addr, pte0);
> + stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
> +}
> +
> +static int rehash_hpte(PowerPCCPU *cpu,
> + const ppc_hash_pte64_t *hptes,
> + void *old_hpt, uint64_t oldsize,
> + void *new_hpt, uint64_t newsize,
> + uint64_t pteg, int slot)
> +{
> + uint64_t old_hash_mask = (oldsize >> 7) - 1;
> + uint64_t new_hash_mask = (newsize >> 7) - 1;
> + target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
> + target_ulong pte1;
> + uint64_t avpn;
> + unsigned base_pg_shift;
> + uint64_t hash, new_pteg, replace_pte0;
> +
> + if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
> + return H_SUCCESS;
> + }
> +
> + pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
> +
> + base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
> + assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
> + avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
> +
> + if (pte0 & HPTE64_V_SECONDARY) {
> + pteg = ~pteg;
> + }
> +
> + if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
> + uint64_t offset, vsid;
> +
> + /* We only have 28 - 23 bits of offset in avpn */
> + offset = (avpn & 0x1f) << 23;
> + vsid = avpn >> 5;
> + /* We can find more bits from the pteg value */
> + if (base_pg_shift < 23) {
> + offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
> + }
> +
> + hash = vsid ^ (offset >> base_pg_shift);
> + } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
> + uint64_t offset, vsid;
> +
> + /* We only have 40 - 23 bits of seg_off in avpn */
> + offset = (avpn & 0x1ffff) << 23;
> + vsid = avpn >> 17;
> + if (base_pg_shift < 23) {
> + offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
> + << base_pg_shift;
> + }
> +
> + hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
> + } else {
> + error_report("rehash_pte: Bad segment size in HPTE");
> + return H_HARDWARE;
> + }
> +
> + new_pteg = hash & new_hash_mask;
> + if (pte0 & HPTE64_V_SECONDARY) {
> + assert(~pteg == (hash & old_hash_mask));
> + new_pteg = ~new_pteg;
> + } else {
> + assert(pteg == (hash & old_hash_mask));
> + }
> + assert((oldsize != newsize) || (pteg == new_pteg));
> + replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
> + /*
> + * Strictly speaking, we don't need all these tests, since we only
> + * ever rehash bolted HPTEs. We might in future handle non-bolted
> + * HPTEs, though so make the logic correct for those cases as
> + * well.
> + */
> + if (replace_pte0 & HPTE64_V_VALID) {
> + assert(newsize < oldsize);
> + if (replace_pte0 & HPTE64_V_BOLTED) {
> + if (pte0 & HPTE64_V_BOLTED) {
> + /* Bolted collision, nothing we can do */
> + return H_PTEG_FULL;
> + } else {
> + /* Discard this hpte */
> + return H_SUCCESS;
> + }
> + }
> + }
> +
> + new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
> + return H_SUCCESS;
> +}
> +
> +static int rehash_hpt(PowerPCCPU *cpu,
> + void *old_hpt, uint64_t oldsize,
> + void *new_hpt, uint64_t newsize)
> +{
> + uint64_t n_ptegs = oldsize >> 7;
> + uint64_t pteg;
> + int slot;
> + int rc;
> +
> + for (pteg = 0; pteg < n_ptegs; pteg++) {
> + hwaddr ptex = pteg * HPTES_PER_GROUP;
> + const ppc_hash_pte64_t *hptes
> + = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
> +
> + if (!hptes) {
> + return H_HARDWARE;
> + }
> +
> + for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
> + rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
> + pteg, slot);
> + if (rc != H_SUCCESS) {
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
> + return rc;
> + }
> + }
> + ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
> + }
> +
> + return H_SUCCESS;
> +}
> +
> +target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu,
> + SpaprMachineState *spapr,
> + target_ulong flags,
> + target_ulong shift)
> +{
> + SpaprPendingHpt *pending = spapr->pending_hpt;
> + int rc;
> + size_t newsize;
> +
> + if (flags != 0) {
> + return H_PARAMETER;
> + }
> +
> + if (!pending || (pending->shift != shift)) {
> + /* no matching prepare */
> + return H_CLOSED;
> + }
> +
> + if (!pending->complete) {
> + /* prepare has not completed */
> + return H_BUSY;
> + }
> +
> + /* Shouldn't have got past PREPARE without an HPT */
> + g_assert(spapr->htab_shift);
> +
> + newsize = 1ULL << pending->shift;
> + rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
> + pending->hpt, newsize);
> + if (rc == H_SUCCESS) {
> + qemu_vfree(spapr->htab);
> + spapr->htab = pending->hpt;
> + spapr->htab_shift = pending->shift;
> +
> + push_sregs_to_kvm_pr(spapr);
> +
> + pending->hpt = NULL; /* so it's not free()d */
> + }
> +
> + /* Clean up */
> + spapr->pending_hpt = NULL;
> + free_pending_hpt(pending);
> +
> + return rc;
> +}
> +
> +static void hypercall_register_types(void)
> +{
> + /* hcall-pft */
> + spapr_register_hypercall(H_ENTER, h_enter);
> + spapr_register_hypercall(H_REMOVE, h_remove);
> + spapr_register_hypercall(H_PROTECT, h_protect);
> + spapr_register_hypercall(H_READ, h_read);
> +
> + /* hcall-bulk */
> + spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
> +
> +}
> +
> +type_init(hypercall_register_types)
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 7f40a158f4..d894a7a6b3 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -582,6 +582,12 @@ typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
> void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
> target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
> target_ulong *args);
> +target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong shift);
> +target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
> + target_ulong flags, target_ulong shift);
> +bool is_ram_address(SpaprMachineState *spapr, hwaddr addr);
> +void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
>
> /* Virtual Processor Area structure constants */
> #define VPA_MIN_SIZE 640
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/4] target/ppc: moved function out of mmu-hash64
2021-05-06 16:39 ` [PATCH v3 2/4] target/ppc: moved function out of mmu-hash64 Lucas Mateus Castro (alqotel)
@ 2021-05-07 3:13 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2021-05-07 3:13 UTC (permalink / raw)
To: Lucas Mateus Castro (alqotel); +Cc: bruno.larsen, qemu-ppc, qemu-devel, farosas
[-- Attachment #1: Type: text/plain, Size: 5526 bytes --]
On Thu, May 06, 2021 at 01:39:39PM -0300, Lucas Mateus Castro (alqotel) wrote:
> The function ppc_hash64_filter_pagesizes has been moved from a function
> with prototype in mmu-hash64.h and implemented in mmu-hash64.c to
> a static function in hw/ppc/spapr_caps.c as it's only used in that file.
>
> Signed-off-by: Lucas Mateus Castro (alqotel)
> <lucas.araujo@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> hw/ppc/spapr_caps.c | 59 +++++++++++++++++++++++++++++++++++++++++
> target/ppc/mmu-hash64.c | 57 ---------------------------------------
> target/ppc/mmu-hash64.h | 3 ---
> 3 files changed, 59 insertions(+), 60 deletions(-)
>
> diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
> index 9ea7ddd1e9..d0c419b392 100644
> --- a/hw/ppc/spapr_caps.c
> +++ b/hw/ppc/spapr_caps.c
> @@ -371,6 +371,65 @@ static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift,
> return true;
> }
>
> +static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
> + bool (*cb)(void *, uint32_t, uint32_t),
> + void *opaque)
> +{
> + PPCHash64Options *opts = cpu->hash64_opts;
> + int i;
> + int n = 0;
> + bool ci_largepage = false;
> +
> + assert(opts);
> +
> + n = 0;
> + for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
> + PPCHash64SegmentPageSizes *sps = &opts->sps[i];
> + int j;
> + int m = 0;
> +
> + assert(n <= i);
> +
> + if (!sps->page_shift) {
> + break;
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
> + PPCHash64PageSize *ps = &sps->enc[j];
> +
> + assert(m <= j);
> + if (!ps->page_shift) {
> + break;
> + }
> +
> + if (cb(opaque, sps->page_shift, ps->page_shift)) {
> + if (ps->page_shift >= 16) {
> + ci_largepage = true;
> + }
> + sps->enc[m++] = *ps;
> + }
> + }
> +
> + /* Clear rest of the row */
> + for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
> + memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
> + }
> +
> + if (m) {
> + n++;
> + }
> + }
> +
> + /* Clear the rest of the table */
> + for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
> + memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
> + }
> +
> + if (!ci_largepage) {
> + opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
> + }
> +}
> +
> static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr,
> PowerPCCPU *cpu,
> uint8_t val, Error **errp)
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index d517a99832..be3596f27b 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1200,61 +1200,4 @@ const PPCHash64Options ppc_hash64_opts_POWER7 = {
> }
> };
>
> -void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
> - bool (*cb)(void *, uint32_t, uint32_t),
> - void *opaque)
> -{
> - PPCHash64Options *opts = cpu->hash64_opts;
> - int i;
> - int n = 0;
> - bool ci_largepage = false;
> -
> - assert(opts);
> -
> - n = 0;
> - for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
> - PPCHash64SegmentPageSizes *sps = &opts->sps[i];
> - int j;
> - int m = 0;
>
> - assert(n <= i);
> -
> - if (!sps->page_shift) {
> - break;
> - }
> -
> - for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
> - PPCHash64PageSize *ps = &sps->enc[j];
> -
> - assert(m <= j);
> - if (!ps->page_shift) {
> - break;
> - }
> -
> - if (cb(opaque, sps->page_shift, ps->page_shift)) {
> - if (ps->page_shift >= 16) {
> - ci_largepage = true;
> - }
> - sps->enc[m++] = *ps;
> - }
> - }
> -
> - /* Clear rest of the row */
> - for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
> - memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
> - }
> -
> - if (m) {
> - n++;
> - }
> - }
> -
> - /* Clear the rest of the table */
> - for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
> - memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
> - }
> -
> - if (!ci_largepage) {
> - opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
> - }
> -}
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 87729d48b3..5dfd7f8b93 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -18,9 +18,6 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
> void ppc_hash64_init(PowerPCCPU *cpu);
> void ppc_hash64_finalize(PowerPCCPU *cpu);
> -void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
> - bool (*cb)(void *, uint32_t, uint32_t),
> - void *opaque);
> #endif
>
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/4] target/ppc: moved ppc_store_lpcr to misc_helper.c
2021-05-06 16:39 ` [PATCH v3 3/4] target/ppc: moved ppc_store_lpcr to misc_helper.c Lucas Mateus Castro (alqotel)
@ 2021-05-07 3:14 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2021-05-07 3:14 UTC (permalink / raw)
To: Lucas Mateus Castro (alqotel); +Cc: bruno.larsen, qemu-ppc, qemu-devel, farosas
[-- Attachment #1: Type: text/plain, Size: 3557 bytes --]
On Thu, May 06, 2021 at 01:39:40PM -0300, Lucas Mateus Castro (alqotel) wrote:
> Moved the function ppc_store from mmu-hash64.c to misc_helper.c and the
> prototype from mmu-hash64.h to cpu.h as it is a more appropriate place,
> but it will have to have its implementation moved to a new file as
> misc_helper.c should not be compiled in a !TCG environment.
>
> Signed-off-by: Lucas Mateus Castro (alqotel)
> <lucas.araujo@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/cpu.h | 1 +
> target/ppc/misc_helper.c | 10 ++++++++++
> target/ppc/mmu-hash64.c | 10 ----------
> target/ppc/mmu-hash64.h | 1 -
> 4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 733a2168c4..a976e7f7b0 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1297,6 +1297,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
> void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
> #endif /* !defined(CONFIG_USER_ONLY) */
> void ppc_store_msr(CPUPPCState *env, target_ulong value);
> +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
>
> void ppc_cpu_list(void);
>
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 002958be26..08a31da289 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -261,6 +261,16 @@ void ppc_store_msr(CPUPPCState *env, target_ulong value)
> hreg_store_msr(env, value, 0);
> }
>
> +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> +{
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> + CPUPPCState *env = &cpu->env;
> +
> + env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> + /* The gtse bit affects hflags */
> + hreg_compute_hflags(env);
> +}
> +
> /*
> * This code is lifted from MacOnLinux. It is called whenever THRM1,2
> * or 3 is read an fixes up the values in such a way that will make
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index be3596f27b..c4a4bc7cd2 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1120,16 +1120,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
> cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
> }
>
> -void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> -{
> - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> - CPUPPCState *env = &cpu->env;
> -
> - env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> - /* The gtse bit affects hflags */
> - hreg_compute_hflags(env);
> -}
> -
> void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> {
> PowerPCCPU *cpu = env_archcpu(env);
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 5dfd7f8b93..4b8b8e7950 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -15,7 +15,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
> target_ulong pte0, target_ulong pte1);
> unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> uint64_t pte0, uint64_t pte1);
> -void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
> void ppc_hash64_init(PowerPCCPU *cpu);
> void ppc_hash64_finalize(PowerPCCPU *cpu);
> #endif
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 4/4] hw/ppc: Altered calls from oea_read to read
2021-05-06 16:39 ` [PATCH v3 4/4] hw/ppc: Altered calls from oea_read to read Lucas Mateus Castro (alqotel)
@ 2021-05-07 3:17 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2021-05-07 3:17 UTC (permalink / raw)
To: Lucas Mateus Castro (alqotel); +Cc: bruno.larsen, qemu-ppc, qemu-devel, farosas
[-- Attachment #1: Type: text/plain, Size: 2195 bytes --]
On Thu, May 06, 2021 at 01:39:41PM -0300, Lucas Mateus Castro (alqotel) wrote:
> Changed spapr.c and pnv.c from calls of ppc_spr_t.oea_read to
> ppc_spr_t.name as oea_read is not available in !TCG builds.
This is correct, but I think we can do it a little more cleanly. This
logic is identical to has_spr() in spapr_hcall.c.
Can you move has_spr() to the target/ppc logic instead and rename it
to, say, ppc_has_spr(). It's simple enough that it could just go
inline in target/ppc/cpu.h. Then we can use that in these places as
well as the places its used in spapr_hcall.c.
>
> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
> ---
> hw/ppc/pnv.c | 2 +-
> hw/ppc/spapr.c | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 77af846cdf..06849b8802 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -199,7 +199,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
> _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
> _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
>
> - if (env->spr_cb[SPR_PURR].oea_read) {
> + if (env->spr_cb[SPR_PURR].name) {
> _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
> }
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index b37ceb8ee8..61653cbe2e 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -705,10 +705,10 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
> _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
> _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
>
> - if (env->spr_cb[SPR_PURR].oea_read) {
> + if (env->spr_cb[SPR_PURR].name) {
> _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
> }
> - if (env->spr_cb[SPR_SPURR].oea_read) {
> + if (env->spr_cb[SPR_SPURR].name) {
> _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-05-07 3:22 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-06 16:39 [PATCH v3 0/4] hw/ppc: code motion to compile without TCG Lucas Mateus Castro (alqotel)
2021-05-06 16:39 ` [PATCH v3 1/4] hw/ppc: moved hcalls that depend on softmmu Lucas Mateus Castro (alqotel)
2021-05-07 3:12 ` David Gibson
2021-05-06 16:39 ` [PATCH v3 2/4] target/ppc: moved function out of mmu-hash64 Lucas Mateus Castro (alqotel)
2021-05-07 3:13 ` David Gibson
2021-05-06 16:39 ` [PATCH v3 3/4] target/ppc: moved ppc_store_lpcr to misc_helper.c Lucas Mateus Castro (alqotel)
2021-05-07 3:14 ` David Gibson
2021-05-06 16:39 ` [PATCH v3 4/4] hw/ppc: Altered calls from oea_read to read Lucas Mateus Castro (alqotel)
2021-05-07 3:17 ` David Gibson
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