* [PULL 01/31] exec/memory_ldst_cached: Sort declarations
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 02/31] exec/memory_ldst_phys: " Richard Henderson
` (30 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
To ease the file review, sort the declarations by the size of
the access (8, 16, 32). Simple code movement, no logical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-2-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory_ldst_cached.h.inc | 46 +++++++++++++--------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/include/exec/memory_ldst_cached.h.inc b/include/exec/memory_ldst_cached.h.inc
index 7bc8790d34..c33449d0cd 100644
--- a/include/exec/memory_ldst_cached.h.inc
+++ b/include/exec/memory_ldst_cached.h.inc
@@ -24,6 +24,18 @@
#define LD_P(size) \
glue(glue(ld, size), glue(ENDIANNESS, _p))
+static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
+ hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
+{
+ assert(addr < cache->len && 2 <= cache->len - addr);
+ fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
+ if (likely(cache->ptr)) {
+ return LD_P(uw)(cache->ptr + addr);
+ } else {
+ return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
+ }
+}
+
static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
@@ -48,18 +60,6 @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
}
}
-static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
- hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
-{
- assert(addr < cache->len && 2 <= cache->len - addr);
- fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
- if (likely(cache->ptr)) {
- return LD_P(uw)(cache->ptr + addr);
- } else {
- return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
- }
-}
-
#undef ADDRESS_SPACE_LD_CACHED
#undef ADDRESS_SPACE_LD_CACHED_SLOW
#undef LD_P
@@ -71,17 +71,6 @@ static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
#define ST_P(size) \
glue(glue(st, size), glue(ENDIANNESS, _p))
-static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
-{
- assert(addr < cache->len && 4 <= cache->len - addr);
- if (likely(cache->ptr)) {
- ST_P(l)(cache->ptr + addr, val);
- } else {
- ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result);
- }
-}
-
static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
{
@@ -93,6 +82,17 @@ static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
}
}
+static inline void ADDRESS_SPACE_ST_CACHED(l)(MemoryRegionCache *cache,
+ hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+{
+ assert(addr < cache->len && 4 <= cache->len - addr);
+ if (likely(cache->ptr)) {
+ ST_P(l)(cache->ptr + addr, val);
+ } else {
+ ADDRESS_SPACE_ST_CACHED_SLOW(l)(cache, addr, val, attrs, result);
+ }
+}
+
static inline void ADDRESS_SPACE_ST_CACHED(q)(MemoryRegionCache *cache,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 02/31] exec/memory_ldst_phys: Sort declarations
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
2021-05-26 23:46 ` [PULL 01/31] exec/memory_ldst_cached: Sort declarations Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 03/31] exec/memory_ldst: Use correct type sizes Richard Henderson
` (29 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
To ease the file review, sort the declarations by the size of
the access (8, 16, 32). Simple code movement, no logical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-3-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory_ldst_phys.h.inc | 78 ++++++++++++++---------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc
index b9dd53c389..4033795add 100644
--- a/include/exec/memory_ldst_phys.h.inc
+++ b/include/exec/memory_ldst_phys.h.inc
@@ -20,6 +20,12 @@
*/
#ifdef TARGET_ENDIANNESS
+static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_lduw, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
static inline uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldl, SUFFIX)(ARG1, addr,
@@ -32,10 +38,10 @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
- return glue(address_space_lduw, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ glue(address_space_stw, SUFFIX)(ARG1, addr, val,
+ MEMTXATTRS_UNSPECIFIED, NULL);
}
static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
@@ -44,18 +50,30 @@ static inline void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
-{
- glue(address_space_stw, SUFFIX)(ARG1, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
{
glue(address_space_stq, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
#else
+static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_ldub, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
+static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
+static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+{
+ return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldl_le, SUFFIX)(ARG1, addr,
@@ -80,36 +98,6 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
-{
- return glue(address_space_ldub, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
-{
- return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
-{
- return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
-{
- glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
-static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
-{
- glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
-}
-
static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
{
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
@@ -128,6 +116,18 @@ static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t va
MEMTXATTRS_UNSPECIFIED, NULL);
}
+static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+{
+ glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
+static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+{
+ glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+}
+
static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
{
glue(address_space_stq_le, SUFFIX)(ARG1, addr, val,
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 03/31] exec/memory_ldst: Use correct type sizes
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
2021-05-26 23:46 ` [PULL 01/31] exec/memory_ldst_cached: Sort declarations Richard Henderson
2021-05-26 23:46 ` [PULL 02/31] exec/memory_ldst_phys: " Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 04/31] exec/memory_ldst_phys: " Richard Henderson
` (28 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
16-bit word.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-4-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory_ldst.h.inc | 16 ++++++++--------
memory_ldst.c.inc | 20 ++++++++++----------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc
index 46e6c220d3..7c3a641f7e 100644
--- a/include/exec/memory_ldst.h.inc
+++ b/include/exec/memory_ldst.h.inc
@@ -20,7 +20,7 @@
*/
#ifdef TARGET_ENDIANNESS
-extern uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
+extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
@@ -29,17 +29,17 @@ extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stq, SUFFIX)(ARG1_DECL,
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result);
#else
-extern uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
+extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
-extern uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
+extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
-extern uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
+extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
@@ -50,11 +50,11 @@ extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stb, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
+ hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result);
extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
diff --git a/memory_ldst.c.inc b/memory_ldst.c.inc
index b56e961967..84b868f294 100644
--- a/memory_ldst.c.inc
+++ b/memory_ldst.c.inc
@@ -157,7 +157,7 @@ uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
DEVICE_BIG_ENDIAN);
}
-uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
+uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
uint8_t *ptr;
@@ -193,7 +193,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
}
/* warning: addr must be aligned */
-static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
+static inline uint16_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
enum device_endian endian)
{
@@ -240,21 +240,21 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
return val;
}
-uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
+uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
-uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
+uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
-uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
+uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
@@ -366,7 +366,7 @@ void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
}
void glue(address_space_stb, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+ hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)
{
uint8_t *ptr;
MemoryRegion *mr;
@@ -398,7 +398,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
/* warning: addr must be aligned */
static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs,
+ hwaddr addr, uint16_t val, MemTxAttrs attrs,
MemTxResult *result, enum device_endian endian)
{
uint8_t *ptr;
@@ -441,21 +441,21 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
}
void glue(address_space_stw, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
{
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
DEVICE_NATIVE_ENDIAN);
}
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
{
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
DEVICE_LITTLE_ENDIAN);
}
void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
{
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
DEVICE_BIG_ENDIAN);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 04/31] exec/memory_ldst_phys: Use correct type sizes
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2021-05-26 23:46 ` [PULL 03/31] exec/memory_ldst: Use correct type sizes Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 05/31] exec/memory_ldst_cached: Use correct type size Richard Henderson
` (27 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
16-bit word.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-5-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory_ldst_phys.h.inc | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc
index 4033795add..ecd678610d 100644
--- a/include/exec/memory_ldst_phys.h.inc
+++ b/include/exec/memory_ldst_phys.h.inc
@@ -20,7 +20,7 @@
*/
#ifdef TARGET_ENDIANNESS
-static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint16_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_lduw, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
@@ -38,7 +38,7 @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
{
glue(address_space_stw, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
@@ -56,19 +56,19 @@ static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
MEMTXATTRS_UNSPECIFIED, NULL);
}
#else
-static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint8_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_ldub, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint16_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
{
return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
MEMTXATTRS_UNSPECIFIED, NULL);
@@ -98,19 +98,19 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val)
{
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
{
glue(address_space_stw_le, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
}
-static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
{
glue(address_space_stw_be, SUFFIX)(ARG1, addr, val,
MEMTXATTRS_UNSPECIFIED, NULL);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 05/31] exec/memory_ldst_cached: Use correct type size
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2021-05-26 23:46 ` [PULL 04/31] exec/memory_ldst_phys: " Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 06/31] exec/memory: " Richard Henderson
` (26 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use uint16_t for (unsigned) 16-bit word.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-6-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory_ldst_cached.h.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/memory_ldst_cached.h.inc b/include/exec/memory_ldst_cached.h.inc
index c33449d0cd..d7834f852c 100644
--- a/include/exec/memory_ldst_cached.h.inc
+++ b/include/exec/memory_ldst_cached.h.inc
@@ -24,7 +24,7 @@
#define LD_P(size) \
glue(glue(ld, size), glue(ENDIANNESS, _p))
-static inline uint32_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
+static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
@@ -72,7 +72,7 @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(MemoryRegionCache *cache,
glue(glue(st, size), glue(ENDIANNESS, _p))
static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+ hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len && 2 <= cache->len - addr);
if (likely(cache->ptr)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 06/31] exec/memory: Use correct type size
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2021-05-26 23:46 ` [PULL 05/31] exec/memory_ldst_cached: Use correct type size Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion Richard Henderson
` (25 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Use uint8_t for (unsigned) byte.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-7-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memory.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index c8b9088924..175d7151a5 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -2305,7 +2305,7 @@ static inline uint8_t address_space_ldub_cached(MemoryRegionCache *cache,
}
static inline void address_space_stb_cached(MemoryRegionCache *cache,
- hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
+ hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)
{
assert(addr < cache->len);
if (likely(cache->ptr)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2021-05-26 23:46 ` [PULL 06/31] exec/memory: " Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-28 15:44 ` Philippe Mathieu-Daudé
2021-05-26 23:46 ` [PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG Richard Henderson
` (24 subsequent siblings)
31 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Only 2 headers require "exec/tb-context.h". Instead of having
all files including "exec/exec-all.h" also including it, directly
include it where it is required:
- accel/tcg/cpu-exec.c
- accel/tcg/translate-all.c
For plugins/plugin.h, we were implicitly relying on
exec/exec-all.h -> exec/tb-context.h -> qemu/qht.h
which is now included directly.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210524170453.3791436-2-f4bug@amsat.org>
[rth: Fix plugins/plugin.h compilation]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 1 -
include/tcg/tcg.h | 1 -
plugins/plugin.h | 1 +
accel/tcg/cpu-exec.c | 1 +
accel/tcg/translate-all.c | 1 +
5 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 8021adf38f..754f4130c9 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -21,7 +21,6 @@
#define EXEC_ALL_H
#include "cpu.h"
-#include "exec/tb-context.h"
#ifdef CONFIG_TCG
#include "exec/cpu_ldst.h"
#endif
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 0f0695e90d..74cb345308 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -27,7 +27,6 @@
#include "cpu.h"
#include "exec/memop.h"
-#include "exec/tb-context.h"
#include "qemu/bitops.h"
#include "qemu/plugin.h"
#include "qemu/queue.h"
diff --git a/plugins/plugin.h b/plugins/plugin.h
index 1aa29dcadd..55017e3581 100644
--- a/plugins/plugin.h
+++ b/plugins/plugin.h
@@ -13,6 +13,7 @@
#define _PLUGIN_INTERNAL_H_
#include <gmodule.h>
+#include "qemu/qht.h"
#define QEMU_PLUGIN_MIN_VERSION 0
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 0dc5271715..10e11f27bb 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -31,6 +31,7 @@
#include "qemu/rcu.h"
#include "exec/tb-hash.h"
#include "exec/tb-lookup.h"
+#include "exec/tb-context.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 640ff6e3e7..e9f4de5190 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -48,6 +48,7 @@
#include "exec/cputlb.h"
#include "exec/tb-hash.h"
+#include "exec/tb-context.h"
#include "exec/translate-all.h"
#include "qemu/bitmap.h"
#include "qemu/error-report.h"
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion
2021-05-26 23:46 ` [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion Richard Henderson
@ 2021-05-28 15:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-28 15:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, Alex Bennée
On 5/27/21 1:46 AM, Richard Henderson wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Only 2 headers require "exec/tb-context.h". Instead of having
> all files including "exec/exec-all.h" also including it, directly
> include it where it is required:
> - accel/tcg/cpu-exec.c
> - accel/tcg/translate-all.c
>
> For plugins/plugin.h, we were implicitly relying on
> exec/exec-all.h -> exec/tb-context.h -> qemu/qht.h
> which is now included directly.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Message-Id: <20210524170453.3791436-2-f4bug@amsat.org>
> [rth: Fix plugins/plugin.h compilation]
Ah, I see you squashed:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg810344.html
I was hoping it goes via Alex's testing-next tree or trivial first,
so this wouldn't be a problem when you apply this patch.
Thanks anyway :)
Phil.
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 1 -
> include/tcg/tcg.h | 1 -
> plugins/plugin.h | 1 +
> accel/tcg/cpu-exec.c | 1 +
> accel/tcg/translate-all.c | 1 +
> 5 files changed, 3 insertions(+), 2 deletions(-)
> diff --git a/plugins/plugin.h b/plugins/plugin.h
> index 1aa29dcadd..55017e3581 100644
> --- a/plugins/plugin.h
> +++ b/plugins/plugin.h
> @@ -13,6 +13,7 @@
> #define _PLUGIN_INTERNAL_H_
>
> #include <gmodule.h>
> +#include "qemu/qht.h"
>
> #define QEMU_PLUGIN_MIN_VERSION 0
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (6 preceding siblings ...)
2021-05-26 23:46 ` [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 09/31] replay: fix watchpoint processing for reverse debugging Richard Henderson
` (23 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Only the TCG accelerator uses the TranslationBlock API.
Move the tb-context.h / tb-hash.h / tb-lookup.h from the
global namespace to the TCG one (in accel/tcg).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210524170453.3791436-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
{include/exec => accel/tcg}/tb-context.h | 0
{include/exec => accel/tcg}/tb-hash.h | 0
{include/exec => accel/tcg}/tb-lookup.h | 2 +-
accel/tcg/cpu-exec.c | 6 +++---
accel/tcg/cputlb.c | 2 +-
accel/tcg/tcg-runtime.c | 2 +-
accel/tcg/translate-all.c | 4 ++--
MAINTAINERS | 1 -
8 files changed, 8 insertions(+), 9 deletions(-)
rename {include/exec => accel/tcg}/tb-context.h (100%)
rename {include/exec => accel/tcg}/tb-hash.h (100%)
rename {include/exec => accel/tcg}/tb-lookup.h (98%)
diff --git a/include/exec/tb-context.h b/accel/tcg/tb-context.h
similarity index 100%
rename from include/exec/tb-context.h
rename to accel/tcg/tb-context.h
diff --git a/include/exec/tb-hash.h b/accel/tcg/tb-hash.h
similarity index 100%
rename from include/exec/tb-hash.h
rename to accel/tcg/tb-hash.h
diff --git a/include/exec/tb-lookup.h b/accel/tcg/tb-lookup.h
similarity index 98%
rename from include/exec/tb-lookup.h
rename to accel/tcg/tb-lookup.h
index 29d61ceb34..9c9e0079da 100644
--- a/include/exec/tb-lookup.h
+++ b/accel/tcg/tb-lookup.h
@@ -14,7 +14,7 @@
#endif
#include "exec/exec-all.h"
-#include "exec/tb-hash.h"
+#include "tb-hash.h"
/* Might cause an exception, so have a longjmp destination ready */
static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 10e11f27bb..ad1279d2ed 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -29,9 +29,6 @@
#include "qemu/compiler.h"
#include "qemu/timer.h"
#include "qemu/rcu.h"
-#include "exec/tb-hash.h"
-#include "exec/tb-lookup.h"
-#include "exec/tb-context.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
@@ -41,6 +38,9 @@
#include "exec/cpu-all.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/replay.h"
+#include "tb-hash.h"
+#include "tb-lookup.h"
+#include "tb-context.h"
#include "internal.h"
/* -icount align implementation. */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2f7088614a..f24348e979 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -24,7 +24,6 @@
#include "exec/memory.h"
#include "exec/cpu_ldst.h"
#include "exec/cputlb.h"
-#include "exec/tb-hash.h"
#include "exec/memory-internal.h"
#include "exec/ram_addr.h"
#include "tcg/tcg.h"
@@ -36,6 +35,7 @@
#include "exec/translate-all.h"
#include "trace/trace-root.h"
#include "trace/mem.h"
+#include "tb-hash.h"
#include "internal.h"
#ifdef CONFIG_PLUGIN
#include "qemu/plugin-memory.h"
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 49f5de37e8..66ac830e2f 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -30,7 +30,7 @@
#include "disas/disas.h"
#include "exec/log.h"
#include "tcg/tcg.h"
-#include "exec/tb-lookup.h"
+#include "tb-lookup.h"
/* 32-bit helpers */
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index e9f4de5190..1eefe6ea8d 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -47,8 +47,6 @@
#endif
#include "exec/cputlb.h"
-#include "exec/tb-hash.h"
-#include "exec/tb-context.h"
#include "exec/translate-all.h"
#include "qemu/bitmap.h"
#include "qemu/error-report.h"
@@ -61,6 +59,8 @@
#include "sysemu/tcg.h"
#include "qapi/error.h"
#include "hw/core/tcg-cpu-ops.h"
+#include "tb-hash.h"
+#include "tb-context.h"
#include "internal.h"
/* #define DEBUG_TB_INVALIDATE */
diff --git a/MAINTAINERS b/MAINTAINERS
index a77f246569..5f55404f2f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -128,7 +128,6 @@ F: docs/devel/decodetree.rst
F: include/exec/cpu*.h
F: include/exec/exec-all.h
F: include/exec/helper*.h
-F: include/exec/tb-hash.h
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
F: include/hw/core/tcg-cpu-ops.h
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 09/31] replay: fix watchpoint processing for reverse debugging
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (7 preceding siblings ...)
2021-05-26 23:46 ` [PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 10/31] tcg/aarch64: Fix tcg_out_rotl Richard Henderson
` (22 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Pavel Dovgalyuk
From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
This patch enables reverse debugging with watchpoints.
Reverse continue scans the execution to find the breakpoints
and watchpoints that should fire. It uses helper function
replay_breakpoint() for that. But this function needs to access
icount, which can't be correct in the middle of TB.
Therefore, in case of watchpoint, we have to retranslate the block
to allow this access.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <162072430303.827403.7379783546934958566.stgit@pasha-ThinkPad-X280>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
softmmu/physmem.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index e1da81ed2f..1c8717684a 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -904,6 +904,16 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
if (watchpoint_address_matches(wp, addr, len)
&& (wp->flags & flags)) {
if (replay_running_debug()) {
+ /*
+ * replay_breakpoint reads icount.
+ * Force recompile to succeed, because icount may
+ * be read only at the end of the block.
+ */
+ if (!cpu->can_do_io) {
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | CF_LAST_IO | curr_cflags(cpu);
+ cpu_loop_exit_restore(cpu, ra);
+ }
/*
* Don't process the watchpoints when we are
* in a reverse debugging operation.
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 10/31] tcg/aarch64: Fix tcg_out_rotl
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (8 preceding siblings ...)
2021-05-26 23:46 ` [PULL 09/31] replay: fix watchpoint processing for reverse debugging Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header Richard Henderson
` (21 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Yasuo Kuwahara
From: Yasuo Kuwahara <kwhr00@gmail.com>
The last argument of tcg_out_extr() must be in the range 0-31 if ext==0.
Before the fix, when m==0 it becomes 32 and it crashes with an Illegal
instruction on Apple Silicon. After the fix, it will be 0. If m is in
the range 1-31, it is the same as before.
Signed-off-by: Yasuo Kuwahara <kwhr00@gmail.com>
Message-Id: <CAHfJ0vSXnmnTLmT0kR=a8ACRdw_UsLYOhStzUzgVEHoH8U-7sA@mail.gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index f07ba98aa4..5bd366f2d4 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1291,9 +1291,8 @@ static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, unsigned int m)
{
- int bits = ext ? 64 : 32;
- int max = bits - 1;
- tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
+ int max = ext ? 63 : 31;
+ tcg_out_extr(s, ext, rd, rn, rn, -m & max);
}
static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd,
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (9 preceding siblings ...)
2021-05-26 23:46 ` [PULL 10/31] tcg/aarch64: Fix tcg_out_rotl Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 12/31] cpu: Split as cpu-common / cpu-sysemu Richard Henderson
` (20 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/core/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07d..919dc3435a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -34,7 +34,6 @@
#include "hw/qdev-properties.h"
#include "trace/trace-root.h"
#include "qemu/plugin.h"
-#include "sysemu/hw_accel.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 12/31] cpu: Split as cpu-common / cpu-sysemu
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (10 preceding siblings ...)
2021-05-26 23:46 ` [PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Richard Henderson
` (19 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The current cpu.c contains sysemu-specific methods.
To avoid building them in user-mode builds, split the
current cpu.c as cpu-common.c / cpu-sysemu.c.
Start by moving cpu_get_crash_info().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/core/{cpu.c => cpu-common.c} | 17 -----------------
hw/core/cpu-sysemu.c | 34 +++++++++++++++++++++++++++++++++
hw/core/meson.build | 3 ++-
3 files changed, 36 insertions(+), 18 deletions(-)
rename hw/core/{cpu.c => cpu-common.c} (96%)
create mode 100644 hw/core/cpu-sysemu.c
diff --git a/hw/core/cpu.c b/hw/core/cpu-common.c
similarity index 96%
rename from hw/core/cpu.c
rename to hw/core/cpu-common.c
index 919dc3435a..ddddf4b10e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu-common.c
@@ -190,23 +190,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
return target_words_bigendian();
}
-/*
- * XXX the following #if is always true because this is a common_ss
- * module, so target CONFIG_* is never defined.
- */
-#if !defined(CONFIG_USER_ONLY)
-GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- GuestPanicInformation *res = NULL;
-
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
- }
- return res;
-}
-#endif
-
void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
new file mode 100644
index 0000000000..f517ef5d46
--- /dev/null
+++ b/hw/core/cpu-sysemu.c
@@ -0,0 +1,34 @@
+/*
+ * QEMU CPU model (system emulation specific)
+ *
+ * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/core/cpu.h"
+
+GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ GuestPanicInformation *res = NULL;
+
+ if (cc->get_crash_info) {
+ res = cc->get_crash_info(cpu);
+ }
+ return res;
+}
diff --git a/hw/core/meson.build b/hw/core/meson.build
index 59f1605bb0..18f44fb7c2 100644
--- a/hw/core/meson.build
+++ b/hw/core/meson.build
@@ -13,7 +13,7 @@ hwcore_files = files(
'qdev-clock.c',
)
-common_ss.add(files('cpu.c'))
+common_ss.add(files('cpu-common.c'))
common_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c'))
common_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c'))
common_ss.add(when: ['CONFIG_GUEST_LOADER', fdt], if_true: files('guest-loader.c'))
@@ -25,6 +25,7 @@ common_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
softmmu_ss.add(files(
+ 'cpu-sysemu.c',
'fw-path-provider.c',
'loader.c',
'machine-hmp-cmds.c',
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (11 preceding siblings ...)
2021-05-26 23:46 ` [PULL 12/31] cpu: Split as cpu-common / cpu-sysemu Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian() Richard Henderson
` (18 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-7-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu-sysemu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d45f78290e..df49528785 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -586,18 +586,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -609,12 +599,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -623,17 +608,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index f517ef5d46..fe90dde868 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -22,6 +22,38 @@
#include "qapi/error.h"
#include "hw/core/cpu.h"
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian()
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (12 preceding siblings ...)
2021-05-26 23:46 ` [PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place Richard Henderson
` (17 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Similarly to commit bf7663c4bd8 ("cpu: introduce
CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method
name to hint this handler shouldn't be called anywhere but from the
virtio code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-8-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu-common.c | 6 ------
hw/core/cpu-sysemu.c | 10 ++++++++++
hw/virtio/virtio.c | 4 +---
4 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index df49528785..d96ff4dace 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -610,6 +610,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index ddddf4b10e..9d73c9a28c 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -185,11 +185,6 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
-{
- return target_words_bigendian();
-}
-
void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
@@ -388,7 +383,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index fe90dde868..078e1a84a5 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -54,6 +54,16 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
return ret;
}
+bool cpu_virtio_is_big_endian(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
+ return target_words_bigendian();
+}
+
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index e02544b2df..ab516ac614 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1972,9 +1972,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (13 preceding siblings ...)
2021-05-26 23:46 ` [PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian() Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 16/31] cpu: Directly use get_paging_enabled() " Richard Henderson
` (16 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/core/cpu-common.c | 63 --------------------------------------------
hw/core/cpu-sysemu.c | 44 +++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+), 63 deletions(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 9d73c9a28c..5913ffe22b 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -116,65 +116,6 @@ void cpu_exit(CPUState *cpu)
qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
}
-int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
-}
-
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
-int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
-}
-
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
-}
-
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
-int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
-}
-
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -377,10 +318,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index 078e1a84a5..7f3a357494 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -54,6 +54,50 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
return ret;
}
+int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
+ return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+}
+
+int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
+ return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+}
+
+int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
+ return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+}
+
+int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
+ return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+}
+
bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 16/31] cpu: Directly use get_paging_enabled() fallback handlers in place
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (14 preceding siblings ...)
2021-05-26 23:46 ` [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 17/31] cpu: Directly use get_memory_mapping() " Richard Henderson
` (15 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/core/cpu-common.c | 13 -------------
hw/core/cpu-sysemu.c | 11 +++++++++++
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 5913ffe22b..2aa6b8cffc 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -66,18 +66,6 @@ CPUState *cpu_create(const char *typename)
return cpu;
}
-bool cpu_paging_enabled(const CPUState *cpu)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- return cc->get_paging_enabled(cpu);
-}
-
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
- return false;
-}
-
void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp)
{
@@ -316,7 +304,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index 7f3a357494..931ba46354 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -22,6 +22,17 @@
#include "qapi/error.h"
#include "hw/core/cpu.h"
+bool cpu_paging_enabled(const CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
+
+ return false;
+}
+
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 17/31] cpu: Directly use get_memory_mapping() fallback handlers in place
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (15 preceding siblings ...)
2021-05-26 23:46 ` [PULL 16/31] cpu: Directly use get_paging_enabled() " Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation Richard Henderson
` (14 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-11-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/core/cpu-common.c | 16 ----------------
hw/core/cpu-sysemu.c | 13 +++++++++++++
2 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 2aa6b8cffc..9530e266ec 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -66,21 +66,6 @@ CPUState *cpu_create(const char *typename)
return cpu;
}
-void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
- Error **errp)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- cc->get_memory_mapping(cpu, list, errp);
-}
-
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
- error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
-}
-
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
@@ -304,7 +289,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index 931ba46354..aa68ca281e 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -33,6 +33,19 @@ bool cpu_paging_enabled(const CPUState *cpu)
return false;
}
+void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
+ Error **errp)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
+
+ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
+}
+
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (16 preceding siblings ...)
2021-05-26 23:46 ` [PULL 17/31] cpu: Directly use get_memory_mapping() " Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd Richard Henderson
` (13 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Migration is specific to system emulation.
Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
and assert in cpu_exec_realizefn() that dc->vmsd not set under
user emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-12-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
cpu.c | 2 ++
target/sh4/cpu.c | 5 +++--
target/xtensa/cpu.c | 4 +++-
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/cpu.c b/cpu.c
index 34a0484bf4..6fe4af2797 100644
--- a/cpu.c
+++ b/cpu.c
@@ -141,6 +141,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#endif /* CONFIG_TCG */
#ifdef CONFIG_USER_ONLY
+ assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
+ qdev_get_vmsd(DEVICE(cpu))->unmigratable);
assert(cc->vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f..35d4251aaf 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_sh_cpu;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
cc->gdb_num_core_regs = 59;
-
- dc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 210ef80092..0267571fbd 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -175,10 +175,12 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -215,9 +217,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
+ dc->vmsd = &vmstate_xtensa_cpu;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (17 preceding siblings ...)
2021-05-26 23:46 ` [PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:46 ` [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass Richard Henderson
` (12 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Quoting Peter Maydell [*]:
There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the
vmstate_cpu_common directly to handle the cpu-common fields,
and the cc->vmsd to handle the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).
See also commit b170fce3dd0 ("cpu: Register VMStateDescription
through CPUState") for historic background.
[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 5 +++--
cpu.c | 12 ++++++------
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu.c | 3 +--
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
10 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d96ff4dace..1dfb788415 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -122,7 +122,8 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
+ * @legacy_vmsd: Legacy state description for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -177,7 +178,7 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
+ const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/cpu.c b/cpu.c
index 6fe4af2797..c57f4c302b 100644
--- a/cpu.c
+++ b/cpu.c
@@ -143,13 +143,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
qdev_get_vmsd(DEVICE(cpu))->unmigratable);
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
@@ -159,10 +159,10 @@ void cpu_exec_unrealizefn(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
+ assert(cc->legacy_vmsd == NULL);
#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7aeb4b1381..bf82276611 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1983,7 +1983,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
+ cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932b..37a8ebcc86 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
+ cc->legacy_vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c496bfa1c2..5a1c8ead8e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6749,7 +6749,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
+ cc->legacy_vmsd = &vmstate_x86_cpu;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1ad2fe4aa3..eba56ac899 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -561,7 +561,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
+ cc->legacy_vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 22ecbccad8..668fd141db 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9305,7 +9305,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
+ cc->legacy_vmsd = &vmstate_ppc_cpu;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3191fd0082..16510da259 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -638,8 +638,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
+ cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 64455cf309..7ce425f611 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
+ cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc8..ba497561bf 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
+ cc->legacy_vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (18 preceding siblings ...)
2021-05-26 23:46 ` [PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd Richard Henderson
@ 2021-05-26 23:46 ` Richard Henderson
2021-05-26 23:47 ` [PULL 21/31] cpu: Introduce SysemuCPUOps structure Richard Henderson
` (11 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:46 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
See rationale in previous commit. Targets should use the vmsd field
of DeviceClass, not CPUClass. As migration is not important on the
AVR target, break the migration compatibility and set the DeviceClass
vmsd field. To feel safer, increment the vmstate version.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210517105140.1062037-14-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/cpu.c | 2 +-
target/avr/machine.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 37a8ebcc86..3353bcb9fc 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vms_avr_cpu;
+ dc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/avr/machine.c b/target/avr/machine.c
index de264f57c3..16f7a3e031 100644
--- a/target/avr/machine.c
+++ b/target/avr/machine.c
@@ -98,8 +98,8 @@ static const VMStateInfo vms_eind = {
const VMStateDescription vms_avr_cpu = {
.name = "cpu",
- .version_id = 0,
- .minimum_version_id = 0,
+ .version_id = 1,
+ .minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.pc_w, AVRCPU),
VMSTATE_UINT32(env.sp, AVRCPU),
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 21/31] cpu: Introduce SysemuCPUOps structure
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (19 preceding siblings ...)
2021-05-26 23:46 ` [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps Richard Henderson
` (10 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org>
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 6 ++++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
cpu.c | 1 +
target/alpha/cpu.c | 8 ++++++++
target/arm/cpu.c | 8 ++++++++
target/avr/cpu.c | 6 ++++++
target/cris/cpu.c | 8 ++++++++
target/hppa/cpu.c | 8 ++++++++
target/i386/cpu.c | 8 ++++++++
target/m68k/cpu.c | 8 ++++++++
target/microblaze/cpu.c | 8 ++++++++
target/mips/cpu.c | 8 ++++++++
target/nios2/cpu.c | 8 ++++++++
target/openrisc/cpu.c | 8 ++++++++
target/ppc/cpu_init.c | 8 ++++++++
target/riscv/cpu.c | 8 ++++++++
target/rx/cpu.c | 10 ++++++++++
target/s390x/cpu.c | 8 ++++++++
target/sh4/cpu.c | 6 ++++++
target/sparc/cpu.c | 8 ++++++++
target/tricore/cpu.c | 6 ++++++
target/xtensa/cpu.c | 6 ++++++
22 files changed, 174 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1dfb788415..cd3fb70cb5 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,9 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -191,6 +194,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 0000000000..e54a08ea25
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/cpu.c b/cpu.c
index c57f4c302b..e3f9804f13 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e2..0b12b2be81 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,13 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +245,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bf82276611..0116e9d8e8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1944,6 +1944,13 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -1987,6 +1994,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 3353bcb9fc..b95caf8c0f 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,11 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +219,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
dc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fc..f1095fcf5c 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,13 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +301,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1f..870130b159 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,13 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +170,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5a1c8ead8e..e422fab49a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6714,6 +6714,13 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -6750,6 +6757,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->legacy_vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index a14874b4da..97ef3ae31c 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -503,6 +503,13 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -535,6 +542,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba20203..96f221ff71 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,13 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +395,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index eba56ac899..9a8c484cb4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -521,6 +521,13 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -562,6 +569,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a38..cb04b04d24 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,13 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +245,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46..12d9173043 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,13 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +212,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 668fd141db..302b9b92a5 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9263,6 +9263,13 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -9306,6 +9313,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16510da259..b2b4a0baf4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -596,6 +596,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -639,6 +646,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26..98e6596158 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,13 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +209,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7ce425f611..77800e99b9 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -476,6 +476,13 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -519,6 +526,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 35d4251aaf..79aec898fa 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps sh4_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -259,6 +264,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
dc->vmsd = &vmstate_sh_cpu;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ba497561bf..70be0ecf5e 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,13 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +897,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->legacy_vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcb..7dc6aab66c 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,11 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +176,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 0267571fbd..a196530451 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -180,6 +180,11 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
+
+#include "hw/core/sysemu-cpu-ops.h"
+
+static const struct SysemuCPUOps xtensa_sysemu_ops = {
+};
#endif
#include "hw/core/tcg-cpu-ops.h"
@@ -216,6 +221,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_xtensa_cpu;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (20 preceding siblings ...)
2021-05-26 23:47 ` [PULL 21/31] cpu: Introduce SysemuCPUOps structure Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian " Richard Henderson
` (9 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Migration is specific to system emulation.
- Move the CPUClass::vmsd field to SysemuCPUOps,
- restrict VMSTATE_CPU() macro to sysemu,
- vmstate_dummy is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-16-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 8 ++------
include/hw/core/sysemu-cpu-ops.h | 6 ++++++
include/migration/vmstate.h | 2 --
cpu.c | 15 +++++++--------
stubs/vmstate.c | 2 --
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
12 files changed, 22 insertions(+), 25 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index cd3fb70cb5..c8d4a8a642 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -125,8 +125,6 @@ struct SysemuCPUOps;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @legacy_vmsd: Legacy state description for migration.
- * Do not use in new targets, use #DeviceClass::vmsd instead.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -181,7 +179,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *legacy_vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
@@ -1065,10 +1062,8 @@ bool target_words_bigendian(void);
#ifdef NEED_CPU_H
#ifdef CONFIG_SOFTMMU
+
extern const VMStateDescription vmstate_cpu_common;
-#else
-#define vmstate_cpu_common vmstate_dummy
-#endif
#define VMSTATE_CPU() { \
.name = "parent_obj", \
@@ -1077,6 +1072,7 @@ extern const VMStateDescription vmstate_cpu_common;
.flags = VMS_STRUCT, \
.offset = 0, \
}
+#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25..0370ac1519 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,12 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @legacy_vmsd: Legacy state for migration.
+ * Do not use in new targets, use #DeviceClass::vmsd instead.
+ */
+ const VMStateDescription *legacy_vmsd;
+
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 075ee80096..8df7b69f38 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -194,8 +194,6 @@ struct VMStateDescription {
const VMStateDescription **subsections;
};
-extern const VMStateDescription vmstate_dummy;
-
extern const VMStateInfo vmstate_info_bool;
extern const VMStateInfo vmstate_info_int8;
diff --git a/cpu.c b/cpu.c
index e3f9804f13..164fefeaa3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -128,7 +128,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
if (!accel_cpu_realizefn(cpu, errp)) {
@@ -144,26 +146,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
#ifdef CONFIG_USER_ONLY
assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
qdev_get_vmsd(DEVICE(cpu))->unmigratable);
- assert(cc->legacy_vmsd == NULL);
#else
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->legacy_vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu);
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->legacy_vmsd == NULL);
-#else
- if (cc->legacy_vmsd != NULL) {
- vmstate_unregister(NULL, cc->legacy_vmsd, cpu);
+ if (cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/stubs/vmstate.c b/stubs/vmstate.c
index cc4fe41dfc..8513d9204e 100644
--- a/stubs/vmstate.c
+++ b/stubs/vmstate.c
@@ -1,8 +1,6 @@
#include "qemu/osdep.h"
#include "migration/vmstate.h"
-const VMStateDescription vmstate_dummy = {};
-
int vmstate_register_with_alias_id(VMStateIf *obj,
uint32_t instance_id,
const VMStateDescription *vmsd,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0116e9d8e8..bd623a4961 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1948,6 +1948,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .legacy_vmsd = &vmstate_arm_cpu,
};
#endif
@@ -1990,7 +1991,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->legacy_vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e422fab49a..761fffee34 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6718,6 +6718,7 @@ static Property x86_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -6756,7 +6757,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->legacy_vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 9a8c484cb4..7aa3f3ecf5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -525,6 +525,7 @@ static Property mips_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .legacy_vmsd = &vmstate_mips_cpu,
};
#endif
@@ -568,7 +569,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 302b9b92a5..5121f9cfd4 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9267,6 +9267,7 @@ static Property ppc_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .legacy_vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -9312,7 +9313,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b2b4a0baf4..44b1f70051 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -600,6 +600,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .legacy_vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -645,7 +646,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
cc->write_elf64_note = riscv_cpu_write_elf64_note;
cc->write_elf32_note = riscv_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 77800e99b9..d7ab7c95b1 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 70be0ecf5e..ffe85a7f59 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -852,6 +852,7 @@ static Property sparc_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .legacy_vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -896,7 +897,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->legacy_vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (21 preceding siblings ...)
2021-05-26 23:47 ` [PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 24/31] cpu: Move CPUClass::get_crash_info " Richard Henderson
` (8 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
VirtIO devices are only meaningful with system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-17-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 9 +++++++++
hw/core/cpu-sysemu.c | 5 +++--
target/arm/cpu.c | 2 +-
target/ppc/cpu_init.c | 4 +---
5 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c8d4a8a642..dd3f5f996e 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -90,10 +90,6 @@ struct SysemuCPUOps;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -152,7 +148,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 0370ac1519..8fa98bf2a7 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,15 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
+
/**
* @legacy_vmsd: Legacy state for migration.
* Do not use in new targets, use #DeviceClass::vmsd instead.
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index aa68ca281e..bad7d2cb01 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/core/cpu.h"
+#include "hw/core/sysemu-cpu-ops.h"
bool cpu_paging_enabled(const CPUState *cpu)
{
@@ -126,8 +127,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bd623a4961..0111201235 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1948,6 +1948,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.legacy_vmsd = &vmstate_arm_cpu,
};
#endif
@@ -1991,7 +1992,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5121f9cfd4..108e0c6580 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9267,6 +9267,7 @@ static Property ppc_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.legacy_vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -9335,9 +9336,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 24/31] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (22 preceding siblings ...)
2021-05-26 23:47 ` [PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 25/31] cpu: Move CPUClass::write_elf* " Richard Henderson
` (7 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-18-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu-sysemu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index dd3f5f996e..bf7d11b14f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -151,7 +151,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 8fa98bf2a7..b9383101fc 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index bad7d2cb01..90b5ac8eb9 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -138,8 +138,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 761fffee34..7761f2fa4c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6718,6 +6718,7 @@ static Property x86_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -6752,7 +6753,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d7ab7c95b1..d2175a87f5 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 25/31] cpu: Move CPUClass::write_elf* to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (23 preceding siblings ...)
2021-05-26 23:47 ` [PULL 24/31] cpu: Move CPUClass::get_crash_info " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 26/31] cpu: Move CPUClass::asidx_from_attrs " Richard Henderson
` (6 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu-sysemu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/ppc/cpu_init.c | 6 ++----
target/riscv/cpu.c | 4 ++--
target/s390x/cpu.c | 2 +-
8 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index bf7d11b14f..15b16d3f6d 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -113,14 +113,6 @@ struct SysemuCPUOps;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -164,15 +156,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index b9383101fc..52ac0ae4e1 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index 90b5ac8eb9..d55ef8d23d 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -84,10 +84,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -95,10 +95,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -106,10 +106,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -117,10 +117,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
bool cpu_virtio_is_big_endian(CPUState *cpu)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0111201235..18627cc3c6 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1948,6 +1948,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.legacy_vmsd = &vmstate_arm_cpu,
};
@@ -1992,8 +1994,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7761f2fa4c..2ba82921d6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6719,6 +6719,10 @@ static Property x86_cpu_properties[] = {
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.legacy_vmsd = &vmstate_x86_cpu,
};
#endif
@@ -6753,10 +6757,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 108e0c6580..16d966696b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9267,6 +9267,8 @@ static Property ppc_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.legacy_vmsd = &vmstate_ppc_cpu,
};
@@ -9316,10 +9318,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 44b1f70051..80cee005a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -600,6 +600,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .write_elf64_note = riscv_cpu_write_elf64_note,
+ .write_elf32_note = riscv_cpu_write_elf32_note,
.legacy_vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -647,8 +649,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
- cc->write_elf64_note = riscv_cpu_write_elf64_note;
- cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d2175a87f5..157ef61d38 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -481,6 +481,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
static const struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.legacy_vmsd = &vmstate_s390_cpu,
};
#endif
@@ -525,7 +526,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 26/31] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (24 preceding siblings ...)
2021-05-26 23:47 ` [PULL 25/31] cpu: Move CPUClass::write_elf* " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 27/31] cpu: Move CPUClass::get_phys_page_debug " Richard Henderson
` (5 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-20-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu-sysemu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 15b16d3f6d..af6246c905 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -109,8 +109,6 @@ struct SysemuCPUOps;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -152,7 +150,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 52ac0ae4e1..8f8326e810 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index d55ef8d23d..ba53c2eaa8 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -72,8 +72,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 18627cc3c6..85666b765f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1948,6 +1948,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -1993,7 +1994,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2ba82921d6..45e7ded0ce 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6718,6 +6718,7 @@ static Property x86_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -6754,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 27/31] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (25 preceding siblings ...)
2021-05-26 23:47 ` [PULL 26/31] cpu: Move CPUClass::asidx_from_attrs " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 28/31] cpu: Move CPUClass::get_memory_mapping " Richard Henderson
` (4 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org>
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu-sysemu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
22 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index af6246c905..405d1f367f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -104,11 +104,6 @@ struct SysemuCPUOps;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -147,9 +142,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 8f8326e810..1f249e0f06 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index ba53c2eaa8..b31c33ad2b 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -52,12 +52,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 0b12b2be81..7687d5a09a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
};
#endif
@@ -243,7 +244,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 85666b765f..2d9b32ec92 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1948,6 +1948,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -1993,7 +1994,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index b95caf8c0f..7551bca3a6 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -187,6 +187,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -217,7 +218,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
dc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index f1095fcf5c..9cb4f817b4 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
};
#endif
@@ -299,7 +300,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 870130b159..4018e3ad90 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
};
#endif
@@ -168,7 +169,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 45e7ded0ce..de212a939d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6718,6 +6718,7 @@ static Property x86_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -6756,7 +6757,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 97ef3ae31c..4238775d5e 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -507,6 +507,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
};
#endif
@@ -540,7 +541,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 96f221ff71..8f88f2afb9 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
};
#endif
@@ -393,7 +394,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 7aa3f3ecf5..7275f64eab 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -525,6 +525,7 @@ static Property mips_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.legacy_vmsd = &vmstate_mips_cpu,
};
#endif
@@ -568,7 +569,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index cb04b04d24..afcd776746 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -211,6 +211,7 @@ static Property nios2_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
};
#endif
@@ -244,7 +245,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 12d9173043..d8e80b81a2 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
};
#endif
@@ -210,7 +211,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 16d966696b..1afa29e338 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9267,6 +9267,7 @@ static Property ppc_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -9315,7 +9316,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 80cee005a3..9775d8ca5c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -600,6 +600,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
.write_elf64_note = riscv_cpu_write_elf64_note,
.write_elf32_note = riscv_cpu_write_elf32_note,
.legacy_vmsd = &vmstate_riscv_cpu,
@@ -647,7 +648,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 98e6596158..e575669ad1 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
};
#endif
@@ -214,7 +215,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 157ef61d38..bd5070c783 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.legacy_vmsd = &vmstate_s390_cpu,
@@ -525,7 +526,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 79aec898fa..1d5a715631 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
};
#endif
@@ -263,7 +264,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
dc->vmsd = &vmstate_sh_cpu;
#endif
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ffe85a7f59..ff950fb307 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -852,6 +852,7 @@ static Property sparc_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.legacy_vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -896,7 +897,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 7dc6aab66c..ff17d1cecd 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -145,6 +145,7 @@ static void tc27x_initfn(Object *obj)
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -175,7 +176,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index a196530451..da4dbecdf1 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -184,6 +184,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
};
#endif
@@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_xtensa_cpu;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 28/31] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (26 preceding siblings ...)
2021-05-26 23:47 ` [PULL 27/31] cpu: Move CPUClass::get_phys_page_debug " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 29/31] cpu: Move CPUClass::get_paging_enabled " Richard Henderson
` (3 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-22-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu-sysemu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 405d1f367f..4f6dd24112 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -95,7 +95,6 @@ struct SysemuCPUOps;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -139,8 +138,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 1f249e0f06..213e5287ab 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index b31c33ad2b..3850fcb27f 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -39,8 +39,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index de212a939d..d400feec8f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6718,6 +6718,7 @@ static Property x86_cpu_properties[] = {
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -6756,7 +6757,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 29/31] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (27 preceding siblings ...)
2021-05-26 23:47 ` [PULL 28/31] cpu: Move CPUClass::get_memory_mapping " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Richard Henderson
` (2 subsequent siblings)
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-23-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu-sysemu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4f6dd24112..e4328de8d4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct SysemuCPUOps;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -137,7 +136,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 213e5287ab..a9ba39e5f2 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index 3850fcb27f..00253f8929 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -27,8 +27,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d400feec8f..744afc0ff2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6485,12 +6485,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -6719,6 +6721,7 @@ static Property x86_cpu_properties[] = {
static const struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -6754,7 +6757,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (28 preceding siblings ...)
2021-05-26 23:47 ` [PULL 29/31] cpu: Move CPUClass::get_paging_enabled " Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-26 23:47 ` [PULL 31/31] hw/core: Constify TCGCPUOps Richard Henderson
2021-05-28 18:25 ` [PULL 00/31] tcg patch queue Peter Maydell
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Add a flag to MIPSCPUClass in order to avoid needing to
replace mips_tcg_ops.do_transaction_failed.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
---
target/mips/cpu-qom.h | 3 +++
hw/mips/jazz.c | 35 +++--------------------------------
target/mips/tcg/op_helper.c | 3 ++-
3 files changed, 8 insertions(+), 33 deletions(-)
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 826ab13019..dda0c911fa 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -47,6 +47,9 @@ struct MIPSCPUClass {
DeviceRealize parent_realize;
DeviceReset parent_reset;
const struct mips_def_t *cpu_def;
+
+ /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
+ bool no_data_aborts;
};
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index dba2088ed1..1e1cf8154e 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -119,30 +119,6 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
-static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr);
-
-static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr)
-{
- if (access_type != MMU_INST_FETCH) {
- /* ignore invalid access (ie do not raise exception) */
- return;
- }
- (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
-}
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
@@ -151,7 +127,7 @@ static void mips_jazz_init(MachineState *machine,
int bios_size, n;
Clock *cpuclk;
MIPSCPU *cpu;
- CPUClass *cc;
+ MIPSCPUClass *mcc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
@@ -198,8 +174,6 @@ static void mips_jazz_init(MachineState *machine,
* However, we can't simply add a global memory region to catch
* everything, as this would make all accesses including instruction
* accesses be ignored and not raise exceptions.
- * So instead we hijack the do_transaction_failed method on the CPU, and
- * do not raise exceptions for data access.
*
* NOTE: this behaviour of raising exceptions for bad instruction
* fetches but not bad data accesses was added in commit 54e755588cf1e9
@@ -209,11 +183,8 @@ static void mips_jazz_init(MachineState *machine,
* we could replace this hijacking of CPU methods with a simple global
* memory region that catches all memory accesses, as we do on Malta.
*/
- cc = CPU_GET_CLASS(cpu);
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
- cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+ mcc = MIPS_CPU_GET_CLASS(cpu);
+ mcc->no_data_aborts = true;
/* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram);
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index ce1549c985..fafbf1faca 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -409,11 +409,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env;
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr);
- } else {
+ } else if (!mcc->no_data_aborts) {
do_raise_exception(env, EXCP_DBE, retaddr);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PULL 31/31] hw/core: Constify TCGCPUOps
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (29 preceding siblings ...)
2021-05-26 23:47 ` [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Richard Henderson
@ 2021-05-26 23:47 ` Richard Henderson
2021-05-28 18:25 ` [PULL 00/31] tcg patch queue Peter Maydell
31 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-05-26 23:47 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
We no longer have any runtime modifications to this struct,
so declare them all const.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 2 +-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/cpu_tcg.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 4 ++--
target/hexagon/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
22 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e4328de8d4..9f09a60fbd 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -156,7 +156,7 @@ struct CPUClass {
const struct SysemuCPUOps *sysemu_ops;
/* when TCG is not available, this pointer is NULL */
- struct TCGCPUOps *tcg_ops;
+ const struct TCGCPUOps *tcg_ops;
/*
* if not NULL, this is called in order for the CPUClass to initialize
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 7687d5a09a..4871ad0c0a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -216,7 +216,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps alpha_tcg_ops = {
+static const struct TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.tlb_fill = alpha_cpu_tlb_fill,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2d9b32ec92..ad65b60b04 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1958,7 +1958,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
-static struct TCGCPUOps arm_tcg_ops = {
+static const struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index d3458335ed..2e0e508f0e 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -898,7 +898,7 @@ static void pxa270c5_initfn(Object *obj)
}
#ifdef CONFIG_TCG
-static struct TCGCPUOps arm_v7m_tcg_ops = {
+static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 7551bca3a6..57e3fab4a0 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -192,7 +192,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps avr_tcg_ops = {
+static const struct TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
.cpu_exec_interrupt = avr_cpu_exec_interrupt,
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 9cb4f817b4..70932b1f8c 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -203,7 +203,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps crisv10_tcg_ops = {
+static const struct TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
.tlb_fill = cris_cpu_tlb_fill,
@@ -213,7 +213,7 @@ static struct TCGCPUOps crisv10_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
-static struct TCGCPUOps crisv32_tcg_ops = {
+static const struct TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
.tlb_fill = cris_cpu_tlb_fill,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index ebe60a6e15..3338365c16 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -269,7 +269,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps hexagon_tcg_ops = {
+static const struct TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
.tlb_fill = hexagon_tlb_fill,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4018e3ad90..2eace4ee12 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -141,7 +141,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps hppa_tcg_ops = {
+static const struct TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index ba39531aa5..014ebea2f6 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -56,7 +56,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps x86_tcg_ops = {
+static const struct TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.cpu_exec_enter = x86_cpu_exec_enter,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 4238775d5e..72de6e9726 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -513,7 +513,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps m68k_tcg_ops = {
+static const struct TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
.cpu_exec_interrupt = m68k_cpu_exec_interrupt,
.tlb_fill = m68k_cpu_tlb_fill,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 8f88f2afb9..72d8f2a0da 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -362,7 +362,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps mb_tcg_ops = {
+static const struct TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 7275f64eab..96236abc00 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -536,7 +536,7 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
* NB: cannot be const, as some elements are changed for specific
* mips hardware (see hw/mips/jazz.c).
*/
-static struct TCGCPUOps mips_tcg_ops = {
+static const struct TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
.cpu_exec_interrupt = mips_cpu_exec_interrupt,
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index afcd776746..5e37defef8 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -217,7 +217,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps nios2_tcg_ops = {
+static const struct TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
.tlb_fill = nios2_cpu_tlb_fill,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index d8e80b81a2..bd34e429ec 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -184,7 +184,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps openrisc_tcg_ops = {
+static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
.tlb_fill = openrisc_cpu_tlb_fill,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1afa29e338..7bdb443114 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9278,7 +9278,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps ppc_tcg_ops = {
+static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.tlb_fill = ppc_cpu_tlb_fill,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9775d8ca5c..1f1cef1d6a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -609,7 +609,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps riscv_tcg_ops = {
+static const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index e575669ad1..96cc96e514 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -183,7 +183,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps rx_tcg_ops = {
+static const struct TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
.cpu_exec_interrupt = rx_cpu_exec_interrupt,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index bd5070c783..890f382a36 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -490,7 +490,7 @@ static const struct SysemuCPUOps s390_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps s390_tcg_ops = {
+static const struct TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
.tlb_fill = s390_cpu_tlb_fill,
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 1d5a715631..8326922942 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -233,7 +233,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps superh_tcg_ops = {
+static const struct TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
.cpu_exec_interrupt = superh_cpu_exec_interrupt,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ff950fb307..da6b30ec74 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -860,7 +860,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps sparc_tcg_ops = {
+static const struct TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index ff17d1cecd..b95682b7f0 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -150,7 +150,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps tricore_tcg_ops = {
+static const struct TCGCPUOps tricore_tcg_ops = {
.initialize = tricore_tcg_init,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
.tlb_fill = tricore_cpu_tlb_fill,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index da4dbecdf1..58ec3a0862 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -190,7 +190,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
-static struct TCGCPUOps xtensa_tcg_ops = {
+static const struct TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
.tlb_fill = xtensa_cpu_tlb_fill,
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PULL 00/31] tcg patch queue
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
` (30 preceding siblings ...)
2021-05-26 23:47 ` [PULL 31/31] hw/core: Constify TCGCPUOps Richard Henderson
@ 2021-05-28 18:25 ` Peter Maydell
31 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-05-28 18:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 27 May 2021 at 00:47, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 0319ad22bd5789e1eaa8a2dd5773db2d2c372f20:
>
> Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2' into staging (2021-05-25 17:31:04 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210526
>
> for you to fetch changes up to 119065574d02deffc28fe5b6a864db9b467c6ffd:
>
> hw/core: Constify TCGCPUOps (2021-05-26 15:33:59 -0700)
>
> ----------------------------------------------------------------
> Adjust types for some memory access functions.
> Reduce inclusion of tcg headers.
> Fix watchpoints vs replay.
> Fix tcg/aarch64 roli expansion.
> Introduce SysemuCPUOps structure.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread