* [PATCH 0/3] target/arm: Decode fixes for aarch64
@ 2021-06-04 18:35 Richard Henderson
2021-06-04 18:35 ` [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Richard Henderson
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Richard Henderson @ 2021-06-04 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
A couple of printfs left over from the beginning of time,
and asserts that are reachable because of lack of decode.
r~
Richard Henderson (3):
target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
target/arm: Remove fprintf from disas_simd_mod_imm
target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
target/arm/translate-a64.c | 87 +++++++++++++++++++++++---------------
1 file changed, 52 insertions(+), 35 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
2021-06-04 18:35 [PATCH 0/3] target/arm: Decode fixes for aarch64 Richard Henderson
@ 2021-06-04 18:35 ` Richard Henderson
2021-06-06 18:45 ` Philippe Mathieu-Daudé
2021-06-04 18:35 ` [PATCH 2/3] target/arm: Remove fprintf from disas_simd_mod_imm Richard Henderson
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2021-06-04 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This fprintf+assert has been in place since the beginning.
It is prior to the fp_access_check, so we're still good to
raise sigill here.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8713dfec17..2477b55c53 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -13234,8 +13234,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7f: /* FSQRT (vector) */
break;
default:
- fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
- g_assert_not_reached();
+ unallocated_encoding(s);
+ return;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] target/arm: Remove fprintf from disas_simd_mod_imm
2021-06-04 18:35 [PATCH 0/3] target/arm: Decode fixes for aarch64 Richard Henderson
2021-06-04 18:35 ` [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Richard Henderson
@ 2021-06-04 18:35 ` Richard Henderson
2021-06-06 18:46 ` Philippe Mathieu-Daudé
2021-06-04 18:35 ` [PATCH 3/3] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Richard Henderson
2021-06-08 8:59 ` [PATCH 0/3] target/arm: Decode fixes for aarch64 Peter Maydell
3 siblings, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2021-06-04 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
The default of this switch is truly unreachable.
The switch selector is 3 bits, and all 8 cases are present.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2477b55c53..9bb15ca618 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -8291,7 +8291,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
}
break;
default:
- fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
2021-06-04 18:35 [PATCH 0/3] target/arm: Decode fixes for aarch64 Richard Henderson
2021-06-04 18:35 ` [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Richard Henderson
2021-06-04 18:35 ` [PATCH 2/3] target/arm: Remove fprintf from disas_simd_mod_imm Richard Henderson
@ 2021-06-04 18:35 ` Richard Henderson
2021-06-06 18:47 ` Philippe Mathieu-Daudé
2021-06-08 8:59 ` [PATCH 0/3] target/arm: Decode fixes for aarch64 Peter Maydell
3 siblings, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2021-06-04 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This fprintf+assert has been in place since the beginning.
It is after to the fp_access_check, so we need to move the
check up. Fold that in to the pairwise filter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 82 +++++++++++++++++++++++---------------
1 file changed, 50 insertions(+), 32 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9bb15ca618..7f74d0e81a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11989,12 +11989,57 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
*/
static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
{
- int opcode, fpopcode;
- int is_q, u, a, rm, rn, rd;
- int datasize, elements;
- int pass;
+ int opcode = extract32(insn, 11, 3);
+ int u = extract32(insn, 29, 1);
+ int a = extract32(insn, 23, 1);
+ int is_q = extract32(insn, 30, 1);
+ int rm = extract32(insn, 16, 5);
+ int rn = extract32(insn, 5, 5);
+ int rd = extract32(insn, 0, 5);
+ /*
+ * For these floating point ops, the U, a and opcode bits
+ * together indicate the operation.
+ */
+ int fpopcode = opcode | (a << 3) | (u << 4);
+ int datasize = is_q ? 128 : 64;
+ int elements = datasize / 16;
+ bool pairwise;
TCGv_ptr fpst;
- bool pairwise = false;
+ int pass;
+
+ switch (fpopcode) {
+ case 0x0: /* FMAXNM */
+ case 0x1: /* FMLA */
+ case 0x2: /* FADD */
+ case 0x3: /* FMULX */
+ case 0x4: /* FCMEQ */
+ case 0x6: /* FMAX */
+ case 0x7: /* FRECPS */
+ case 0x8: /* FMINNM */
+ case 0x9: /* FMLS */
+ case 0xa: /* FSUB */
+ case 0xe: /* FMIN */
+ case 0xf: /* FRSQRTS */
+ case 0x13: /* FMUL */
+ case 0x14: /* FCMGE */
+ case 0x15: /* FACGE */
+ case 0x17: /* FDIV */
+ case 0x1a: /* FABD */
+ case 0x1c: /* FCMGT */
+ case 0x1d: /* FACGT */
+ pairwise = false;
+ break;
+ case 0x10: /* FMAXNMP */
+ case 0x12: /* FADDP */
+ case 0x16: /* FMAXP */
+ case 0x18: /* FMINNMP */
+ case 0x1e: /* FMINP */
+ pairwise = true;
+ break;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
@@ -12005,31 +12050,6 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
return;
}
- /* For these floating point ops, the U, a and opcode bits
- * together indicate the operation.
- */
- opcode = extract32(insn, 11, 3);
- u = extract32(insn, 29, 1);
- a = extract32(insn, 23, 1);
- is_q = extract32(insn, 30, 1);
- rm = extract32(insn, 16, 5);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
-
- fpopcode = opcode | (a << 3) | (u << 4);
- datasize = is_q ? 128 : 64;
- elements = datasize / 16;
-
- switch (fpopcode) {
- case 0x10: /* FMAXNMP */
- case 0x12: /* FADDP */
- case 0x16: /* FMAXP */
- case 0x18: /* FMINNMP */
- case 0x1e: /* FMINP */
- pairwise = true;
- break;
- }
-
fpst = fpstatus_ptr(FPST_FPCR_F16);
if (pairwise) {
@@ -12152,8 +12172,6 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
- fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
- __func__, insn, fpopcode, s->pc_curr);
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
2021-06-04 18:35 ` [PATCH 1/3] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Richard Henderson
@ 2021-06-06 18:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-06 18:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 6/4/21 8:35 PM, Richard Henderson wrote:
> This fprintf+assert has been in place since the beginning.
> It is prior to the fp_access_check, so we're still good to
> raise sigill here.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-a64.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] target/arm: Remove fprintf from disas_simd_mod_imm
2021-06-04 18:35 ` [PATCH 2/3] target/arm: Remove fprintf from disas_simd_mod_imm Richard Henderson
@ 2021-06-06 18:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-06 18:46 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 6/4/21 8:35 PM, Richard Henderson wrote:
> The default of this switch is truly unreachable.
> The switch selector is 3 bits, and all 8 cases are present.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-a64.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
2021-06-04 18:35 ` [PATCH 3/3] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Richard Henderson
@ 2021-06-06 18:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-06 18:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 6/4/21 8:35 PM, Richard Henderson wrote:
> This fprintf+assert has been in place since the beginning.
> It is after to the fp_access_check, so we need to move the
> check up. Fold that in to the pairwise filter.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-a64.c | 82 +++++++++++++++++++++++---------------
> 1 file changed, 50 insertions(+), 32 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] target/arm: Decode fixes for aarch64
2021-06-04 18:35 [PATCH 0/3] target/arm: Decode fixes for aarch64 Richard Henderson
` (2 preceding siblings ...)
2021-06-04 18:35 ` [PATCH 3/3] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Richard Henderson
@ 2021-06-08 8:59 ` Peter Maydell
3 siblings, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2021-06-08 8:59 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Fri, 4 Jun 2021 at 19:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> A couple of printfs left over from the beginning of time,
> and asserts that are reachable because of lack of decode.
>
>
> r~
>
>
> Richard Henderson (3):
> target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
> target/arm: Remove fprintf from disas_simd_mod_imm
> target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
>
> target/arm/translate-a64.c | 87 +++++++++++++++++++++++---------------
> 1 file changed, 52 insertions(+), 35 deletions(-)
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread
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2021-06-06 18:45 ` Philippe Mathieu-Daudé
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