From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 23/33] tcg/tci: Split out tci_qemu_ld, tci_qemu_st
Date: Sat, 19 Jun 2021 11:14:42 -0700 [thread overview]
Message-ID: <20210619181452.877683-24-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210619181452.877683-1-richard.henderson@linaro.org>
We can share this code between 32-bit and 64-bit loads and stores.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 183 +++++++++++++++++++++---------------------------------
1 file changed, 71 insertions(+), 112 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 7103005889..5520537abe 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -317,6 +317,73 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
#define qemu_st_beq(X) \
cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+
+ switch (mop) {
+ case MO_UB:
+ return qemu_ld_ub;
+ case MO_SB:
+ return (int8_t)qemu_ld_ub;
+ case MO_LEUW:
+ return qemu_ld_leuw;
+ case MO_LESW:
+ return (int16_t)qemu_ld_leuw;
+ case MO_LEUL:
+ return qemu_ld_leul;
+ case MO_LESL:
+ return (int32_t)qemu_ld_leul;
+ case MO_LEQ:
+ return qemu_ld_leq;
+ case MO_BEUW:
+ return qemu_ld_beuw;
+ case MO_BESW:
+ return (int16_t)qemu_ld_beuw;
+ case MO_BEUL:
+ return qemu_ld_beul;
+ case MO_BESL:
+ return (int32_t)qemu_ld_beul;
+ case MO_BEQ:
+ return qemu_ld_beq;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+
+ switch (mop) {
+ case MO_UB:
+ qemu_st_b(val);
+ break;
+ case MO_LEUW:
+ qemu_st_lew(val);
+ break;
+ case MO_LEUL:
+ qemu_st_lel(val);
+ break;
+ case MO_LEQ:
+ qemu_st_leq(val);
+ break;
+ case MO_BEUW:
+ qemu_st_bew(val);
+ break;
+ case MO_BEUL:
+ qemu_st_bel(val);
+ break;
+ case MO_BEQ:
+ qemu_st_beq(val);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
#if TCG_TARGET_REG_BITS == 64
# define CASE_32_64(x) \
case glue(glue(INDEX_op_, x), _i64): \
@@ -909,34 +976,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp32 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp32 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp32 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp32 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp32 = qemu_ld_leul;
- break;
- case MO_BEUW:
- tmp32 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp32 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp32 = qemu_ld_beul;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
regs[r0] = tmp32;
break;
@@ -952,46 +992,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r3], regs[r2]);
oi = regs[r4];
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp64 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp64 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp64 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp64 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp64 = qemu_ld_leul;
- break;
- case MO_LESL:
- tmp64 = (int32_t)qemu_ld_leul;
- break;
- case MO_LEQ:
- tmp64 = qemu_ld_leq;
- break;
- case MO_BEUW:
- tmp64 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp64 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp64 = qemu_ld_beul;
- break;
- case MO_BESL:
- tmp64 = (int32_t)qemu_ld_beul;
- break;
- case MO_BEQ:
- tmp64 = qemu_ld_beq;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg64(regs, r1, r0, tmp64);
} else {
@@ -1008,25 +1009,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp32);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp32);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp32);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp32);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp32);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
break;
case INDEX_op_qemu_st_i64:
@@ -1045,31 +1028,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp64);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp64);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp64);
- break;
- case MO_LEQ:
- qemu_st_leq(tmp64);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp64);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp64);
- break;
- case MO_BEQ:
- qemu_st_beq(tmp64);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
break;
case INDEX_op_mb:
--
2.25.1
next prev parent reply other threads:[~2021-06-19 18:36 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-19 18:14 [PULL 00/33] tcg patch queue Richard Henderson
2021-06-19 18:14 ` [PULL 01/33] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
2021-06-19 18:14 ` [PULL 02/33] tcg: Add tcg_call_flags Richard Henderson
2021-06-19 18:14 ` [PULL 03/33] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
2021-06-19 18:14 ` [PULL 04/33] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
2021-06-19 18:14 ` [PULL 05/33] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
2021-06-19 18:14 ` [PULL 06/33] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
2021-06-19 18:14 ` [PULL 07/33] tcg: Add tcg_call_func Richard Henderson
2021-06-19 18:14 ` [PULL 08/33] tcg: Build ffi data structures for helpers Richard Henderson
2021-06-19 18:14 ` [PULL 09/33] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-06-19 18:14 ` [PULL 10/33] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-06-19 18:14 ` [PULL 11/33] tcg/tci: Use ffi for calls Richard Henderson
2021-06-19 18:14 ` [PULL 12/33] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-06-19 18:14 ` [PULL 13/33] tcg/tci: Emit setcond before brcond Richard Henderson
2021-06-19 18:14 ` [PULL 14/33] tcg/tci: Remove tci_write_reg Richard Henderson
2021-06-19 18:14 ` [PULL 15/33] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-06-19 18:14 ` [PULL 16/33] tcg/tci: Implement goto_ptr Richard Henderson
2021-06-19 18:14 ` [PULL 17/33] tcg/tci: Implement movcond Richard Henderson
2021-06-19 18:14 ` [PULL 18/33] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-06-19 18:14 ` [PULL 19/33] tcg/tci: Implement extract, sextract Richard Henderson
2021-06-19 18:14 ` [PULL 20/33] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-06-19 18:14 ` [PULL 21/33] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-06-19 18:14 ` [PULL 22/33] tcg/tci: Implement add2, sub2 Richard Henderson
2021-06-19 18:14 ` Richard Henderson [this message]
2021-06-19 18:14 ` [PULL 24/33] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces" Richard Henderson
2021-06-19 18:14 ` [PULL 25/33] tcg/tci: Remove the qemu_ld/st_type macros Richard Henderson
2021-06-19 18:14 ` [PULL 26/33] tcg/tci: Use {set,clear}_helper_retaddr Richard Henderson
2021-06-19 18:14 ` [PULL 27/33] tests/tcg: Increase timeout for TCI Richard Henderson
2021-06-19 18:14 ` [PULL 28/33] accel/tcg: Probe the proper permissions for atomic ops Richard Henderson
2021-06-19 18:14 ` [PULL 29/33] tcg/sparc: Fix temp_allocate_frame vs sparc stack bias Richard Henderson
2021-06-19 18:14 ` [PULL 30/33] tcg: Allocate sufficient storage in temp_allocate_frame Richard Henderson
2021-09-01 10:52 ` Richard W.M. Jones
2021-09-01 12:55 ` Daniel P. Berrangé
2021-06-19 18:14 ` [PULL 31/33] tcg: Restart when exhausting the stack frame Richard Henderson
2021-06-19 18:14 ` [PULL 32/33] tcg: expose TCGCond manipulation routines Richard Henderson
2021-06-19 18:14 ` [PULL 33/33] util/oslib-win32: Fix fatal assertion in qemu_try_memalign Richard Henderson
2021-06-19 21:50 ` [PULL 00/33] tcg patch queue Richard Henderson
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