From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH for-6.2 15/34] target/arm: Implement MVE integer vector-vs-scalar comparisons
Date: Tue, 13 Jul 2021 14:37:07 +0100 [thread overview]
Message-ID: <20210713133726.26842-16-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210713133726.26842-1-peter.maydell@linaro.org>
Implement the MVE integer vector comparison instructions that compare
each element against a scalar from a general purpose register. These
are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)"
encodings T4, T5 and T6.
We have to move the decodetree pattern for VPST, because it
overlaps with VCMP T4 with size = 0b11.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 32 +++++++++++++++++++++++++++
target/arm/mve.decode | 18 +++++++++++++---
target/arm/mve_helper.c | 44 +++++++++++++++++++++++++++++++-------
target/arm/translate-mve.c | 43 +++++++++++++++++++++++++++++++++++++
4 files changed, 126 insertions(+), 11 deletions(-)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index e89238eac9d..035779b0576 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -516,3 +516,35 @@ DEF_HELPER_FLAGS_3(mve_vcmpgtw, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vcmpleb, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vcmplew, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmpne_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpne_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmphi_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmphi_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmphi_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmpge_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpge_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmplt_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmplt_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 76bbf9a6136..ef708ba80ff 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -38,6 +38,7 @@
&vidup qd rn size imm
&viwdup qd rn rm size imm
&vcmp qm qn size mask
+&vcmp_scalar qn rm size mask
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
# Note that both Rn and Qd are 3 bits only (no D bit)
@@ -90,6 +91,8 @@
# Vector comparison; 4-bit Qm but 3-bit Qn
%mask_22_13 22:1 13:3
@vcmp .... .... .. size:2 qn:3 . .... .... .... .... &vcmp qm=%qm mask=%mask_22_13
+@vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \
+ mask=%mask_22_13
# Vector loads and stores
@@ -349,9 +352,6 @@ VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
rdahi=%rdahi rdalo=%rdalo
}
-# Predicate operations
-VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
-
# Logical immediate operations (1 reg and modified-immediate)
# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
@@ -474,3 +474,15 @@ VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp
VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp
VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp
VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp
+
+{
+ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
+ VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_scalar
+}
+VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_scalar
+VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_scalar
+VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_scalar
+VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_scalar
+VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_scalar
+VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_scalar
+VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_scalar
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 23398e86f7d..57a92bc6841 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -1791,15 +1791,43 @@ DO_VIWDUP_ALL(vdwdup, do_sub_wrap)
mve_advance_vpt(env); \
}
-#define DO_VCMP_S(OP, FN) \
- DO_VCMP(OP##b, 1, int8_t, FN) \
- DO_VCMP(OP##h, 2, int16_t, FN) \
- DO_VCMP(OP##w, 4, int32_t, FN)
+#define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
+ uint32_t rm) \
+ { \
+ TYPE *n = vn; \
+ uint16_t mask = mve_element_mask(env); \
+ uint16_t eci_mask = mve_eci_mask(env); \
+ uint16_t beatpred = 0; \
+ uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \
+ unsigned e; \
+ for (e = 0; e < 16 / ESIZE; e++) { \
+ bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \
+ /* Comparison sets 0/1 bits for each byte in the element */ \
+ beatpred |= r * emask; \
+ emask <<= ESIZE; \
+ } \
+ beatpred &= mask; \
+ env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
+ (beatpred & eci_mask); \
+ mve_advance_vpt(env); \
+ }
-#define DO_VCMP_U(OP, FN) \
- DO_VCMP(OP##b, 1, uint8_t, FN) \
- DO_VCMP(OP##h, 2, uint16_t, FN) \
- DO_VCMP(OP##w, 4, uint32_t, FN)
+#define DO_VCMP_S(OP, FN) \
+ DO_VCMP(OP##b, 1, int8_t, FN) \
+ DO_VCMP(OP##h, 2, int16_t, FN) \
+ DO_VCMP(OP##w, 4, int32_t, FN) \
+ DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \
+ DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \
+ DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN)
+
+#define DO_VCMP_U(OP, FN) \
+ DO_VCMP(OP##b, 1, uint8_t, FN) \
+ DO_VCMP(OP##h, 2, uint16_t, FN) \
+ DO_VCMP(OP##w, 4, uint32_t, FN) \
+ DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \
+ DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \
+ DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN)
#define DO_EQ(N, M) ((N) == (M))
#define DO_NE(N, M) ((N) != (M))
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index a7334609e29..f8b8639eab7 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -44,6 +44,7 @@ typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
static inline long mve_qreg_offset(unsigned reg)
@@ -1207,6 +1208,37 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
return true;
}
+static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
+ MVEGenScalarCmpFn *fn)
+{
+ TCGv_ptr qn;
+ TCGv_i32 rm;
+
+ if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm == 13) {
+ return false;
+ }
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
+ return true;
+ }
+
+ qn = mve_qreg_ptr(a->qn);
+ if (a->rm == 15) {
+ /* Encoding Rm=0b1111 means "constant zero" */
+ rm = tcg_constant_i32(0);
+ } else {
+ rm = load_reg(s, a->rm);
+ }
+ fn(cpu_env, qn, rm);
+ tcg_temp_free_ptr(qn);
+ tcg_temp_free_i32(rm);
+ if (a->mask) {
+ /* VPT */
+ gen_vpst(s, a->mask);
+ }
+ mve_update_eci(s);
+ return true;
+}
+
#define DO_VCMP(INSN, FN) \
static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \
{ \
@@ -1217,6 +1249,17 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
NULL, \
}; \
return do_vcmp(s, a, fns[a->size]); \
+ } \
+ static bool trans_##INSN##_scalar(DisasContext *s, \
+ arg_vcmp_scalar *a) \
+ { \
+ static MVEGenScalarCmpFn * const fns[] = { \
+ gen_helper_mve_##FN##_scalarb, \
+ gen_helper_mve_##FN##_scalarh, \
+ gen_helper_mve_##FN##_scalarw, \
+ NULL, \
+ }; \
+ return do_vcmp_scalar(s, a, fns[a->size]); \
}
DO_VCMP(VCMPEQ, vcmpeq)
--
2.20.1
next prev parent reply other threads:[~2021-07-13 13:50 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 13:36 [PATCH for-6.2 00/34] target/arm: Third slice of MVE implementation Peter Maydell
2021-07-13 13:36 ` [PATCH for-6.2 01/34] target/arm: Note that we handle VMOVL as a special case of VSHLL Peter Maydell
2021-07-14 17:02 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 02/34] target/arm: Print MVE VPR in CPU dumps Peter Maydell
2021-07-15 1:34 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 03/34] target/arm: Fix MVE VSLI by 0 and VSRI by <dt> Peter Maydell
2021-07-16 16:27 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 04/34] target/arm: Fix signed VADDV Peter Maydell
2021-07-15 1:37 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 05/34] target/arm: Fix mask handling for MVE narrowing operations Peter Maydell
2021-07-16 16:29 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 06/34] target/arm: Fix 48-bit saturating shifts Peter Maydell
2021-07-16 16:34 ` Richard Henderson
2021-07-16 16:39 ` Peter Maydell
2021-07-13 13:36 ` [PATCH for-6.2 07/34] target/arm: Fix calculation of LTP mask when LR is 0 Peter Maydell
2021-07-16 16:35 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 08/34] target/arm: Fix VPT advance when ECI is non-zero Peter Maydell
2021-07-16 16:44 ` Richard Henderson
2021-07-16 16:58 ` Richard Henderson
2021-07-19 14:16 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 09/34] target/arm: Factor out mve_eci_mask() Peter Maydell
2021-07-16 16:48 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 10/34] target/arm: Fix VLDRB/H/W for predicated elements Peter Maydell
2021-07-16 16:58 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 11/34] target/arm: Implement MVE VMULL (polynomial) Peter Maydell
2021-07-16 17:14 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 12/34] target/arm: Implement MVE incrementing/decrementing dup insns Peter Maydell
2021-07-16 19:57 ` Richard Henderson
2021-07-19 14:25 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 13/34] target/arm: Factor out gen_vpst() Peter Maydell
2021-07-16 21:04 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 14/34] target/arm: Implement MVE integer vector comparisons Peter Maydell
2021-07-16 21:55 ` Richard Henderson
2021-07-13 13:37 ` Peter Maydell [this message]
2021-07-16 21:58 ` [PATCH for-6.2 15/34] target/arm: Implement MVE integer vector-vs-scalar comparisons Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 16/34] target/arm: Implement MVE VPSEL Peter Maydell
2021-07-16 22:03 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 17/34] target/arm: Implement MVE VMLAS Peter Maydell
2021-07-16 22:11 ` Richard Henderson
2021-07-17 10:06 ` Peter Maydell
2021-07-17 20:40 ` Richard Henderson
2021-07-20 10:13 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 18/34] target/arm: Implement MVE shift-by-scalar Peter Maydell
2021-07-16 22:15 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 19/34] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats Peter Maydell
2021-07-16 22:16 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 20/34] target/arm: Implement MVE integer min/max across vector Peter Maydell
2021-07-17 20:46 ` Richard Henderson
2021-07-19 15:28 ` Peter Maydell
2021-07-20 18:21 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 21/34] target/arm: Implement MVE VABAV Peter Maydell
2021-07-17 20:50 ` Richard Henderson
2021-07-17 22:13 ` Peter Maydell
2021-07-17 22:18 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 22/34] target/arm: Implement MVE narrowing moves Peter Maydell
2021-07-21 21:45 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 23/34] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn Peter Maydell
2021-07-21 21:45 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 24/34] target/arm: Implement MVE VMLADAV and VMLSLDAV Peter Maydell
2021-07-21 22:01 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 25/34] target/arm: Implement MVE VMLA Peter Maydell
2021-07-21 22:03 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 26/34] target/arm: Implement MVE saturating doubling multiply accumulates Peter Maydell
2021-07-21 22:07 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 27/34] target/arm: Implement MVE VQABS, VQNEG Peter Maydell
2021-07-21 22:09 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 28/34] target/arm: Implement MVE VMAXA, VMINA Peter Maydell
2021-07-21 22:12 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 29/34] target/arm: Implement MVE VMOV to/from 2 general-purpose registers Peter Maydell
2021-07-21 22:20 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 30/34] target/arm: Implement MVE VPNOT Peter Maydell
2021-07-21 22:24 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 31/34] target/arm: Implement MVE VCTP Peter Maydell
2021-07-21 22:33 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 32/34] target/arm: Implement MVE scatter-gather insns Peter Maydell
2021-07-22 0:36 ` Richard Henderson
2021-07-22 8:42 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 33/34] target/arm: Implement MVE scatter-gather immediate forms Peter Maydell
2021-07-22 0:49 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 34/34] target/arm: Implement MVE interleaving loads/stores Peter Maydell
2021-07-22 17:52 ` Richard Henderson
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