From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH for-6.2 28/34] target/arm: Implement MVE VMAXA, VMINA
Date: Tue, 13 Jul 2021 14:37:20 +0100 [thread overview]
Message-ID: <20210713133726.26842-29-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210713133726.26842-1-peter.maydell@linaro.org>
Implement the MVE VMAXA and VMINA insns, which take the absolute
value of the signed elements in the input vector and then accumulate
the unsigned max or min into the destination vector.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 4 ++++
target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++
target/arm/translate-mve.c | 2 ++
4 files changed, 40 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 69f0474f6a3..c36640e75e9 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -88,6 +88,14 @@ DEF_HELPER_FLAGS_3(mve_vqnegb, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vqnegh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vqnegw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vmaxab, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vmaxah, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vmaxaw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vminab, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vminah, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vminaw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 1d38dd8dba3..3899937f033 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -156,6 +156,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
VQMOVUNB 111 0 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op
VQMOVN_BS 111 0 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op
+ VMAXA 111 0 1110 0 . 11 .. 11 ... 0 1110 1 0 . 0 ... 1 @1op
+
VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
}
@@ -176,6 +178,8 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
VQMOVUNT 111 0 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op
VQMOVN_TS 111 0 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op
+ VMINA 111 0 1110 0 . 11 .. 11 ... 1 1110 1 0 . 0 ... 1 @1op
+
VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
}
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 3b3695885ef..40e652229d6 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -2250,3 +2250,29 @@ DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W)
DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B)
DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H)
DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W)
+
+/*
+ * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its
+ * absolute value; we then do an unsigned comparison.
+ */
+#define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \
+ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
+ { \
+ UTYPE *d = vd; \
+ STYPE *m = vm; \
+ uint16_t mask = mve_element_mask(env); \
+ unsigned e; \
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
+ UTYPE r = DO_ABS(m[H##ESIZE(e)]); \
+ r = FN(d[H##ESIZE(e)], r); \
+ mergemask(&d[H##ESIZE(e)], r, mask); \
+ } \
+ mve_advance_vpt(env); \
+ }
+
+DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX)
+DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX)
+DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX)
+DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN)
+DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN)
+DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 59e09f58a8c..f243c34bd21 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -277,6 +277,8 @@ DO_1OP(VABS, vabs)
DO_1OP(VNEG, vneg)
DO_1OP(VQABS, vqabs)
DO_1OP(VQNEG, vqneg)
+DO_1OP(VMAXA, vmaxa)
+DO_1OP(VMINA, vmina)
/* Narrowing moves: only size 0 and 1 are valid */
#define DO_VMOVN(INSN, FN) \
--
2.20.1
next prev parent reply other threads:[~2021-07-13 13:57 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 13:36 [PATCH for-6.2 00/34] target/arm: Third slice of MVE implementation Peter Maydell
2021-07-13 13:36 ` [PATCH for-6.2 01/34] target/arm: Note that we handle VMOVL as a special case of VSHLL Peter Maydell
2021-07-14 17:02 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 02/34] target/arm: Print MVE VPR in CPU dumps Peter Maydell
2021-07-15 1:34 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 03/34] target/arm: Fix MVE VSLI by 0 and VSRI by <dt> Peter Maydell
2021-07-16 16:27 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 04/34] target/arm: Fix signed VADDV Peter Maydell
2021-07-15 1:37 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 05/34] target/arm: Fix mask handling for MVE narrowing operations Peter Maydell
2021-07-16 16:29 ` Richard Henderson
2021-07-13 13:36 ` [PATCH for-6.2 06/34] target/arm: Fix 48-bit saturating shifts Peter Maydell
2021-07-16 16:34 ` Richard Henderson
2021-07-16 16:39 ` Peter Maydell
2021-07-13 13:36 ` [PATCH for-6.2 07/34] target/arm: Fix calculation of LTP mask when LR is 0 Peter Maydell
2021-07-16 16:35 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 08/34] target/arm: Fix VPT advance when ECI is non-zero Peter Maydell
2021-07-16 16:44 ` Richard Henderson
2021-07-16 16:58 ` Richard Henderson
2021-07-19 14:16 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 09/34] target/arm: Factor out mve_eci_mask() Peter Maydell
2021-07-16 16:48 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 10/34] target/arm: Fix VLDRB/H/W for predicated elements Peter Maydell
2021-07-16 16:58 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 11/34] target/arm: Implement MVE VMULL (polynomial) Peter Maydell
2021-07-16 17:14 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 12/34] target/arm: Implement MVE incrementing/decrementing dup insns Peter Maydell
2021-07-16 19:57 ` Richard Henderson
2021-07-19 14:25 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 13/34] target/arm: Factor out gen_vpst() Peter Maydell
2021-07-16 21:04 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 14/34] target/arm: Implement MVE integer vector comparisons Peter Maydell
2021-07-16 21:55 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 15/34] target/arm: Implement MVE integer vector-vs-scalar comparisons Peter Maydell
2021-07-16 21:58 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 16/34] target/arm: Implement MVE VPSEL Peter Maydell
2021-07-16 22:03 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 17/34] target/arm: Implement MVE VMLAS Peter Maydell
2021-07-16 22:11 ` Richard Henderson
2021-07-17 10:06 ` Peter Maydell
2021-07-17 20:40 ` Richard Henderson
2021-07-20 10:13 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 18/34] target/arm: Implement MVE shift-by-scalar Peter Maydell
2021-07-16 22:15 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 19/34] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats Peter Maydell
2021-07-16 22:16 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 20/34] target/arm: Implement MVE integer min/max across vector Peter Maydell
2021-07-17 20:46 ` Richard Henderson
2021-07-19 15:28 ` Peter Maydell
2021-07-20 18:21 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 21/34] target/arm: Implement MVE VABAV Peter Maydell
2021-07-17 20:50 ` Richard Henderson
2021-07-17 22:13 ` Peter Maydell
2021-07-17 22:18 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 22/34] target/arm: Implement MVE narrowing moves Peter Maydell
2021-07-21 21:45 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 23/34] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn Peter Maydell
2021-07-21 21:45 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 24/34] target/arm: Implement MVE VMLADAV and VMLSLDAV Peter Maydell
2021-07-21 22:01 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 25/34] target/arm: Implement MVE VMLA Peter Maydell
2021-07-21 22:03 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 26/34] target/arm: Implement MVE saturating doubling multiply accumulates Peter Maydell
2021-07-21 22:07 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 27/34] target/arm: Implement MVE VQABS, VQNEG Peter Maydell
2021-07-21 22:09 ` Richard Henderson
2021-07-13 13:37 ` Peter Maydell [this message]
2021-07-21 22:12 ` [PATCH for-6.2 28/34] target/arm: Implement MVE VMAXA, VMINA Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 29/34] target/arm: Implement MVE VMOV to/from 2 general-purpose registers Peter Maydell
2021-07-21 22:20 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 30/34] target/arm: Implement MVE VPNOT Peter Maydell
2021-07-21 22:24 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 31/34] target/arm: Implement MVE VCTP Peter Maydell
2021-07-21 22:33 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 32/34] target/arm: Implement MVE scatter-gather insns Peter Maydell
2021-07-22 0:36 ` Richard Henderson
2021-07-22 8:42 ` Peter Maydell
2021-07-13 13:37 ` [PATCH for-6.2 33/34] target/arm: Implement MVE scatter-gather immediate forms Peter Maydell
2021-07-22 0:49 ` Richard Henderson
2021-07-13 13:37 ` [PATCH for-6.2 34/34] target/arm: Implement MVE interleaving loads/stores Peter Maydell
2021-07-22 17:52 ` Richard Henderson
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