* [PULL 0/9] tcg patch queue
@ 2021-09-12 15:58 Richard Henderson
2021-09-12 15:58 ` [PULL 1/9] accel/tcg: Add DisasContextBase argument to translator_ld* Richard Henderson
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Note that I've extended the expiration date of my gpg key
and have uploaded it to keyserver.ubuntu.com.
r~
The following changes since commit 99c44988d5ba1866a411450c877ed818b1b70081:
Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210910' into staging (2021-09-11 14:00:39 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210912
for you to fetch changes up to 267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118:
tcg/arm: Fix tcg_out_vec_op function signature (2021-09-12 05:07:36 -0700)
----------------------------------------------------------------
Fix translation race condition for user-only.
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
Fix tcg/arm tcg_out_vec_op signature.
Fix tcg/ppc (32bit) build with clang.
Remove dupluate TCG_KICK_PERIOD definition.
Remove unused tcg_global_reg_new.
Use __builtin_bswap*.
----------------------------------------------------------------
Bin Meng (1):
tcg: Remove tcg_global_reg_new defines
Ilya Leoshkevich (2):
accel/tcg: Add DisasContextBase argument to translator_ld*
accel/tcg: Clear PAGE_WRITE before translation
Jose R. Ziviani (1):
tcg/arm: Fix tcg_out_vec_op function signature
Luc Michel (1):
accel/tcg: remove redundant TCG_KICK_PERIOD define
Richard Henderson (4):
tcg/i386: Split P_VEXW from P_REXW
include/qemu: Use builtins for bswap
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
meson.build | 6 ----
include/exec/translate-all.h | 1 +
include/exec/translator.h | 44 +++++++++++++----------
include/qemu/bswap.h | 53 ++-------------------------
include/tcg/tcg-op.h | 2 --
target/arm/arm_ldst.h | 12 +++----
accel/tcg/tcg-accel-ops-rr.c | 2 --
accel/tcg/translate-all.c | 59 ++++++++++++++++++-------------
accel/tcg/translator.c | 39 ++++++++++++++++++++
target/alpha/translate.c | 2 +-
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 9 ++---
target/hexagon/translate.c | 3 +-
target/hppa/translate.c | 5 +--
target/i386/tcg/translate.c | 10 +++---
target/m68k/translate.c | 2 +-
target/mips/tcg/translate.c | 8 ++---
target/openrisc/translate.c | 2 +-
target/ppc/translate.c | 5 +--
target/riscv/translate.c | 5 +--
target/s390x/tcg/translate.c | 16 +++++----
target/sh4/translate.c | 4 +--
target/sparc/translate.c | 2 +-
target/xtensa/translate.c | 5 +--
target/mips/tcg/micromips_translate.c.inc | 2 +-
target/mips/tcg/mips16e_translate.c.inc | 4 +--
target/mips/tcg/nanomips_translate.c.inc | 4 +--
tcg/arm/tcg-target.c.inc | 3 +-
tcg/i386/tcg-target.c.inc | 13 +++----
tcg/ppc/tcg-target.c.inc | 25 ++++++++++---
30 files changed, 185 insertions(+), 164 deletions(-)
^ permalink raw reply [flat|nested] 11+ messages in thread* [PULL 1/9] accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 2/9] accel/tcg: Clear PAGE_WRITE before translation Richard Henderson ` (8 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Ilya Leoshkevich From: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/exec/translator.h | 9 +++++---- target/arm/arm_ldst.h | 12 ++++++------ target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 9 +++++---- target/hexagon/translate.c | 3 ++- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 10 +++++----- target/m68k/translate.c | 2 +- target/mips/tcg/translate.c | 8 ++++---- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 5 +++-- target/riscv/translate.c | 5 +++-- target/s390x/tcg/translate.c | 16 +++++++++------- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 2 +- target/xtensa/translate.c | 5 +++-- target/mips/tcg/micromips_translate.c.inc | 2 +- target/mips/tcg/mips16e_translate.c.inc | 4 ++-- target/mips/tcg/nanomips_translate.c.inc | 4 ++-- 20 files changed, 58 insertions(+), 50 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index d318803267..6c054e8d05 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -157,7 +157,8 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ static inline type \ - fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \ + fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap) \ { \ type ret = load_fn(env, pc); \ if (do_swap) { \ @@ -166,10 +167,10 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); plugin_insn_append(&ret, sizeof(ret)); \ return ret; \ } \ - \ - static inline type fullname(CPUArchState *env, abi_ptr pc) \ + static inline type fullname(CPUArchState *env, \ + DisasContextBase *dcbase, abi_ptr pc) \ { \ - return fullname ## _swap(env, pc, false); \ + return fullname ## _swap(env, dcbase, pc, false); \ } GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h index 057160e8da..cee0548a1c 100644 --- a/target/arm/arm_ldst.h +++ b/target/arm/arm_ldst.h @@ -24,15 +24,15 @@ #include "qemu/bswap.h" /* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, - bool sctlr_b) +static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, + target_ulong addr, bool sctlr_b) { - return translator_ldl_swap(env, addr, bswap_code(sctlr_b)); + return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b)); } /* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, - bool sctlr_b) +static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, + target_ulong addr, bool sctlr_b) { #ifndef CONFIG_USER_ONLY /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped @@ -41,7 +41,7 @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, addr ^= 2; } #endif - return translator_lduw_swap(env, addr, bswap_code(sctlr_b)); + return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b)); } #endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index de6c0a8439..b034206688 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUAlphaState *env = cpu->env_ptr; - uint32_t insn = translator_ldl(env, ctx->base.pc_next); + uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); ctx->base.pc_next += 4; ctx->base.is_jmp = translate_one(ctx, insn); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422e2ac0c9..a52949b1f3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14655,7 +14655,7 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) uint32_t insn; s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b); + insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); s->insn = insn; s->base.pc_next += 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 24b7f49d76..422fca353d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9302,7 +9302,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) * boundary, so we cross the page if the first 16 bits indicate * that this is a 32 bit insn. */ - uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b); + uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b); return !thumb_insn_is_16bit(s, s->base.pc_next, insn); } @@ -9540,7 +9540,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b); + insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); dc->insn = insn; dc->base.pc_next += 4; disas_arm_insn(dc, insn); @@ -9610,11 +9610,12 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->pc_curr = dc->base.pc_next; - insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); + insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); dc->base.pc_next += 2; if (!is_16bit) { - uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b); + uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, + dc->sctlr_b); insn = insn << 16 | insn2; dc->base.pc_next += 2; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 54fdcaa5e8..6fb4e6853c 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -112,7 +112,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { words[nwords] = - translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t)); + translator_ldl(env, &ctx->base, + ctx->base.pc_next + nwords * sizeof(uint32_t)); found_end = is_packet_end(words[nwords]); } if (!found_end) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b18150ef8d..3ce22cdd09 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4177,7 +4177,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn = translator_ldl(env, ctx->base.pc_next); + uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index aacb605eee..a46be75b00 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2028,28 +2028,28 @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes) static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s) { - return translator_ldub(env, advance_pc(env, s, 1)); + return translator_ldub(env, &s->base, advance_pc(env, s, 1)); } static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s) { - return translator_ldsw(env, advance_pc(env, s, 2)); + return translator_ldsw(env, &s->base, advance_pc(env, s, 2)); } static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s) { - return translator_lduw(env, advance_pc(env, s, 2)); + return translator_lduw(env, &s->base, advance_pc(env, s, 2)); } static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s) { - return translator_ldl(env, advance_pc(env, s, 4)); + return translator_ldl(env, &s->base, advance_pc(env, s, 4)); } #ifdef TARGET_X86_64 static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s) { - return translator_ldq(env, advance_pc(env, s, 8)); + return translator_ldq(env, &s->base, advance_pc(env, s, 8)); } #endif diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c34d9aed61..50a55f949c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -415,7 +415,7 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) { uint16_t im; - im = translator_lduw(env, s->pc); + im = translator_lduw(env, &s->base, s->pc); s->pc += 2; return im; } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6f4a9a839c..148afec9dc 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16041,17 +16041,17 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) is_slot = ctx->hflags & MIPS_HFLAG_BMASK; if (ctx->insn_flags & ISA_NANOMIPS32) { - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); insn_bytes = decode_isa_nanomips(env, ctx); } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { - ctx->opcode = translator_ldl(env, ctx->base.pc_next); + ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); insn_bytes = 4; decode_opc(env, ctx); } else if (ctx->insn_flags & ASE_MICROMIPS) { - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); insn_bytes = decode_isa_micromips(env, ctx); } else if (ctx->insn_flags & ASE_MIPS16) { - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); insn_bytes = decode_ase_mips16e(env, ctx); } else { gen_reserved_instruction(ctx); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d6ea536744..5f3d430245 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1613,7 +1613,7 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); OpenRISCCPU *cpu = OPENRISC_CPU(cs); - uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next); + uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next); if (!decode(dc, insn)) { gen_illegal_exception(dc); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..5d8b06bd80 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8585,7 +8585,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); ctx->cia = pc = ctx->base.pc_next; - insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); + insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); ctx->base.pc_next = pc += 4; if (!is_prefix_insn(ctx, insn)) { @@ -8600,7 +8600,8 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); ok = true; } else { - uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); + uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, + need_byteswap(ctx)); ctx->base.pc_next = pc += 4; ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..74b33fa3c9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -500,7 +500,8 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) } else { uint32_t opcode32 = opcode; opcode32 = deposit32(opcode32, 16, 16, - translator_lduw(env, ctx->base.pc_next + 2)); + translator_lduw(env, &ctx->base, + ctx->base.pc_next + 2)); ctx->pc_succ_insn = ctx->base.pc_next + 4; if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); @@ -561,7 +562,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cpu->env_ptr; - uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); + uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0632b0374b..f284870cd2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -388,14 +388,16 @@ static void update_cc_op(DisasContext *s) } } -static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc) +static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s, + uint64_t pc) { - return (uint64_t)cpu_lduw_code(env, pc); + return (uint64_t)translator_lduw(env, &s->base, pc); } -static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc) +static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s, + uint64_t pc) { - return (uint64_t)(uint32_t)cpu_ldl_code(env, pc); + return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); } static int get_mem_index(DisasContext *s) @@ -6273,7 +6275,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) ilen = s->ex_value & 0xf; op = insn >> 56; } else { - insn = ld_code2(env, pc); + insn = ld_code2(env, s, pc); op = (insn >> 8) & 0xff; ilen = get_ilen(op); switch (ilen) { @@ -6281,10 +6283,10 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) insn = insn << 48; break; case 4: - insn = ld_code4(env, pc) << 32; + insn = ld_code4(env, s, pc) << 32; break; case 6: - insn = (insn << 48) | (ld_code4(env, pc + 2) << 16); + insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16); break; default: g_assert_not_reached(); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8704fea1ca..cf5fe9243d 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1907,7 +1907,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) /* Read all of the insns for the region. */ for (i = 0; i < max_insns; ++i) { - insns[i] = translator_lduw(env, pc + i * 2); + insns[i] = translator_lduw(env, &ctx->base, pc + i * 2); } ld_adr = ld_dst = ld_mop = -1; @@ -2307,7 +2307,7 @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } #endif - ctx->opcode = translator_lduw(env, ctx->base.pc_next); + ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next += 2; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bb70ba17de..fdb8bbe5dc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5855,7 +5855,7 @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) CPUSPARCState *env = cs->env_ptr; unsigned int insn; - insn = translator_ldl(env, dc->pc); + insn = translator_ldl(env, &dc->base, dc->pc); dc->base.pc_next += 4; disas_sparc_insn(dc, insn); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 20399d6a04..dcf6b500ef 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -882,7 +882,8 @@ static int arg_copy_compare(const void *a, const void *b) static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { xtensa_isa isa = dc->config->isa; - unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)}; + unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base, + dc->pc)}; unsigned len = xtensa_op0_insn_len(dc, b[0]); xtensa_format fmt; int slot, slots; @@ -907,7 +908,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) dc->base.pc_next = dc->pc + len; for (i = 1; i < len; ++i) { - b[i] = translator_ldub(env, dc->pc + i); + b[i] = translator_ldub(env, &dc->base, dc->pc + i); } xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); fmt = xtensa_format_decode(isa, dc->insnbuf); diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 5e95f47854..0da4c802a3 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -1627,7 +1627,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; - insn = translator_lduw(env, ctx->base.pc_next + 2); + insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = (ctx->opcode >> 21) & 0x1f; diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index 54071813f1..84d816603a 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -455,7 +455,7 @@ static void decode_i64_mips16(DisasContext *ctx, static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { - int extend = translator_lduw(env, ctx->base.pc_next + 2); + int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; int16_t imm, offset; @@ -688,7 +688,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) /* No delay slot, so just process as a normal instruction */ break; case M16_OPC_JAL: - offset = translator_lduw(env, ctx->base.pc_next + 2); + offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); offset = (((ctx->opcode & 0x1f) << 21) | ((ctx->opcode >> 5) & 0x1f) << 16 | offset) << 2; diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index a66ae26796..ccbcecad09 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -3656,7 +3656,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) int offset; int imm; - insn = translator_lduw(env, ctx->base.pc_next + 2); + insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); ctx->opcode = (ctx->opcode << 16) | insn; rt = extract32(ctx->opcode, 21, 5); @@ -3775,7 +3775,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_P48I: { - insn = translator_lduw(env, ctx->base.pc_next + 4); + insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4); target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; switch (extract32(ctx->opcode, 16, 5)) { case NM_LI48: -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 2/9] accel/tcg: Clear PAGE_WRITE before translation 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson 2021-09-12 15:58 ` [PULL 1/9] accel/tcg: Add DisasContextBase argument to translator_ld* Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 3/9] tcg/i386: Split P_VEXW from P_REXW Richard Henderson ` (7 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Ilya Leoshkevich From: Ilya Leoshkevich <iii@linux.ibm.com> translate_insn() implementations fetch instruction bytes piecemeal, which can cause qemu-user to generate inconsistent translations if another thread modifies them concurrently [1]. Fix by making pages containing translated instruction non-writable right before loading instruction bytes from them. [1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20210805204835.158918-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/exec/translate-all.h | 1 + include/exec/translator.h | 39 ++++++++++++++---------- accel/tcg/translate-all.c | 59 +++++++++++++++++++++--------------- accel/tcg/translator.c | 39 ++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 41 deletions(-) diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index a557b4e2bb..9f646389af 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -33,6 +33,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end); void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); #ifdef CONFIG_USER_ONLY +void page_protect(tb_page_addr_t page_addr); int page_unprotect(target_ulong address, uintptr_t pc); #endif diff --git a/include/exec/translator.h b/include/exec/translator.h index 6c054e8d05..9bc46eda59 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" +#include "exec/translate-all.h" #include "tcg/tcg.h" @@ -74,6 +75,17 @@ typedef struct DisasContextBase { int num_insns; int max_insns; bool singlestep_enabled; +#ifdef CONFIG_USER_ONLY + /* + * Guest address of the last byte of the last protected page. + * + * Pages containing the translated instructions are made non-writable in + * order to achieve consistency in case another thread is modifying the + * code while translate_insn() fetches the instruction bytes piecemeal. + * Such writer threads are blocked on mmap_lock() in page_unprotect(). + */ + target_ulong page_protect_end; +#endif } DisasContextBase; /** @@ -156,28 +168,23 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); */ #define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ - static inline type \ - fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ - abi_ptr pc, bool do_swap) \ - { \ - type ret = load_fn(env, pc); \ - if (do_swap) { \ - ret = swap_fn(ret); \ - } \ - plugin_insn_append(&ret, sizeof(ret)); \ - return ret; \ - } \ + type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap); \ static inline type fullname(CPUArchState *env, \ DisasContextBase *dcbase, abi_ptr pc) \ { \ return fullname ## _swap(env, dcbase, pc, false); \ } -GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) -GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) -GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16) -GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32) -GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64) +#define FOR_EACH_TRANSLATOR_LD(F) \ + F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \ + F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \ + F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \ + F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \ + F(translator_ldq, uint64_t, cpu_ldq_code, bswap64) + +FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD) + #undef GEN_TRANSLATOR_LD #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bbfcfb698c..fb9ebfad9e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1297,31 +1297,8 @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb, invalidate_page_bitmap(p); #if defined(CONFIG_USER_ONLY) - if (p->flags & PAGE_WRITE) { - target_ulong addr; - PageDesc *p2; - int prot; - - /* force the host page as non writable (writes will have a - page fault + mprotect overhead) */ - page_addr &= qemu_host_page_mask; - prot = 0; - for (addr = page_addr; addr < page_addr + qemu_host_page_size; - addr += TARGET_PAGE_SIZE) { - - p2 = page_find(addr >> TARGET_PAGE_BITS); - if (!p2) { - continue; - } - prot |= p2->flags; - p2->flags &= ~PAGE_WRITE; - } - mprotect(g2h_untagged(page_addr), qemu_host_page_size, - (prot & PAGE_BITS) & ~PAGE_WRITE); - if (DEBUG_TB_INVALIDATE_GATE) { - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); - } - } + /* translator_loop() must have made all TB pages non-writable */ + assert(!(p->flags & PAGE_WRITE)); #else /* if some code is already present, then the pages are already protected. So we handle the case where only the first TB is @@ -2394,6 +2371,38 @@ int page_check_range(target_ulong start, target_ulong len, int flags) return 0; } +void page_protect(tb_page_addr_t page_addr) +{ + target_ulong addr; + PageDesc *p; + int prot; + + p = page_find(page_addr >> TARGET_PAGE_BITS); + if (p && (p->flags & PAGE_WRITE)) { + /* + * Force the host page as non writable (writes will have a page fault + + * mprotect overhead). + */ + page_addr &= qemu_host_page_mask; + prot = 0; + for (addr = page_addr; addr < page_addr + qemu_host_page_size; + addr += TARGET_PAGE_SIZE) { + + p = page_find(addr >> TARGET_PAGE_BITS); + if (!p) { + continue; + } + prot |= p->flags; + p->flags &= ~PAGE_WRITE; + } + mprotect(g2h_untagged(page_addr), qemu_host_page_size, + (prot & PAGE_BITS) & ~PAGE_WRITE); + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); + } + } +} + /* called from signal handler: invalidate the code and unprotect the * page. Return 0 if the fault was not handled, 1 if it was handled, * and 2 if it was handled but the caller must cause the TB to be diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index c53a7f8e44..390bd9db0a 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -42,6 +42,15 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0; } +static inline void translator_page_protect(DisasContextBase *dcbase, + target_ulong pc) +{ +#ifdef CONFIG_USER_ONLY + dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK; + page_protect(pc); +#endif +} + void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { @@ -56,6 +65,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, db->num_insns = 0; db->max_insns = max_insns; db->singlestep_enabled = cflags & CF_SINGLE_STEP; + translator_page_protect(db, db->pc_next); ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ @@ -137,3 +147,32 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, } #endif } + +static inline void translator_maybe_page_protect(DisasContextBase *dcbase, + target_ulong pc, size_t len) +{ +#ifdef CONFIG_USER_ONLY + target_ulong end = pc + len - 1; + + if (end > dcbase->page_protect_end) { + translator_page_protect(dcbase, end); + } +#endif +} + +#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \ + type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \ + abi_ptr pc, bool do_swap) \ + { \ + translator_maybe_page_protect(dcbase, pc, sizeof(type)); \ + type ret = load_fn(env, pc); \ + if (do_swap) { \ + ret = swap_fn(ret); \ + } \ + plugin_insn_append(&ret, sizeof(ret)); \ + return ret; \ + } + +FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD) + +#undef GEN_TRANSLATOR_LD -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 3/9] tcg/i386: Split P_VEXW from P_REXW 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson 2021-09-12 15:58 ` [PULL 1/9] accel/tcg: Add DisasContextBase argument to translator_ld* Richard Henderson 2021-09-12 15:58 ` [PULL 2/9] accel/tcg: Clear PAGE_WRITE before translation Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 4/9] accel/tcg: remove redundant TCG_KICK_PERIOD define Richard Henderson ` (6 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell We need to be able to represent VEX.W on a 32-bit host, where REX.W will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ. Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/i386/tcg-target.c.inc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 98d924b91a..997510109d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -241,8 +241,9 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ +#define P_VEXW 0x1000 /* Set VEX.W = 1 */ #if TCG_TARGET_REG_BITS == 64 -# define P_REXW 0x1000 /* Set REX.W = 1 */ +# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */ # define P_REXB_R 0x2000 /* REG field as byte register */ # define P_REXB_RM 0x4000 /* R/M field as byte register */ # define P_GS 0x8000 /* gs segment override */ @@ -410,13 +411,13 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) -#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) +#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) -#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) -#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) @@ -576,7 +577,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, /* Use the two byte form if possible, which cannot encode VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ - if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT + if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT && ((rm | index) & 8) == 0) { /* Two byte VEX prefix. */ tcg_out8(s, 0xc5); @@ -601,7 +602,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */ tcg_out8(s, tmp); - tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */ } tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 4/9] accel/tcg: remove redundant TCG_KICK_PERIOD define 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (2 preceding siblings ...) 2021-09-12 15:58 ` [PULL 3/9] tcg/i386: Split P_VEXW from P_REXW Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 5/9] tcg: Remove tcg_global_reg_new defines Richard Henderson ` (5 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Luc Michel, Philippe Mathieu-Daudé From: Luc Michel <lmichel@kalray.eu> The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h. Remove it from tcg-accel-ops-rr.c. Signed-off-by: Luc Michel <lmichel@kalray.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210811141229.12470-1-lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- accel/tcg/tcg-accel-ops-rr.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index c02c061ecb..a5fd26190e 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -60,8 +60,6 @@ void rr_kick_vcpu_thread(CPUState *unused) static QEMUTimer *rr_kick_vcpu_timer; static CPUState *rr_current_cpu; -#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) - static inline int64_t rr_next_kick_time(void) { return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 5/9] tcg: Remove tcg_global_reg_new defines 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (3 preceding siblings ...) 2021-09-12 15:58 ` [PULL 4/9] accel/tcg: remove redundant TCG_KICK_PERIOD define Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 6/9] include/qemu: Use builtins for bswap Richard Henderson ` (4 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Bin Meng, Philippe Mathieu-Daudé From: Bin Meng <bmeng.cn@gmail.com> Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/tcg/tcg-op.h | 2 -- target/hppa/translate.c | 3 --- 2 files changed, 5 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 2a654f350c..0545a6224c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -843,7 +843,6 @@ static inline void tcg_gen_plugin_cb_end(void) #if TARGET_LONG_BITS == 32 #define tcg_temp_new() tcg_temp_new_i32() -#define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new() tcg_temp_local_new_i32() #define tcg_temp_free tcg_temp_free_i32 @@ -851,7 +850,6 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else #define tcg_temp_new() tcg_temp_new_i64() -#define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new() tcg_temp_local_new_i64() #define tcg_temp_free tcg_temp_free_i64 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ce22cdd09..c3698cf067 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -34,7 +34,6 @@ #undef TCGv #undef tcg_temp_new -#undef tcg_global_reg_new #undef tcg_global_mem_new #undef tcg_temp_local_new #undef tcg_temp_free @@ -59,7 +58,6 @@ #define TCGv_reg TCGv_i64 #define tcg_temp_new tcg_temp_new_i64 -#define tcg_global_reg_new tcg_global_reg_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new tcg_temp_local_new_i64 #define tcg_temp_free tcg_temp_free_i64 @@ -155,7 +153,6 @@ #else #define TCGv_reg TCGv_i32 #define tcg_temp_new tcg_temp_new_i32 -#define tcg_global_reg_new tcg_global_reg_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new tcg_temp_local_new_i32 #define tcg_temp_free tcg_temp_free_i32 -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 6/9] include/qemu: Use builtins for bswap 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (4 preceding siblings ...) 2021-09-12 15:58 ` [PULL 5/9] tcg: Remove tcg_global_reg_new defines Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 7/9] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN Richard Henderson ` (3 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé All supported compilers have builtins for this. Drop all of the complicated system detection stuff. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210708181743.750220-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- meson.build | 6 ----- include/qemu/bswap.h | 53 +++----------------------------------------- 2 files changed, 3 insertions(+), 56 deletions(-) diff --git a/meson.build b/meson.build index 9a64d16943..306797c604 100644 --- a/meson.build +++ b/meson.build @@ -1332,8 +1332,6 @@ config_host_data.set('HAVE_STRCHRNUL', cc.has_function('strchrnul')) config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include <stdlib.h>')) # has_header_symbol -config_host_data.set('CONFIG_BYTESWAP_H', - cc.has_header_symbol('byteswap.h', 'bswap_32')) config_host_data.set('CONFIG_EPOLL_CREATE1', cc.has_header_symbol('sys/epoll.h', 'epoll_create1')) config_host_data.set('CONFIG_HAS_ENVIRON', @@ -1353,10 +1351,6 @@ config_host_data.set('CONFIG_INOTIFY', cc.has_header_symbol('sys/inotify.h', 'inotify_init')) config_host_data.set('CONFIG_INOTIFY1', cc.has_header_symbol('sys/inotify.h', 'inotify_init1')) -config_host_data.set('CONFIG_MACHINE_BSWAP_H', - cc.has_header_symbol('machine/bswap.h', 'bswap32', - prefix: '''#include <sys/endian.h> - #include <sys/types.h>''')) config_host_data.set('CONFIG_PRCTL_PR_SET_TIMERSLACK', cc.has_header_symbol('sys/prctl.h', 'PR_SET_TIMERSLACK')) config_host_data.set('CONFIG_RTNETLINK', diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 2d3bb8bbed..9e12bd8073 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -1,73 +1,26 @@ #ifndef BSWAP_H #define BSWAP_H -#ifdef CONFIG_MACHINE_BSWAP_H -# include <sys/endian.h> -# include <machine/bswap.h> -#elif defined(__FreeBSD__) -# include <sys/endian.h> -#elif defined(__HAIKU__) -# include <endian.h> -#elif defined(CONFIG_BYTESWAP_H) -# include <byteswap.h> -#define BSWAP_FROM_BYTESWAP -# else -#define BSWAP_FROM_FALLBACKS -#endif /* ! CONFIG_MACHINE_BSWAP_H */ - #ifdef __cplusplus extern "C" { #endif #include "fpu/softfloat-types.h" -#ifdef BSWAP_FROM_BYTESWAP static inline uint16_t bswap16(uint16_t x) { - return bswap_16(x); + return __builtin_bswap16(x); } static inline uint32_t bswap32(uint32_t x) { - return bswap_32(x); + return __builtin_bswap32(x); } static inline uint64_t bswap64(uint64_t x) { - return bswap_64(x); + return __builtin_bswap64(x); } -#endif - -#ifdef BSWAP_FROM_FALLBACKS -static inline uint16_t bswap16(uint16_t x) -{ - return (((x & 0x00ff) << 8) | - ((x & 0xff00) >> 8)); -} - -static inline uint32_t bswap32(uint32_t x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | - ((x & 0xff000000U) >> 24)); -} - -static inline uint64_t bswap64(uint64_t x) -{ - return (((x & 0x00000000000000ffULL) << 56) | - ((x & 0x000000000000ff00ULL) << 40) | - ((x & 0x0000000000ff0000ULL) << 24) | - ((x & 0x00000000ff000000ULL) << 8) | - ((x & 0x000000ff00000000ULL) >> 8) | - ((x & 0x0000ff0000000000ULL) >> 24) | - ((x & 0x00ff000000000000ULL) >> 40) | - ((x & 0xff00000000000000ULL) >> 56)); -} -#endif - -#undef BSWAP_FROM_BYTESWAP -#undef BSWAP_FROM_FALLBACKS static inline void bswap16s(uint16_t *s) { -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 7/9] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (5 preceding siblings ...) 2021-09-12 15:58 ` [PULL 6/9] include/qemu: Use builtins for bswap Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 8/9] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF Richard Henderson ` (2 subsequent siblings) 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell If __APPLE__, ensure that _CALL_DARWIN is set, then remove our local TCG_TARGET_CALL_DARWIN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/ppc/tcg-target.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0f4665213..2202ce017e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -25,8 +25,8 @@ #include "elf.h" #include "../tcg-pool.c.inc" -#if defined _CALL_DARWIN || defined __APPLE__ -#define TCG_TARGET_CALL_DARWIN +#if !defined _CALL_DARWIN && defined __APPLE__ +#define _CALL_DARWIN 1 #endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 @@ -169,7 +169,7 @@ static const int tcg_target_call_oarg_regs[] = { }; static const int tcg_target_callee_save_regs[] = { -#ifdef TCG_TARGET_CALL_DARWIN +#ifdef _CALL_DARWIN TCG_REG_R11, #endif TCG_REG_R14, @@ -2372,7 +2372,7 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (1 * SZR) # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) -#elif defined(TCG_TARGET_CALL_DARWIN) +#elif defined(_CALL_DARWIN) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (2 * SZR) #elif TCG_TARGET_REG_BITS == 64 -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 8/9] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (6 preceding siblings ...) 2021-09-12 15:58 ` [PULL 7/9] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-12 15:58 ` [PULL 9/9] tcg/arm: Fix tcg_out_vec_op function signature Richard Henderson 2021-09-13 9:57 ` [PULL 0/9] tcg patch queue Peter Maydell 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Brad Smith Clang only sets _CALL_ELF for ppc64, and nothing at all to specify the ABI for ppc32. Make a good guess based on other symbols. Reported-by: Brad Smith <brad@comstyle.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/ppc/tcg-target.c.inc | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 2202ce017e..5e1fac914a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -25,9 +25,24 @@ #include "elf.h" #include "../tcg-pool.c.inc" -#if !defined _CALL_DARWIN && defined __APPLE__ -#define _CALL_DARWIN 1 -#endif +/* + * Standardize on the _CALL_FOO symbols used by GCC: + * Apple XCode does not define _CALL_DARWIN. + * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). + */ +#if !defined(_CALL_SYSV) && \ + !defined(_CALL_DARWIN) && \ + !defined(_CALL_AIX) && \ + !defined(_CALL_ELF) +# if defined(__APPLE__) +# define _CALL_DARWIN +# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32 +# define _CALL_SYSV +# else +# error "Unknown ABI" +# endif +#endif + #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ALIGN_ARGS 1 #endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PULL 9/9] tcg/arm: Fix tcg_out_vec_op function signature 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (7 preceding siblings ...) 2021-09-12 15:58 ` [PULL 8/9] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF Richard Henderson @ 2021-09-12 15:58 ` Richard Henderson 2021-09-13 9:57 ` [PULL 0/9] tcg patch queue Peter Maydell 9 siblings, 0 replies; 11+ messages in thread From: Richard Henderson @ 2021-09-12 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé, Jose R. Ziviani From: "Jose R. Ziviani" <jziviani@suse.de> Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op for arm is missing. It causes a build error on armv6 and armv7: tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *' {aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=] const TCGArg *args, const int *const_args) ~~~~~~~~~~~~~~^~~~ ../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]' {aka 'const unsigned int[16]'} const TCGArg args[TCG_MAX_OP_ARGS], ~~~~~~~~~~~~~~^~~~ Signed-off-by: Jose R. Ziviani <jziviani@suse.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210908185338.7927-1-jziviani@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/arm/tcg-target.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 007ceee68e..e5b4f86841 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2715,7 +2715,8 @@ static const ARMInsn vec_cmp0_insn[16] = { static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, - const TCGArg *args, const int *const_args) + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { TCGType type = vecl + TCG_TYPE_V64; unsigned q = vecl; -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PULL 0/9] tcg patch queue 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson ` (8 preceding siblings ...) 2021-09-12 15:58 ` [PULL 9/9] tcg/arm: Fix tcg_out_vec_op function signature Richard Henderson @ 2021-09-13 9:57 ` Peter Maydell 9 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2021-09-13 9:57 UTC (permalink / raw) To: Richard Henderson; +Cc: QEMU Developers On Sun, 12 Sept 2021 at 16:58, Richard Henderson <richard.henderson@linaro.org> wrote: > > Note that I've extended the expiration date of my gpg key > and have uploaded it to keyserver.ubuntu.com. > > > r~ > > > The following changes since commit 99c44988d5ba1866a411450c877ed818b1b70081: > > Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210910' into staging (2021-09-11 14:00:39 +0100) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210912 > > for you to fetch changes up to 267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118: > > tcg/arm: Fix tcg_out_vec_op function signature (2021-09-12 05:07:36 -0700) > > ---------------------------------------------------------------- > Fix translation race condition for user-only. > Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ. > Fix tcg/arm tcg_out_vec_op signature. > Fix tcg/ppc (32bit) build with clang. > Remove dupluate TCG_KICK_PERIOD definition. > Remove unused tcg_global_reg_new. > Use __builtin_bswap*. > Hi; this fails to build on NetBSD: In file included from /usr/include/stdarg.h:37:0, from /home/qemu/qemu-test.X505HZ/src/include/qemu/osdep.h:79, from ../src/tests/qtest/test-arm-mptimer.c:10: /home/qemu/qemu-test.X505HZ/src/include/qemu/bswap.h:10:24: error: expected declaration specifiers or '...' before '__builtin_constant_p' static inline uint16_t bswap16(uint16_t x) ^ /home/qemu/qemu-test.X505HZ/src/include/qemu/bswap.h:15:24: error: expected declaration specifiers or '...' before '__builtin_constant_p' static inline uint32_t bswap32(uint32_t x) ^ /home/qemu/qemu-test.X505HZ/src/include/qemu/bswap.h:20:24: error: expected declaration specifiers or '...' before '__builtin_constant_p' static inline uint64_t bswap64(uint64_t x) ^ and on FreeBSD: In file included from ../src/disas/nanomips.cpp:31: In file included from /usr/home/qemu/qemu-test.UUfQa1/src/include/disas/dis-asm.h:12: /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:10:24: error: unknown type name '__builtin_constant_p' static inline uint16_t bswap16(uint16_t x) ^ /usr/include/sys/endian.h:61:20: note: expanded from macro 'bswap16' #define bswap16(x) __bswap16(x) ^ /usr/include/x86/endian.h:76:16: note: expanded from macro '__bswap16' ((__uint16_t)(__builtin_constant_p(x) ? \ ^ In file included from ../src/disas/nanomips.cpp:31: In file included from /usr/home/qemu/qemu-test.UUfQa1/src/include/disas/dis-asm.h:12: /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:10:24: error: expected ')' /usr/include/sys/endian.h:61:20: note: expanded from macro 'bswap16' #define bswap16(x) __bswap16(x) ^ /usr/include/x86/endian.h:76:40: note: expanded from macro '__bswap16' ((__uint16_t)(__builtin_constant_p(x) ? \ ^ /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:10:24: note: to match this '(' /usr/include/sys/endian.h:61:20: note: expanded from macro 'bswap16' #define bswap16(x) __bswap16(x) ^ /usr/include/x86/endian.h:76:15: note: expanded from macro '__bswap16' ((__uint16_t)(__builtin_constant_p(x) ? \ ^ In file included from ../src/disas/nanomips.cpp:31: In file included from /usr/home/qemu/qemu-test.UUfQa1/src/include/disas/dis-asm.h:12: /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:12:30: error: use of undeclared identifier 'x' return __builtin_bswap16(x); ^ /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:15:24: error: expected ')' static inline uint32_t bswap32(uint32_t x) ^ /usr/include/sys/endian.h:62:20: note: expanded from macro 'bswap32' #define bswap32(x) __bswap32(x) ^ /usr/include/x86/endian.h:79:27: note: expanded from macro '__bswap32' (__builtin_constant_p(x) ? \ ^ /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:15:24: note: to match this '(' /usr/include/sys/endian.h:62:20: note: expanded from macro 'bswap32' #define bswap32(x) __bswap32(x) ^ /usr/include/x86/endian.h:79:2: note: expanded from macro '__bswap32' (__builtin_constant_p(x) ? \ ^ In file included from ../src/disas/nanomips.cpp:31: In file included from /usr/home/qemu/qemu-test.UUfQa1/src/include/disas/dis-asm.h:12: /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:15:24: error: cannot redeclare builtin function '__builtin_constant_p' static inline uint32_t bswap32(uint32_t x) ^ /usr/include/sys/endian.h:62:20: note: expanded from macro 'bswap32' #define bswap32(x) __bswap32(x) ^ /usr/include/x86/endian.h:79:3: note: expanded from macro '__bswap32' (__builtin_constant_p(x) ? \ ^ /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:10:24: note: '__builtin_constant_p' is a builtin with type 'int (...) noexcept' static inline uint16_t bswap16(uint16_t x) ^ /usr/include/sys/endian.h:61:20: note: expanded from macro 'bswap16' #define bswap16(x) __bswap16(x) ^ /usr/include/x86/endian.h:76:16: note: expanded from macro '__bswap16' ((__uint16_t)(__builtin_constant_p(x) ? \ ^ In file included from ../src/disas/nanomips.cpp:31: In file included from /usr/home/qemu/qemu-test.UUfQa1/src/include/disas/dis-asm.h:12: /usr/home/qemu/qemu-test.UUfQa1/src/include/qemu/bswap.h:15:24: error: definition of builtin function '__builtin_constant_p' static inline uint32_t bswap32(uint32_t x) ^ /usr/include/sys/endian.h:62:20: note: expanded from macro 'bswap32' #define bswap32(x) __bswap32(x) ^ /usr/include/x86/endian.h:79:3: note: expanded from macro '__bswap32' (__builtin_constant_p(x) ? \ ^ [etc etc] thanks -- PMM ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-09-13 10:11 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-12 15:58 [PULL 0/9] tcg patch queue Richard Henderson 2021-09-12 15:58 ` [PULL 1/9] accel/tcg: Add DisasContextBase argument to translator_ld* Richard Henderson 2021-09-12 15:58 ` [PULL 2/9] accel/tcg: Clear PAGE_WRITE before translation Richard Henderson 2021-09-12 15:58 ` [PULL 3/9] tcg/i386: Split P_VEXW from P_REXW Richard Henderson 2021-09-12 15:58 ` [PULL 4/9] accel/tcg: remove redundant TCG_KICK_PERIOD define Richard Henderson 2021-09-12 15:58 ` [PULL 5/9] tcg: Remove tcg_global_reg_new defines Richard Henderson 2021-09-12 15:58 ` [PULL 6/9] include/qemu: Use builtins for bswap Richard Henderson 2021-09-12 15:58 ` [PULL 7/9] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN Richard Henderson 2021-09-12 15:58 ` [PULL 8/9] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF Richard Henderson 2021-09-12 15:58 ` [PULL 9/9] tcg/arm: Fix tcg_out_vec_op function signature Richard Henderson 2021-09-13 9:57 ` [PULL 0/9] tcg patch queue Peter Maydell
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