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From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Laurent Vivier" <laurent@vivier.eu>
Subject: [PATCH v4 15/30] tcg/loongarch64: Implement clz/ctz ops
Date: Fri, 24 Sep 2021 00:59:24 +0800	[thread overview]
Message-ID: <20210923165939.729081-16-git@xen0n.name> (raw)
In-Reply-To: <20210923165939.729081-1-git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target-con-set.h |  1 +
 tcg/loongarch64/tcg-target.c.inc     | 42 ++++++++++++++++++++++++++++
 tcg/loongarch64/tcg-target.h         |  8 +++---
 3 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index d958183020..2975e03127 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -18,4 +18,5 @@ C_O0_I1(r)
 C_O1_I1(r, r)
 C_O1_I2(r, r, rC)
 C_O1_I2(r, r, rU)
+C_O1_I2(r, r, rW)
 C_O1_I2(r, 0, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index ce6843b408..5b529b52ad 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -386,6 +386,28 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
     tcg_out_opc_addi_w(s, ret, arg, 0);
 }
 
+static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
+                           TCGReg a0, TCGReg a1, TCGReg a2,
+                           bool c2, bool is_32bit)
+{
+    if (c2) {
+        /*
+         * Fast path: semantics already satisfied due to constraint and
+         * insn behavior, single instruction is enough.
+         */
+        tcg_debug_assert(a2 == (is_32bit ? 32 : 64));
+        /* all clz/ctz insns belong to DJ-format */
+        tcg_out32(s, encode_dj_insn(opc, a0, a1));
+        return;
+    }
+
+    tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1));
+    /* a0 = a1 ? REG_TMP0 : a2 */
+    tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1);
+    tcg_out_opc_masknez(s, a0, a2, a1);
+    tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
+}
+
 /*
  * Entry-points
  */
@@ -546,6 +568,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_opc_revb_d(s, a0, a1);
         break;
 
+    case INDEX_op_clz_i32:
+        tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true);
+        break;
+    case INDEX_op_clz_i64:
+        tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false);
+        break;
+
+    case INDEX_op_ctz_i32:
+        tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true);
+        break;
+    case INDEX_op_ctz_i64:
+        tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     default:
@@ -606,6 +642,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
         /* LoongArch reg-imm bitops have their imms ZERO-extended */
         return C_O1_I2(r, r, rU);
 
+    case INDEX_op_clz_i32:
+    case INDEX_op_clz_i64:
+    case INDEX_op_ctz_i32:
+    case INDEX_op_ctz_i64:
+        return C_O1_I2(r, r, rW);
+
     case INDEX_op_deposit_i32:
     case INDEX_op_deposit_i64:
         /* Must deposit into the same register as input */
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 02d17d2f6d..ef489cbc86 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -120,8 +120,8 @@ typedef enum {
 #define TCG_TARGET_HAS_eqv_i32          0
 #define TCG_TARGET_HAS_nand_i32         0
 #define TCG_TARGET_HAS_nor_i32          1
-#define TCG_TARGET_HAS_clz_i32          0
-#define TCG_TARGET_HAS_ctz_i32          0
+#define TCG_TARGET_HAS_clz_i32          1
+#define TCG_TARGET_HAS_ctz_i32          1
 #define TCG_TARGET_HAS_ctpop_i32        0
 #define TCG_TARGET_HAS_direct_jump      0
 #define TCG_TARGET_HAS_brcond2          0
@@ -156,8 +156,8 @@ typedef enum {
 #define TCG_TARGET_HAS_eqv_i64          0
 #define TCG_TARGET_HAS_nand_i64         0
 #define TCG_TARGET_HAS_nor_i64          1
-#define TCG_TARGET_HAS_clz_i64          0
-#define TCG_TARGET_HAS_ctz_i64          0
+#define TCG_TARGET_HAS_clz_i64          1
+#define TCG_TARGET_HAS_ctz_i64          1
 #define TCG_TARGET_HAS_ctpop_i64        0
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
-- 
2.33.0



  parent reply	other threads:[~2021-09-23 17:16 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-23 16:59 [PATCH v4 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-23 17:53   ` Philippe Mathieu-Daudé
2021-09-23 16:59 ` [PATCH v4 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-24 14:52   ` Richard Henderson
2021-09-23 16:59 ` [PATCH v4 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-23 16:59 ` WANG Xuerui [this message]
2021-09-23 16:59 ` [PATCH v4 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-24 14:56   ` Richard Henderson
2021-09-24 15:19     ` WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 30/30] configure, meson.build: Mark support " WANG Xuerui

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