From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Laurent Vivier" <laurent@vivier.eu>
Subject: [PATCH v4 27/30] tcg/loongarch64: Register the JIT
Date: Fri, 24 Sep 2021 00:59:36 +0800 [thread overview]
Message-ID: <20210923165939.729081-28-git@xen0n.name> (raw)
In-Reply-To: <20210923165939.729081-1-git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 83b8bcdfdf..bce03a96d7 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1594,3 +1594,47 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_LOONGARCH
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.return_column = TCG_REG_RA,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */
+ 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */
+ 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */
+ 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */
+ 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */
+ 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */
+ 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */
+ 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */
+ 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */
+ 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */
+ 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
+ }
+};
+
+void tcg_register_jit(const void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
--
2.33.0
next prev parent reply other threads:[~2021-09-23 17:37 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 16:59 [PATCH v4 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-23 17:53 ` Philippe Mathieu-Daudé
2021-09-23 16:59 ` [PATCH v4 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-24 14:52 ` Richard Henderson
2021-09-23 16:59 ` [PATCH v4 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-24 14:56 ` Richard Henderson
2021-09-24 15:19 ` WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-23 16:59 ` WANG Xuerui [this message]
2021-09-23 16:59 ` [PATCH v4 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 30/30] configure, meson.build: Mark support " WANG Xuerui
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