From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
Bin Meng <bin.meng@windriver.com>,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v12 1/7] [RISCV_PM] Add J-extension into RISC-V
Date: Tue, 28 Sep 2021 22:00:30 +0300 [thread overview]
Message-ID: <20210928190036.4114438-2-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20210928190036.4114438-1-space.monkey.delivers@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5896aca346..cd86f5422f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -68,6 +68,7 @@
#define RVU RV('U')
#define RVH RV('H')
#define RVB RV('B')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -292,6 +293,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.30.2
next prev parent reply other threads:[~2021-09-28 19:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-28 19:00 [PATCH v12 0/7] RISC-V Pointer Masking implementatio Alexey Baturo
2021-09-28 19:00 ` Alexey Baturo [this message]
2021-09-28 19:00 ` [PATCH v12 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-09-29 10:55 ` Richard Henderson
2021-09-28 19:00 ` [PATCH v12 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 7/7] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
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