From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
Bin Meng <bin.meng@windriver.com>,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com,
Alistair Francis <alistair.francis@wdc.com>,
Anatoly Parshintsev <kupokupokupopo@gmail.com>,
palmer@dabbelt.com
Subject: [PATCH v12 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
Date: Tue, 28 Sep 2021 22:00:35 +0300 [thread overview]
Message-ID: <20210928190036.4114438-7-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20210928190036.4114438-1-space.monkey.delivers@gmail.com>
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 20 ++++++++++++++
target/riscv/translate.c | 56 +++++++++++++++++++++++++++++++++-------
2 files changed, 66 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c41a937a80..a7496d9a56 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -405,6 +405,8 @@ FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+/* If PointerMasking should be applied */
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -462,6 +464,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+ if (riscv_has_ext(env, RVJ)) {
+ int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
+ bool pm_enabled = false;
+ switch (priv) {
+ case PRV_U:
+ pm_enabled = env->mmte & U_PM_ENABLE;
+ break;
+ case PRV_S:
+ pm_enabled = env->mmte & S_PM_ENABLE;
+ break;
+ case PRV_M:
+ pm_enabled = env->mmte & M_PM_ENABLE;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index de4997a3e5..4618443524 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
#include "exec/gen-icount.h"
@@ -81,6 +84,10 @@ typedef struct DisasContext {
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
+ /* PointerMasking extension */
+ bool pm_enabled;
+ TCGv pm_mask;
+ TCGv pm_base;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -117,16 +124,6 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
-/*
- * Temp stub: generates address adjustment for PointerMasking
- */
-static void gen_pm_adjust_address(DisasContext *s,
- TCGv *dst,
- TCGv src)
-{
- tcg_gen_mov_tl(*dst, src);
-}
-
/*
* A narrow n-bit operation, where n < FLEN, checks that input operands
* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
@@ -281,6 +278,26 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
+/*
+ * Generates address adjustment for PointerMasking
+ */
+static void gen_pm_adjust_address(DisasContext *s,
+ TCGv *dst,
+ TCGv src)
+{
+ TCGv temp;
+ if (!s->pm_enabled) {
+ /* Load unmodified address */
+ tcg_gen_mov_tl(*dst, src);
+ } else {
+ temp = temp_new(s);
+ tcg_gen_andc_tl(temp, src, s->pm_mask);
+ tcg_gen_or_tl(temp, temp, s->pm_base);
+ *dst = temp;
+ }
+}
+
+
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
@@ -553,6 +570,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->w = false;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
+ ctx->pm_mask = pm_mask[priv];
+ ctx->pm_base = pm_base[priv];
ctx->zero = tcg_constant_tl(0);
}
@@ -666,4 +687,19 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
+#ifndef CONFIG_USER_ONLY
+ /* Assign PM CSRs to tcg globals */
+ pm_mask[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+ pm_base[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+ pm_mask[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+ pm_base[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+ pm_mask[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+ pm_base[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
+#endif
}
--
2.30.2
next prev parent reply other threads:[~2021-09-28 19:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-28 19:00 [PATCH v12 0/7] RISC-V Pointer Masking implementatio Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 1/7] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-09-29 10:55 ` Richard Henderson
2021-09-28 19:00 ` [PATCH v12 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-09-28 19:00 ` [PATCH v12 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-09-28 19:00 ` Alexey Baturo [this message]
2021-09-28 19:00 ` [PATCH v12 7/7] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
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