* [PATCH v2 0/2] target/riscv: fix hypervisor exceptions @ 2021-10-26 14:51 Jose Martins 2021-10-26 14:51 ` [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS Jose Martins 2021-10-26 14:51 ` [PATCH v2 2/2] target/riscv: remove force HS exception Jose Martins 0 siblings, 2 replies; 5+ messages in thread From: Jose Martins @ 2021-10-26 14:51 UTC (permalink / raw) To: qemu-devel; +Cc: Jose Martins This patch series fixes the forwarding of VS-level execptions to HS-mode and removes unecessary code previously used for the routing of exceptions to HS-mode. Jose Martins (2): target/riscv: fix VS interrupts forwarding to HS target/riscv: remove force HS exception target/riscv/cpu.h | 2 -- target/riscv/cpu_bits.h | 6 ----- target/riscv/cpu_helper.c | 54 +++++++-------------------------------- 3 files changed, 9 insertions(+), 53 deletions(-) -- 2.33.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS 2021-10-26 14:51 [PATCH v2 0/2] target/riscv: fix hypervisor exceptions Jose Martins @ 2021-10-26 14:51 ` Jose Martins 2021-10-27 3:24 ` Alistair Francis 2021-10-26 14:51 ` [PATCH v2 2/2] target/riscv: remove force HS exception Jose Martins 1 sibling, 1 reply; 5+ messages in thread From: Jose Martins @ 2021-10-26 14:51 UTC (permalink / raw) To: qemu-devel Cc: Jose Martins, Alistair Francis, Bin Meng, Palmer Dabbelt, open list:RISC-V TCG CPUs VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when not delegated in hideleg (which was not being taken into account). This was mainly because hs level sie was not always considered enabled when it should. The spec states that "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode." and also "For purposes of interrupt global enables, HS-mode is considered more privileged than VS-mode, and VS-mode is considered more privileged than VU-mode". Also, vs-level interrupts were not being taken into account unless V=1, but should be unless delegated. Finally, there is no need for a special case for to handle vs interrupts as the current privilege level, the state of the global ie and of the delegation registers should be enough to route all interrupts to the appropriate privilege level in riscv_cpu_do_interrupt. Signed-off-by: Jose Martins <josemartins90@gmail.com> --- target/riscv/cpu_helper.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..55db004fea 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -38,36 +38,24 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - target_ulong irqs; + target_ulong virt_enabled = riscv_cpu_virt_enabled(env); target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); - target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); - target_ulong pending = env->mip & env->mie & - ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); - target_ulong vspending = (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); + target_ulong pending = env->mip & env->mie; target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); - target_ulong hs_sie = env->priv < PRV_S || - (env->priv == PRV_S && hs_mstatus_sie); + target_ulong hsie = virt_enabled || sie; + target_ulong vsie = virt_enabled && sie; - if (riscv_cpu_virt_enabled(env)) { - target_ulong pending_hs_irq = pending & -hs_sie; - - if (pending_hs_irq) { - riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); - return ctz64(pending_hs_irq); - } - - pending = vspending; - } - - irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); + target_ulong irqs = + (pending & ~env->mideleg & -mie) | + (pending & env->mideleg & ~env->hideleg & -hsie) | + (pending & env->mideleg & env->hideleg & -vsie); if (irqs) { return ctz64(irqs); /* since non-zero */ -- 2.33.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS 2021-10-26 14:51 ` [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS Jose Martins @ 2021-10-27 3:24 ` Alistair Francis 0 siblings, 0 replies; 5+ messages in thread From: Alistair Francis @ 2021-10-27 3:24 UTC (permalink / raw) To: Jose Martins Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V TCG CPUs On Wed, Oct 27, 2021 at 12:53 AM Jose Martins <josemartins90@gmail.com> wrote: > > VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when > not delegated in hideleg (which was not being taken into account). This > was mainly because hs level sie was not always considered enabled when > it should. The spec states that "Interrupts for higher-privilege modes, > y>x, are always globally enabled regardless of the setting of the global > yIE bit for the higher-privilege mode." and also "For purposes of > interrupt global enables, HS-mode is considered more privileged than > VS-mode, and VS-mode is considered more privileged than VU-mode". Also, > vs-level interrupts were not being taken into account unless V=1, but > should be unless delegated. > > Finally, there is no need for a special case for to handle vs interrupts > as the current privilege level, the state of the global ie and of the > delegation registers should be enough to route all interrupts to the > appropriate privilege level in riscv_cpu_do_interrupt. > > Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 28 ++++++++-------------------- > 1 file changed, 8 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 968cb8046f..55db004fea 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -38,36 +38,24 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) > #ifndef CONFIG_USER_ONLY > static int riscv_cpu_local_irq_pending(CPURISCVState *env) > { > - target_ulong irqs; > + target_ulong virt_enabled = riscv_cpu_virt_enabled(env); > > target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); > target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); > - target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE); > > - target_ulong pending = env->mip & env->mie & > - ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); > - target_ulong vspending = (env->mip & env->mie & > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); > + target_ulong pending = env->mip & env->mie; > > target_ulong mie = env->priv < PRV_M || > (env->priv == PRV_M && mstatus_mie); > target_ulong sie = env->priv < PRV_S || > (env->priv == PRV_S && mstatus_sie); > - target_ulong hs_sie = env->priv < PRV_S || > - (env->priv == PRV_S && hs_mstatus_sie); > + target_ulong hsie = virt_enabled || sie; > + target_ulong vsie = virt_enabled && sie; > > - if (riscv_cpu_virt_enabled(env)) { > - target_ulong pending_hs_irq = pending & -hs_sie; > - > - if (pending_hs_irq) { > - riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP); > - return ctz64(pending_hs_irq); > - } > - > - pending = vspending; > - } > - > - irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie); > + target_ulong irqs = > + (pending & ~env->mideleg & -mie) | > + (pending & env->mideleg & ~env->hideleg & -hsie) | > + (pending & env->mideleg & env->hideleg & -vsie); > > if (irqs) { > return ctz64(irqs); /* since non-zero */ > -- > 2.33.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] target/riscv: remove force HS exception 2021-10-26 14:51 [PATCH v2 0/2] target/riscv: fix hypervisor exceptions Jose Martins 2021-10-26 14:51 ` [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS Jose Martins @ 2021-10-26 14:51 ` Jose Martins 2021-10-27 3:24 ` Alistair Francis 1 sibling, 1 reply; 5+ messages in thread From: Jose Martins @ 2021-10-26 14:51 UTC (permalink / raw) To: qemu-devel Cc: Jose Martins, Alistair Francis, Bin Meng, Palmer Dabbelt, open list:RISC-V TCG CPUs There is no need to "force an hs exception" as the current privilege level, the state of the global ie and of the delegation registers should be enough to route the interrupt to the appropriate privilege level in riscv_cpu_do_interrupt. The is true for both asynchronous and synchronous exceptions, specifically, guest page faults which must be hardwired to zero hedeleg. As such the hs_force_except mechanism can be removed. Signed-off-by: Jose Martins <josemartins90@gmail.com> --- target/riscv/cpu.h | 2 -- target/riscv/cpu_bits.h | 6 ------ target/riscv/cpu_helper.c | 26 +------------------------- 3 files changed, 1 insertion(+), 33 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..b3205bfee3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -338,8 +338,6 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); -void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7330ff5a19..5c447e1cc5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -410,12 +410,6 @@ /* Virtulisation Register Fields */ #define VIRT_ONOFF 1 -/* This is used to save state for when we take an exception. If this is set - * that means that we want to force a HS level exception (no matter what the - * delegation is set to). This will occur for things such as a second level - * page table fault. - */ -#define FORCE_HS_EXCEP 2 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 55db004fea..59b72262be 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -178,24 +178,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) env->virt = set_field(env->virt, VIRT_ONOFF, enable); } -bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) -{ - if (!riscv_has_ext(env, RVH)) { - return false; - } - - return get_field(env->virt, FORCE_HS_EXCEP); -} - -void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); -} - bool riscv_cpu_two_stage_lookup(int mmu_idx) { return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; @@ -912,7 +894,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); uint64_t s; /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -941,8 +922,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - force_hs_execp = true; - /* fallthrough */ case RISCV_EXCP_INST_ADDR_MIS: case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: @@ -1001,8 +980,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); } - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && - !force_hs_execp) { + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt @@ -1024,7 +1002,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) htval = env->guest_phys_fault_addr; riscv_cpu_set_virt_enabled(env, 0); - riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); @@ -1060,7 +1037,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trapping to M mode, virt is disabled */ riscv_cpu_set_virt_enabled(env, 0); - riscv_cpu_set_force_hs_excep(env, 0); } s = env->mstatus; -- 2.33.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] target/riscv: remove force HS exception 2021-10-26 14:51 ` [PATCH v2 2/2] target/riscv: remove force HS exception Jose Martins @ 2021-10-27 3:24 ` Alistair Francis 0 siblings, 0 replies; 5+ messages in thread From: Alistair Francis @ 2021-10-27 3:24 UTC (permalink / raw) To: Jose Martins Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V TCG CPUs On Wed, Oct 27, 2021 at 12:54 AM Jose Martins <josemartins90@gmail.com> wrote: > > There is no need to "force an hs exception" as the current privilege > level, the state of the global ie and of the delegation registers should > be enough to route the interrupt to the appropriate privilege level in > riscv_cpu_do_interrupt. The is true for both asynchronous and > synchronous exceptions, specifically, guest page faults which must be > hardwired to zero hedeleg. As such the hs_force_except mechanism can be > removed. > > Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 2 -- > target/riscv/cpu_bits.h | 6 ------ > target/riscv/cpu_helper.c | 26 +------------------------- > 3 files changed, 1 insertion(+), 33 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index bf1c899c00..b3205bfee3 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -338,8 +338,6 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); > bool riscv_cpu_fp_enabled(CPURISCVState *env); > bool riscv_cpu_virt_enabled(CPURISCVState *env); > void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); > -bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); > -void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); > bool riscv_cpu_two_stage_lookup(int mmu_idx); > int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); > hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 7330ff5a19..5c447e1cc5 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -410,12 +410,6 @@ > > /* Virtulisation Register Fields */ > #define VIRT_ONOFF 1 > -/* This is used to save state for when we take an exception. If this is set > - * that means that we want to force a HS level exception (no matter what the > - * delegation is set to). This will occur for things such as a second level > - * page table fault. > - */ > -#define FORCE_HS_EXCEP 2 > > /* RV32 satp CSR field masks */ > #define SATP32_MODE 0x80000000 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 55db004fea..59b72262be 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -178,24 +178,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) > env->virt = set_field(env->virt, VIRT_ONOFF, enable); > } > > -bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) > -{ > - if (!riscv_has_ext(env, RVH)) { > - return false; > - } > - > - return get_field(env->virt, FORCE_HS_EXCEP); > -} > - > -void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) > -{ > - if (!riscv_has_ext(env, RVH)) { > - return; > - } > - > - env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); > -} > - > bool riscv_cpu_two_stage_lookup(int mmu_idx) > { > return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; > @@ -912,7 +894,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > - bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); > uint64_t s; > > /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide > @@ -941,8 +922,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_INST_GUEST_PAGE_FAULT: > case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: > case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: > - force_hs_execp = true; > - /* fallthrough */ > case RISCV_EXCP_INST_ADDR_MIS: > case RISCV_EXCP_INST_ACCESS_FAULT: > case RISCV_EXCP_LOAD_ADDR_MIS: > @@ -1001,8 +980,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); > } > > - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && > - !force_hs_execp) { > + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { > /* Trap to VS mode */ > /* > * See if we need to adjust cause. Yes if its VS mode interrupt > @@ -1024,7 +1002,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) > htval = env->guest_phys_fault_addr; > > riscv_cpu_set_virt_enabled(env, 0); > - riscv_cpu_set_force_hs_excep(env, 0); > } else { > /* Trap into HS mode */ > env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); > @@ -1060,7 +1037,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > /* Trapping to M mode, virt is disabled */ > riscv_cpu_set_virt_enabled(env, 0); > - riscv_cpu_set_force_hs_excep(env, 0); > } > > s = env->mstatus; > -- > 2.33.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-10-27 3:27 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-26 14:51 [PATCH v2 0/2] target/riscv: fix hypervisor exceptions Jose Martins 2021-10-26 14:51 ` [PATCH v2 1/2] target/riscv: fix VS interrupts forwarding to HS Jose Martins 2021-10-27 3:24 ` Alistair Francis 2021-10-26 14:51 ` [PATCH v2 2/2] target/riscv: remove force HS exception Jose Martins 2021-10-27 3:24 ` Alistair Francis
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