From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen
Date: Mon, 1 Nov 2021 18:01:34 +0800 [thread overview]
Message-ID: <20211101100143.44356-5-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211101100143.44356-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/gdbstub.c | 73 +++++++++++++++++++++++++++++++-----------
1 file changed, 54 insertions(+), 19 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 23429179e2..15abbbdb54 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -24,11 +24,25 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+ target_ulong tmp;
if (n < 32) {
- return gdb_get_regl(mem_buf, env->gpr[n]);
+ tmp = env->gpr[n];
} else if (n == 32) {
- return gdb_get_regl(mem_buf, env->pc);
+ tmp = env->pc;
+ } else {
+ return 0;
+ }
+
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ gdb_get_reg32(mem_buf, tmp);
+ break;
+ case MXL_RV64:
+ gdb_get_reg64(mem_buf, tmp);
+ break;
+ default:
+ g_assert_not_reached();
}
return 0;
}
@@ -37,18 +51,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-
- if (n == 0) {
- /* discard writes to x0 */
- return sizeof(target_ulong);
- } else if (n < 32) {
- env->gpr[n] = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ int length = 0;
+ target_ulong tmp;
+
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ tmp = (uint32_t)ldl_p(mem_buf);
+ length = 4;
+ break;
+ case MXL_RV64:
+ if (cpu_get_xl(env) < MXL_RV64) {
+ tmp = (int32_t)ldq_p(mem_buf);
+ } else {
+ tmp = ldq_p(mem_buf);
+ }
+ length = 8;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (n > 0 && n < 32) {
+ env->gpr[n] = tmp;
} else if (n == 32) {
- env->pc = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ env->pc = tmp;
}
- return 0;
+
+ return length;
}
static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
@@ -198,13 +226,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
-#if defined(TARGET_RISCV32)
- gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
- 1, "riscv-32bit-virtual.xml", 0);
-#elif defined(TARGET_RISCV64)
- gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
- 1, "riscv-64bit-virtual.xml", 0);
-#endif
+ switch (env->misa_mxl_max) {
+ case MXL_RV32:
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+ riscv_gdb_set_virtual,
+ 1, "riscv-32bit-virtual.xml", 0);
+ break;
+ case MXL_RV64:
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
+ riscv_gdb_set_virtual,
+ 1, "riscv-64bit-virtual.xml", 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
--
2.25.1
next prev parent reply other threads:[~2021-11-01 10:18 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei
2021-11-01 10:29 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:33 ` Richard Henderson
2021-11-02 1:48 ` LIU Zhiwei
2021-11-02 10:18 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:35 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-01 10:01 ` LIU Zhiwei [this message]
2021-11-01 10:40 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:46 ` Richard Henderson
2021-11-01 15:56 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 13:41 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 11:35 ` Richard Henderson
2021-11-08 9:28 ` LIU Zhiwei
2021-11-09 6:37 ` Richard Henderson
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:25 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 16:33 ` Richard Henderson
2021-11-08 9:38 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 16:43 ` Richard Henderson
2021-11-08 11:23 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 16:49 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 17:01 ` Richard Henderson
2021-11-08 12:10 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211101100143.44356-5-zhiwei_liu@c-sky.com \
--to=zhiwei_liu@c-sky.com \
--cc=Alistair.Francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).