From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH 02/13] target/riscv: Extend pc for runtime pc write
Date: Tue, 2 Nov 2021 09:48:01 +0800 [thread overview]
Message-ID: <e454d42a-4d75-f81e-7d37-c3d81945258e@c-sky.com> (raw)
In-Reply-To: <03cbb2ba-3fc0-e904-6bf6-56ece9cf46b9@linaro.org>
On 2021/11/1 下午6:33, Richard Henderson wrote:
> On 11/1/21 6:01 AM, LIU Zhiwei wrote:
>> In some cases, we must restore the guest PC to the address of the
>> start of
>> the TB, such as when the instruction counter hit zero. So extend pc
>> register
>> according to current xlen for these cases.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.c | 20 +++++++++++++++++---
>> target/riscv/cpu.h | 2 ++
>> target/riscv/cpu_helper.c | 2 +-
>> 3 files changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 7d53125dbc..7eefd4f6a6 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr
>> value)
>> {
>> RISCVCPU *cpu = RISCV_CPU(cs);
>> CPURISCVState *env = &cpu->env;
>> - env->pc = value;
>> +
>> + if (cpu_get_xl(env) == MXL_RV32) {
>> + env->pc = (int32_t)value;
>> + } else {
>> + env->pc = value;
>> + }
>> }
>
> Good.
>
>> static void riscv_cpu_synchronize_from_tb(CPUState *cs,
>> @@ -327,7 +332,12 @@ static void
>> riscv_cpu_synchronize_from_tb(CPUState *cs,
>> {
>> RISCVCPU *cpu = RISCV_CPU(cs);
>> CPURISCVState *env = &cpu->env;
>> - env->pc = tb->pc;
>> +
>> + if (cpu_get_xl(env) == MXL_RV32) {
>> + env->pc = (int32_t)tb->pc;
>> + } else {
>> + env->pc = tb->pc;
>> + }
>
> Bad, since TB->PC should be extended properly.
> Though this waits on a change to cpu_get_tb_cpu_state.
Should the env->pc always hold the sign-extend result? In
cpu_get_tb_cpu_state, we just truncate to the XLEN bits.
Thanks,
Zhiwei
>
>> @@ -348,7 +358,11 @@ static bool riscv_cpu_has_work(CPUState *cs)
>> void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
>> target_ulong *data)
>> {
>> - env->pc = data[0];
>> + if (cpu_get_xl(env) == MXL_RV32) {
>> + env->pc = (int32_t)data[0];
>> + } else {
>> + env->pc = data[0];
>> + }
>
> Likewise.
>
>
> r~
next prev parent reply other threads:[~2021-11-02 1:50 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei
2021-11-01 10:29 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:33 ` Richard Henderson
2021-11-02 1:48 ` LIU Zhiwei [this message]
2021-11-02 10:18 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:35 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-01 10:40 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:46 ` Richard Henderson
2021-11-01 15:56 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 13:41 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 11:35 ` Richard Henderson
2021-11-08 9:28 ` LIU Zhiwei
2021-11-09 6:37 ` Richard Henderson
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:25 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 16:33 ` Richard Henderson
2021-11-08 9:38 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 16:43 ` Richard Henderson
2021-11-08 11:23 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 16:49 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 17:01 ` Richard Henderson
2021-11-08 12:10 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
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