From: Halil Pasic <pasic@linux.ibm.com>
To: Pierre Morel <pmorel@linux.ibm.com>
Cc: thuth@redhat.com, Nico Boehr <nrb@linux.ibm.com>,
frankja@linux.ibm.com, cohuck@redhat.com, qemu-devel@nongnu.org,
Halil Pasic <pasic@linux.ibm.com>,
borntraeger@de.ibm.com, qemu-s390x@nongnu.org
Subject: Re: [PATCH qemu] s390x/css: fix PMCW invalid mask
Date: Mon, 20 Dec 2021 13:11:54 +0100 [thread overview]
Message-ID: <20211220131154.57562cd2.pasic@linux.ibm.com> (raw)
In-Reply-To: <d7459eec-c760-1441-ce40-550b0897e1ba@linux.ibm.com>
On Mon, 20 Dec 2021 11:44:44 +0100
Pierre Morel <pmorel@linux.ibm.com> wrote:
> >
> > The PoP says that the machine shall ignore other fields
> > of the PMCW when an MSCH is performed. I.e. we should not update
> > "our" pmcw.flags bit 5 from 0 to 1 even if 1 was supplied, and
> > thus STSCH should keep storing the bit 5 as 0 even if there was
> > a MSCH with bit 5 set.
>
> So I do understand that there is no problem, we do not keep track
> of this bit in our pmcw.flags and stsch keep storing this bit as 0. right?
Right! False alarm by me -- sorry.
Regards,
Halil
next prev parent reply other threads:[~2021-12-20 16:01 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 13:16 [PATCH qemu] s390x/css: fix PMCW invalid mask Nico Boehr
2021-12-17 13:58 ` Halil Pasic
2021-12-17 14:54 ` Halil Pasic
2021-12-17 17:13 ` Pierre Morel
2021-12-17 19:28 ` Halil Pasic
2021-12-20 10:44 ` Pierre Morel
2021-12-20 12:11 ` Halil Pasic [this message]
2021-12-22 16:46 ` Cornelia Huck
2021-12-23 10:41 ` Halil Pasic
2021-12-23 11:12 ` Cornelia Huck
2022-01-05 8:42 ` Thomas Huth
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