From: Pierre Morel <pmorel@linux.ibm.com>
To: Halil Pasic <pasic@linux.ibm.com>
Cc: thuth@redhat.com, Nico Boehr <nrb@linux.ibm.com>,
frankja@linux.ibm.com, cohuck@redhat.com, qemu-devel@nongnu.org,
borntraeger@de.ibm.com, qemu-s390x@nongnu.org
Subject: Re: [PATCH qemu] s390x/css: fix PMCW invalid mask
Date: Mon, 20 Dec 2021 11:44:44 +0100 [thread overview]
Message-ID: <d7459eec-c760-1441-ce40-550b0897e1ba@linux.ibm.com> (raw)
In-Reply-To: <20211217202818.7e843a1d.pasic@linux.ibm.com>
On 12/17/21 20:28, Halil Pasic wrote:
> On Fri, 17 Dec 2021 18:13:47 +0100
> Pierre Morel <pmorel@linux.ibm.com> wrote:
>
>>>> Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But,
>>>> as per the principles of operation, bit 5 is ignored in MSCH and bits 0,
>>>> 1, 6 and 7 need to be zero.
>>>
>>> On a second thought, don't we have to make sure then that bit 5 is
>>> ignored?
>>>
>>> static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
>>> {
>>> int i;
>>>
>>> dest->intparm = be32_to_cpu(src->intparm);
>>> dest->flags = be16_to_cpu(src->flags);
>>> dest->devno = be16_to_cpu(src->devno);
>>>
>>> Here we seem to grab flags as a whole, but actually we would have to
>>> mask of bit 5.
>>
>> Why?
>> If this bit is ignored by the machine shouldn't we just ignore it?
>> Forcing it to 0 or to 1 is purely arbitrary no?
>
> We do the masking later on:
> IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
> {
> [..]
> /* Only update the program-modifiable fields. */
> schib->pmcw.intparm = schib_copy.pmcw.intparm;
> oldflags = schib->pmcw.flags;
> schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
> PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
> PMCW_FLAGS_MASK_MP);
> schib->pmcw.flags |= schib_copy.pmcw.flags &
> (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
> PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
> PMCW_FLAGS_MASK_MP);
> [..]
>
> I just didn't read far enough. We do that for a while now.
yes.
>
> The PoP says that the machine shall ignore other fields
> of the PMCW when an MSCH is performed. I.e. we should not update
> "our" pmcw.flags bit 5 from 0 to 1 even if 1 was supplied, and
> thus STSCH should keep storing the bit 5 as 0 even if there was
> a MSCH with bit 5 set.
So I do understand that there is no problem, we do not keep track
of this bit in our pmcw.flags and stsch keep storing this bit as 0. right?
Regards,
Pierre
>
> Regards,
> Halil
>
--
Pierre Morel
IBM Lab Boeblingen
next prev parent reply other threads:[~2021-12-20 15:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 13:16 [PATCH qemu] s390x/css: fix PMCW invalid mask Nico Boehr
2021-12-17 13:58 ` Halil Pasic
2021-12-17 14:54 ` Halil Pasic
2021-12-17 17:13 ` Pierre Morel
2021-12-17 19:28 ` Halil Pasic
2021-12-20 10:44 ` Pierre Morel [this message]
2021-12-20 12:11 ` Halil Pasic
2021-12-22 16:46 ` Cornelia Huck
2021-12-23 10:41 ` Halil Pasic
2021-12-23 11:12 ` Cornelia Huck
2022-01-05 8:42 ` Thomas Huth
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