[PATCH 0/3] tcg/s390x vector fixes

[PATCH 0/3] tcg/s390x vector fixes

[Richard Henderson]

These 3 issues were found by running risu on arm neon test cases.
In the meantime, Thomas encountered one of the same with the new
tests of vectorized sha512.


r~


Richard Henderson (3):
  tcg/s390x: Fix tcg_out_dupi_vec vs VGM
  tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
  tcg/s390x: Fix tcg_out_dup_vec vs general registers

 tcg/s390x/tcg-target.c.inc | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

-- 
2.25.1

[PATCH 1/3] tcg/s390x: Fix tcg_out_dupi_vec vs VGM

[Richard Henderson]

The immediate operands to VGM were in the wrong order,
producing an inverse mask.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 6e65828c09..508f1bccc7 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2715,7 +2715,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                 msb = clz32(val);
                 lsb = 31 - ctz32(val);
             }
-            tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
+            tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
             return;
         }
     } else {
@@ -2729,7 +2729,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                 msb = clz64(val);
                 lsb = 63 - ctz64(val);
             }
-            tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
+            tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
             return;
         }
     }
-- 
2.25.1

[PATCH 2/3] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL

[Richard Henderson]

The operands are output in the wrong order: the tcg selector
argument is first, whereas the s390x selector argument is last.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 508f1bccc7..3b185b3c96 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2868,7 +2868,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         break;
 
     case INDEX_op_bitsel_vec:
-        tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
+        tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
         break;
 
     case INDEX_op_cmp_vec:
-- 
2.25.1

[PATCH 3/3] tcg/s390x: Fix tcg_out_dup_vec vs general registers

[Richard Henderson]

We copied the data from the general register input to the
vector register output, but have not yet replicated it.
We intended to fall through into the vector-vector case,
but failed to redirect the input register.

This is caught by an assertion failure in tcg_out_insn_VRIc,
which diagnosed the incorrect register class.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 3b185b3c96..33becd7694 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2675,6 +2675,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
         if (vece == MO_64) {
             return true;
         }
+        src = dst;
     }
 
     /*
-- 
2.25.1

Re: [PATCH 2/3] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL

[Thomas Huth]

On 10/03/2022 21.27, Richard Henderson wrote:
> The operands are output in the wrong order: the tcg selector
> argument is first, whereas the s390x selector argument is last.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
> Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/s390x/tcg-target.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 508f1bccc7..3b185b3c96 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -2868,7 +2868,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
>           break;
>   
>       case INDEX_op_bitsel_vec:
> -        tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
> +        tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
>           break;
>   
>       case INDEX_op_cmp_vec:

Thank you very much, this indeed fixes the sha512 tet for me!

Tested-by: Thomas Huth <thuth@redhat.com>

Re: [PATCH 0/3] tcg/s390x vector fixes

[Thomas Huth]

On 10/03/2022 21.27, Richard Henderson wrote:
> These 3 issues were found by running risu on arm neon test cases.
> In the meantime, Thomas encountered one of the same with the new
> tests of vectorized sha512.

Thanks! If you don't mind (e.g. if you don't have any other TCG patches 
pending), I can take these through my s390x-next tree (I'm planning another 
pull request before the rc0 hard freeze tomorrow):

  https://gitlab.com/thuth/qemu/-/commits/s390x-next/

  Thomas

Re: [PATCH 0/3] tcg/s390x vector fixes

[Richard Henderson]

On 3/14/22 05:41, Thomas Huth wrote:
> On 10/03/2022 21.27, Richard Henderson wrote:
>> These 3 issues were found by running risu on arm neon test cases.
>> In the meantime, Thomas encountered one of the same with the new
>> tests of vectorized sha512.
> 
> Thanks! If you don't mind (e.g. if you don't have any other TCG patches pending), I can 
> take these through my s390x-next tree (I'm planning another pull request before the rc0 
> hard freeze tomorrow):

I did have another tcg patch; I've just sent off the lot.  But thanks.


r~