* [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements
@ 2022-04-27 17:21 Max Filippov
2022-04-27 17:21 ` [PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers Max Filippov
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Hello,
this series fixes xtensa TCG tests so that they could be built on cores
with reduced configurations (e.g. missing windowed registers, no loop
option, single data watchpoint register) and expands test coverage to
configurations not supported earlier (e.g. MMUv3, timers at high IRQ
levels).
Max Filippov (7):
tests/tcg/xtensa: fix build for cores without windowed registers
tests/tcg/xtensa: restore vecbase SR after test
tests/tcg/xtensa: fix watchpoint test
tests/tcg/xtensa: remove dependency on the loop option
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
tests/tcg/xtensa: enable mmu tests for MMUv3
tests/tcg/xtensa: fix vectors and checks in timer test
tests/tcg/xtensa/crt.S | 2 +
tests/tcg/xtensa/test_break.S | 86 ++++++++-------
tests/tcg/xtensa/test_mmu.S | 182 +++++++++++++++++--------------
tests/tcg/xtensa/test_phys_mem.S | 10 +-
tests/tcg/xtensa/test_sr.S | 2 +
tests/tcg/xtensa/test_timer.S | 68 +++++++++---
6 files changed, 213 insertions(+), 137 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
2022-04-27 17:21 ` [PATCH 2/7] tests/tcg/xtensa: restore vecbase SR after test Max Filippov
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Don't try to initialize windowbase/windowstart in crt.S if they don't
exist.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/crt.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/tcg/xtensa/crt.S b/tests/tcg/xtensa/crt.S
index d9846acace90..909872cd3853 100644
--- a/tests/tcg/xtensa/crt.S
+++ b/tests/tcg/xtensa/crt.S
@@ -8,10 +8,12 @@
.text
.global _start
_start:
+#if XCHAL_HAVE_WINDOWED
movi a2, 1
wsr a2, windowstart
movi a2, 0
wsr a2, windowbase
+#endif
movi a1, _fstack
movi a2, 0x4000f
wsr a2, ps
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/7] tests/tcg/xtensa: restore vecbase SR after test
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
2022-04-27 17:21 ` [PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
2022-04-27 17:21 ` [PATCH 3/7] tests/tcg/xtensa: fix watchpoint test Max Filippov
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Writing garbage into the vecbase SR results in hang in the subsequent
tests that expect to raise an exception. Restore vecbase SR to its
reset value after the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_sr.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S
index b1a91a0637ee..34441c7afff7 100644
--- a/tests/tcg/xtensa/test_sr.S
+++ b/tests/tcg/xtensa/test_sr.S
@@ -221,6 +221,8 @@ test_sr_mask /*scompare1*/12, 0, 0
#if XCHAL_HAVE_VECBASE
test_sr vecbase, 1
+movi a2, XCHAL_VECBASE_RESET_VADDR
+wsr a2, vecbase
#else
test_sr_mask /*vecbase*/231, 0, 0
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/7] tests/tcg/xtensa: fix watchpoint test
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
2022-04-27 17:21 ` [PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers Max Filippov
2022-04-27 17:21 ` [PATCH 2/7] tests/tcg/xtensa: restore vecbase SR after test Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
2022-04-27 17:21 ` [PATCH 4/7] tests/tcg/xtensa: remove dependency on the loop option Max Filippov
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't
hardcode register numbers in the test as 0 and 1, use macros that only
index valid DBREAK* registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_break.S | 86 +++++++++++++++++++----------------
1 file changed, 46 insertions(+), 40 deletions(-)
diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S
index 3379a3f9f06e..3aa18b5cec3f 100644
--- a/tests/tcg/xtensa/test_break.S
+++ b/tests/tcg/xtensa/test_break.S
@@ -200,64 +200,70 @@ test_end
.endm
#if XCHAL_NUM_DBREAK
+#define DB0 0
+#if XCHAL_NUM_DBREAK > 1
+#define DB1 1
+#else
+#define DB1 0
+#endif
test dbreak_exact
- dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
- dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
- dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
+ dbreak_test DB0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
+ dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
+ dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
- dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
- dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
- dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
+ dbreak_test DB1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
+ dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
+ dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
test_end
-test dbreak_overlap
- dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
- dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
+test DBdbreak_overlap
+ dbreak_test DB0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
+ dbreak_test DB1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
- dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
- dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
+ dbreak_test DB0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
+ dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
- dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
- dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
+ dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
+ dbreak_test DB1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
- dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
- dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
- dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i
+ dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
+ dbreak_test DB1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
+ dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007c, l32i
- dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
- dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
- dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i
+ dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
+ dbreak_test DB0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
+ dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000078, l32i
- dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
- dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
- dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i
+ dbreak_test DB0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
+ dbreak_test DB1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
+ dbreak_test DB0, 0x40000020, 0xd0000060, 0xd0000074, l32i
- dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
- dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
+ dbreak_test DB0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
+ dbreak_test DB1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
- dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
- dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
+ dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
+ dbreak_test DB1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
- dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
- dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
+ dbreak_test DB0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
+ dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
- dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i
- dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i
- dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i
+ dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007b, s8i
+ dbreak_test DB1, 0x80000038, 0xd0000078, 0xd000007a, s16i
+ dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007c, s32i
- dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i
- dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i
- dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i
+ dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000075, s8i
+ dbreak_test DB0, 0x80000030, 0xd0000070, 0xd0000076, s16i
+ dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000078, s32i
- dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i
- dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i
- dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i
+ dbreak_test DB0, 0x80000020, 0xd0000060, 0xd000006f, s8i
+ dbreak_test DB1, 0x80000020, 0xd0000060, 0xd0000070, s16i
+ dbreak_test DB0, 0x80000020, 0xd0000060, 0xd0000074, s32i
test_end
-test dbreak_invalid
- dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
- dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
+test DBdbreak_invalid
+ dbreak_test DB0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
+ dbreak_test DB1, 0x40000035, 0xd0000072, 0xd0000070, l32i
test_end
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/7] tests/tcg/xtensa: remove dependency on the loop option
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
` (2 preceding siblings ...)
2022-04-27 17:21 ` [PATCH 3/7] tests/tcg/xtensa: fix watchpoint test Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
2022-04-27 17:21 ` [PATCH 5/7] tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 Max Filippov
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
xtensa core may not have the loop option, but still have timers. Don't
use loop opcode in the timer test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_timer.S | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S
index 1ec8e20883ff..2a383e77190e 100644
--- a/tests/tcg/xtensa/test_timer.S
+++ b/tests/tcg/xtensa/test_timer.S
@@ -115,9 +115,9 @@ test ccompare0_interrupt
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
- loop a3, 1f
- nop
1:
+ addi a3, a3, -1
+ bnez a3, 1b
test_fail
2:
rsr a2, exccause
@@ -148,9 +148,9 @@ test ccompare1_interrupt
movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
- loop a3, 1f
- nop
1:
+ addi a3, a3, -1
+ bnez a3, 1b
test_fail
2:
test_end
@@ -177,9 +177,9 @@ test ccompare2_interrupt
movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
- loop a3, 1f
- nop
1:
+ addi a3, a3, -1
+ bnez a3, 1b
test_fail
2:
test_end
@@ -197,7 +197,7 @@ test ccompare_interrupt_masked
wsr a2, ccompare2
#endif
- movi a3, 2 * WAIT_LOOPS
+ movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
@@ -211,9 +211,10 @@ test ccompare_interrupt_masked
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
- loop a3, 1f
- nop
1:
+ addi a3, a3, -1
+ bnez a3, 1b
+
test_fail
2:
rsr a2, exccause
@@ -231,7 +232,6 @@ test ccompare_interrupt_masked_waiti
wsr a2, ccompare2
#endif
- movi a3, 2 * WAIT_LOOPS
make_ccount_delta a2, a15
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/7] tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
` (3 preceding siblings ...)
2022-04-27 17:21 ` [PATCH 4/7] tests/tcg/xtensa: remove dependency on the loop option Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
2022-04-27 17:21 ` [PATCH 6/7] tests/tcg/xtensa: enable mmu " Max Filippov
2022-04-27 17:21 ` [PATCH 7/7] tests/tcg/xtensa: fix vectors and checks in timer test Max Filippov
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Autorefill tests in the phys_mem test suite are disabled for cores that
have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it
invalidate TLB mappings for entries that conflict with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_phys_mem.S | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S
index 9bb3ee3866ed..f935a702945c 100644
--- a/tests/tcg/xtensa/test_phys_mem.S
+++ b/tests/tcg/xtensa/test_phys_mem.S
@@ -2,7 +2,7 @@
test_suite phys_mem
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
+#if XCHAL_HAVE_PTP_MMU
.purgem test_init
@@ -13,6 +13,14 @@ test_suite phys_mem
witlb a2, a3
movi a2, 0xc0000000
wsr a2, ptevaddr
+#if XCHAL_HAVE_SPANNING_WAY
+ movi a2, 0xc0000000 | XCHAL_SPANNING_WAY
+ idtlb a2
+ iitlb a2
+ movi a2, 0x20000000 | XCHAL_SPANNING_WAY
+ idtlb a2
+ iitlb a2
+#endif
.endm
test inst_fetch_get_pte_no_phys
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6/7] tests/tcg/xtensa: enable mmu tests for MMUv3
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
` (4 preceding siblings ...)
2022-04-27 17:21 ` [PATCH 5/7] tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
2022-04-27 17:21 ` [PATCH 7/7] tests/tcg/xtensa: fix vectors and checks in timer test Max Filippov
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
MMU test suite is disabled for cores that have spanning TLB way, i.e.
for all MMUv3 cores. Instead of disabling it make testing region virtual
addresses explicit and invalidate TLB mappings for entries that conflict
with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_mmu.S | 182 ++++++++++++++++++++----------------
1 file changed, 103 insertions(+), 79 deletions(-)
diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S
index 4cbd6ef4f9d8..1006c8cf77b2 100644
--- a/tests/tcg/xtensa/test_mmu.S
+++ b/tests/tcg/xtensa/test_mmu.S
@@ -2,7 +2,9 @@
test_suite mmu
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
+#if XCHAL_HAVE_PTP_MMU
+#define BASE 0x20000000
+#define TLB_BASE 0x80000000
.purgem test_init
@@ -29,17 +31,27 @@ test_suite mmu
idtlb a2
movi a2, 0x00000009
idtlb a2
+#if XCHAL_HAVE_SPANNING_WAY
+ movi a2, BASE | XCHAL_SPANNING_WAY
+ idtlb a2
+ iitlb a2
+ movi a2, TLB_BASE | XCHAL_SPANNING_WAY
+ idtlb a2
+ iitlb a2
+ movi a2, TLB_BASE
+ wsr a2, ptevaddr
+#endif
.endm
test tlb_group
movi a2, 0x04000002 /* PPN */
- movi a3, 0x01200004 /* VPN */
+ movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
witlb a2, a3
movi a3, 0x00200004
rdtlb0 a1, a3
ritlb0 a2, a3
- movi a3, 0x01000001
+ movi a3, BASE + 0x01000001
assert eq, a1, a3
assert eq, a2, a3
movi a3, 0x00200004
@@ -48,17 +60,17 @@ test tlb_group
movi a3, 0x04000002
assert eq, a1, a3
assert eq, a2, a3
- movi a3, 0x01234567
+ movi a3, BASE + 0x01234567
pdtlb a1, a3
pitlb a2, a3
- movi a3, 0x01234014
+ movi a3, BASE + 0x01234014
assert eq, a1, a3
- movi a3, 0x0123400c
+ movi a3, BASE + 0x0123400c
assert eq, a2, a3
movi a3, 0x00200004
idtlb a3
iitlb a3
- movi a3, 0x01234567
+ movi a3, BASE + 0x01234567
pdtlb a1, a3
pitlb a2, a3
movi a3, 0x00000010
@@ -72,7 +84,7 @@ test_end
test itlb_miss
set_vector kernel, 1f
- movi a3, 0x00100000
+ movi a3, BASE + 0x00100000
jx a3
test_fail
1:
@@ -86,7 +98,7 @@ test_end
test dtlb_miss
set_vector kernel, 1f
- movi a3, 0x00100000
+ movi a3, BASE + 0x00100000
l8ui a2, a3, 0
test_fail
1:
@@ -116,11 +128,11 @@ test dtlb_multi_hit
set_vector kernel, 1f
movi a2, 0x04000002 /* PPN */
- movi a3, 0x01200004 /* VPN */
+ movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
- movi a3, 0x01200007 /* VPN */
+ movi a3, BASE + 0x01200007 /* VPN */
wdtlb a2, a3
- movi a3, 0x01200000
+ movi a3, BASE + 0x01200000
pdtlb a2, a3
test_fail
1:
@@ -168,15 +180,18 @@ test load_store_privilege
and a3, a3, a1
movi a1, 4
or a3, a3, a1
+ movi a5, BASE
+ add a3, a3, a5
witlb a2, a3
movi a3, 10f
movi a1, 0x000fffff
and a1, a3, a1
+ add a1, a1, a5
movi a2, 0x04000003 /* PPN */
- movi a3, 0x01200004 /* VPN */
+ movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
- movi a3, 0x01200001
+ movi a3, BASE + 0x01200001
movi a2, 0x4004f
jx a1
10:
@@ -192,6 +207,7 @@ test load_store_privilege
movi a3, 1b
movi a1, 0x000fffff
and a3, a3, a1
+ add a3, a3, a5
assert eq, a2, a3
rsr a2, exccause
movi a3, 26
@@ -206,9 +222,9 @@ test cring_load_store_privilege
set_vector double, 2f
movi a2, 0x04000003 /* PPN */
- movi a3, 0x01200004 /* VPN */
+ movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
- movi a3, 0x01200004
+ movi a3, BASE + 0x01200004
movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
wsr a2, ps
isync
@@ -245,10 +261,13 @@ test inst_fetch_prohibited
and a3, a3, a1
movi a1, 4
or a3, a3, a1
+ movi a5, BASE
+ add a3, a3, a5
witlb a2, a3
movi a3, 10f
movi a1, 0x000fffff
and a1, a3, a1
+ add a1, a1, a5
jx a1
.align 4
10:
@@ -268,9 +287,9 @@ test load_prohibited
set_vector kernel, 2f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x01200004 /* VPN */
+ movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
- movi a3, 0x01200002
+ movi a3, BASE + 0x01200002
1:
l8ui a2, a3, 0
test_fail
@@ -289,9 +308,9 @@ test store_prohibited
set_vector kernel, 2f
movi a2, 0x04000001 /* PPN */
- movi a3, 0x01200004 /* VPN */
+ movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
- movi a3, 0x01200003
+ movi a3, BASE + 0x01200003
l8ui a2, a3, 0
1:
s8i a2, a3, 0
@@ -311,10 +330,10 @@ test_end
* and DTLB way 7 to cover this PTE, ring=pt_ring, attr=pt_attr
*/
.macro pt_setup pt_ring, pt_attr, pte_ring, vaddr, paddr, pte_attr
- movi a2, 0x80000000
+ movi a2, TLB_BASE
wsr a2, ptevaddr
- movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
+ movi a3, TLB_BASE | 7 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
movi a4, 0x04000003 | ((\pt_ring) << 4) /* PADDR 64M */
wdtlb a4, a3
isync
@@ -324,7 +343,7 @@ test_end
add a2, a1, a2
s32i a3, a2, 0
- movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
+ movi a3, TLB_BASE | 7 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
movi a4, 0x04000000 | ((\pt_ring) << 4) | (\pt_attr) /* PADDR 64M */
wdtlb a4, a3
isync
@@ -343,10 +362,13 @@ test_end
and a3, a3, a1
movi a1, 4
or a3, a3, a1
+ movi a5, BASE
+ add a3, a3, a5
witlb a2, a3
movi a3, 10f
movi a1, 0x000fffff
and a1, a3, a1
+ add a1, a1, a5
movi a2, 0
wsr a2, excvaddr
@@ -396,6 +418,8 @@ test_end
movi a2, (\vaddr)
movi a1, 0xfffff
and a1, a1, a2
+ movi a5, BASE
+ add a1, a1, a5
rsr a2, epc1
assert eq, a1, a2
.endm
@@ -403,7 +427,7 @@ test_end
test dtlb_autoload
set_vector kernel, 0
- pt_setup 0, 3, 1, 0x1000, 0x1000, 3
+ pt_setup 0, 3, 1, BASE + 0x1000, 0x1000, 3
assert_no_auto_tlb
l8ui a1, a3, 0
@@ -418,8 +442,8 @@ test autoload_load_store_privilege
set_vector kernel, 0
set_vector double, 2f
- pt_setup 0, 3, 0, 0x2000, 0x2000, 3
- movi a3, 0x2004
+ pt_setup 0, 3, 0, BASE + 0x2000, 0x2000, 3
+ movi a3, BASE + 0x2004
assert_no_auto_tlb
movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
@@ -441,7 +465,7 @@ test_end
test autoload_pte_load_prohibited
set_vector kernel, 2f
- pt_setup 0, 3, 0, 0x3000, 0, 0xc
+ pt_setup 0, 3, 0, BASE + 0x3000, 0, 0xc
assert_no_auto_tlb
1:
l32i a2, a3, 0
@@ -458,7 +482,7 @@ test_end
test autoload_pt_load_prohibited
set_vector kernel, 2f
- pt_setup 0, 0xc, 0, 0x4000, 0x4000, 3
+ pt_setup 0, 0xc, 0, BASE + 0x4000, 0x4000, 3
assert_no_auto_tlb
1:
l32i a2, a3, 0
@@ -474,8 +498,8 @@ test_end
test autoload_pt_privilege
set_vector kernel, 2f
- pt_setup 0, 3, 1, 0x5000, 0, 3
- go_ring 1, 0, 0x5001
+ pt_setup 0, 3, 1, BASE + 0x5000, 0, 3
+ go_ring 1, 0, BASE + 0x5001
l8ui a2, a3, 0
1:
@@ -491,8 +515,8 @@ test_end
test autoload_pte_privilege
set_vector kernel, 2f
- pt_setup 0, 3, 0, 0x6000, 0, 3
- go_ring 1, 0, 0x6001
+ pt_setup 0, 3, 0, BASE + 0x6000, 0, 3
+ go_ring 1, 0, BASE + 0x6001
1:
l8ui a2, a3, 0
syscall
@@ -507,9 +531,9 @@ test_end
test autoload_3_level_pt
set_vector kernel, 2f
- pt_setup 1, 3, 1, 0x00400000, 0, 3
- pt_setup 1, 3, 1, 0x80001000, 0x2000000, 3
- go_ring 1, 0, 0x00400001
+ pt_setup 1, 3, 1, BASE + 0x00400000, 0, 3
+ pt_setup 1, 3, 1, TLB_BASE + ((BASE + 0x00400000) >> 10), 0x2000000, 3
+ go_ring 1, 0, BASE + 0x00400001
1:
l8ui a2, a3, 0
syscall
@@ -526,14 +550,14 @@ test cross_page_insn
set_vector kernel, 2f
movi a2, 0x04000003 /* PPN */
- movi a3, 0x00007000 /* VPN */
+ movi a3, BASE + 0x00007000 /* VPN */
witlb a2, a3
wdtlb a2, a3
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
wdtlb a2, a3
- movi a2, 0x00007fff
+ movi a2, BASE + 0x00007fff
movi a3, 20f
movi a4, 21f
sub a4, a4, a3
@@ -543,8 +567,8 @@ test cross_page_insn
addi a2, a2, 1
addi a3, a3, 1
1:
- movi a2, 0x00007fff
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007fff
+ movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: OK */
jx a2
@@ -560,20 +584,20 @@ test cross_page_insn
movi a3, 1
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x8002
+ movi a3, BASE + 0x8002
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007fff
+ movi a3, BASE + 0x00007fff
assert ne, a2, a3
reset_ps
set_vector kernel, 3f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
- movi a2, 0x00007fff
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007fff
+ movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: OK */
jx a2
3:
@@ -581,22 +605,22 @@ test cross_page_insn
movi a3, 28
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7fff
+ movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007fff
+ movi a3, BASE + 0x00007fff
assert eq, a2, a3
reset_ps
set_vector kernel, 4f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
movi a2, 0x04000003 /* PPN */
wdtlb a2, a3
- movi a2, 0x00007fff
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007fff
+ movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: FAIL */
jx a2
4:
@@ -604,20 +628,20 @@ test cross_page_insn
movi a3, 20
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7fff
+ movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007fff
+ movi a3, BASE + 0x00007fff
assert eq, a2, a3
reset_ps
set_vector kernel, 5f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
- movi a2, 0x00007fff
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007fff
+ movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: FAIL */
jx a2
5:
@@ -625,10 +649,10 @@ test cross_page_insn
movi a3, 20
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7fff
+ movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007fff
+ movi a3, BASE + 0x00007fff
assert eq, a2, a3
test_end
@@ -636,14 +660,14 @@ test cross_page_tb
set_vector kernel, 2f
movi a2, 0x04000003 /* PPN */
- movi a3, 0x00007000 /* VPN */
+ movi a3, BASE + 0x00007000 /* VPN */
witlb a2, a3
wdtlb a2, a3
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
wdtlb a2, a3
- movi a2, 0x00007ffc
+ movi a2, BASE + 0x00007ffc
movi a3, 20f
movi a4, 21f
sub a4, a4, a3
@@ -653,8 +677,8 @@ test cross_page_tb
addi a2, a2, 1
addi a3, a3, 1
1:
- movi a2, 0x00007ffc
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007ffc
+ movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: OK */
jx a2
@@ -670,20 +694,20 @@ test cross_page_tb
movi a3, 1
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7fff
+ movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007ffc
+ movi a3, BASE + 0x00007ffc
assert ne, a2, a3
reset_ps
set_vector kernel, 3f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
- movi a2, 0x00007ffc
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007ffc
+ movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: OK */
jx a2
3:
@@ -691,22 +715,22 @@ test cross_page_tb
movi a3, 28
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7ffc
+ movi a3, BASE + 0x7ffc
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007ffc
+ movi a3, BASE + 0x00007ffc
assert eq, a2, a3
reset_ps
set_vector kernel, 4f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
movi a2, 0x04000003 /* PPN */
wdtlb a2, a3
- movi a2, 0x00007ffc
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007ffc
+ movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: FAIL */
jx a2
4:
@@ -714,20 +738,20 @@ test cross_page_tb
movi a3, 20
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7fff
+ movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007ffc
+ movi a3, BASE + 0x00007ffc
assert ne, a2, a3
reset_ps
set_vector kernel, 5f
movi a2, 0x0400000c /* PPN */
- movi a3, 0x00008000 /* VPN */
+ movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
- movi a2, 0x00007ffc
- movi a3, 0x00008000
+ movi a2, BASE + 0x00007ffc
+ movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: FAIL */
jx a2
5:
@@ -735,10 +759,10 @@ test cross_page_tb
movi a3, 28
assert eq, a2, a3
rsr a2, epc1
- movi a3, 0x7ffc
+ movi a3, BASE + 0x7ffc
assert eq, a2, a3
rsr a2, excsave1
- movi a3, 0x00007ffc
+ movi a3, BASE + 0x00007ffc
assert eq, a2, a3
test_end
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 7/7] tests/tcg/xtensa: fix vectors and checks in timer test
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
` (5 preceding siblings ...)
2022-04-27 17:21 ` [PATCH 6/7] tests/tcg/xtensa: enable mmu " Max Filippov
@ 2022-04-27 17:21 ` Max Filippov
6 siblings, 0 replies; 8+ messages in thread
From: Max Filippov @ 2022-04-27 17:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Timer test assumes that timer 0 IRQ has level 1 and other timers have
higher level IRQs. This assumption is not correct and the levels may be
arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and
using it for vector selection and by making the check for the timer
exception cause conditional.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_timer.S | 48 ++++++++++++++++++++++++++++++-----
1 file changed, 41 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S
index 2a383e77190e..2a06eebad883 100644
--- a/tests/tcg/xtensa/test_timer.S
+++ b/tests/tcg/xtensa/test_timer.S
@@ -38,6 +38,28 @@ test_end
#if XCHAL_NUM_TIMERS
+#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
+#define TIMER0_VECTOR kernel
+#else
+#define TIMER0_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT))
+#endif
+
+#if XCHAL_NUM_TIMERS > 1
+#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
+#define TIMER1_VECTOR kernel
+#else
+#define TIMER1_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT))
+#endif
+#endif
+
+#if XCHAL_NUM_TIMERS > 2
+#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
+#define TIMER2_VECTOR kernel
+#else
+#define TIMER2_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT))
+#endif
+#endif
+
test ccount_update_deadline
movi a2, 0
wsr a2, intenable
@@ -90,9 +112,8 @@ test ccompare
assert nei, a5, 0
test_end
-#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
test ccompare0_interrupt
- set_vector kernel, 2f
+ set_vector TIMER0_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@@ -120,15 +141,16 @@ test ccompare0_interrupt
bnez a3, 1b
test_fail
2:
+#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
-test_end
#endif
+test_end
#if XCHAL_NUM_TIMERS > 1
test ccompare1_interrupt
- set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f
+ set_vector TIMER1_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@@ -153,13 +175,17 @@ test ccompare1_interrupt
bnez a3, 1b
test_fail
2:
+#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
+ rsr a2, exccause
+ assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
+#endif
test_end
#endif
#if XCHAL_NUM_TIMERS > 2
test ccompare2_interrupt
- set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f
+ set_vector TIMER2_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@@ -182,12 +208,16 @@ test ccompare2_interrupt
bnez a3, 1b
test_fail
2:
+#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
+ rsr a2, exccause
+ assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
+#endif
test_end
#endif
test ccompare_interrupt_masked
- set_vector kernel, 2f
+ set_vector TIMER0_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@@ -217,12 +247,14 @@ test ccompare_interrupt_masked
test_fail
2:
+#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
+#endif
test_end
test ccompare_interrupt_masked_waiti
- set_vector kernel, 2f
+ set_vector TIMER0_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@@ -247,8 +279,10 @@ test ccompare_interrupt_masked_waiti
waiti 0
test_fail
2:
+#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
+#endif
test_end
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-04-27 17:29 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
2022-04-27 17:21 ` [PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers Max Filippov
2022-04-27 17:21 ` [PATCH 2/7] tests/tcg/xtensa: restore vecbase SR after test Max Filippov
2022-04-27 17:21 ` [PATCH 3/7] tests/tcg/xtensa: fix watchpoint test Max Filippov
2022-04-27 17:21 ` [PATCH 4/7] tests/tcg/xtensa: remove dependency on the loop option Max Filippov
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2022-04-27 17:21 ` [PATCH 6/7] tests/tcg/xtensa: enable mmu " Max Filippov
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