[PATCH v3 0/2] Enhance maximum priority support of PLIC

[PATCH v3 0/2] Enhance maximum priority support of PLIC

[Jim Shu]

This patchset fixes hard-coded maximum priority of interrupt priority
register and also changes this register to WARL field to align the PLIC
spec.

Changelog:

v3:
  * fix opposite of power-of-2 max priority checking expression.

v2:
  * change interrupt priority register to WARL field.

Jim Shu (2):
  hw/intc: sifive_plic: fix hard-coded max priority level
  hw/intc: sifive_plic: change interrupt priority register to WARL field

 hw/intc/sifive_plic.c | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

-- 
2.17.1

[PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level

[Jim Shu]

The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.

Also change interrupt priority register to use num_priorities Property
in maximum priority level.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 hw/intc/sifive_plic.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae3630e..f864efa761 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -180,8 +180,10 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 
-        plic->source_priority[irq] = value & 7;
-        sifive_plic_update(plic);
+        if (value <= plic->num_priorities) {
+            plic->source_priority[irq] = value;
+            sifive_plic_update(plic);
+        }
     } else if (addr_between(addr, plic->pending_base,
                             plic->num_sources >> 3)) {
         qemu_log_mask(LOG_GUEST_ERROR,
-- 
2.17.1

[PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

[Jim Shu]

PLIC spec [1] requires interrupt source priority registers are WARL
field and the number of supported priority is power-of-2 to simplify SW
discovery.

Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
spec, whose number of supported priority is not power-of-2. Just change
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.

[1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities

Signed-off-by: Jim Shu <jim.shu@sifive.com>
---
 hw/intc/sifive_plic.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f864efa761..c2dfacf028 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -180,7 +180,15 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 
-        if (value <= plic->num_priorities) {
+        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+            /*
+             * if "num_priorities + 1" is power-of-2, make each register bit of
+             * interrupt priority WARL (Write-Any-Read-Legal). Just filter
+             * out the access to unsupported priority bits.
+             */
+            plic->source_priority[irq] = value % (plic->num_priorities + 1);
+            sifive_plic_update(plic);
+        } else if (value <= plic->num_priorities) {
             plic->source_priority[irq] = value;
             sifive_plic_update(plic);
         }
@@ -207,7 +215,16 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
         uint32_t contextid = (addr & (plic->context_stride - 1));
 
         if (contextid == 0) {
-            if (value <= plic->num_priorities) {
+            if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+                /*
+                 * if "num_priorities + 1" is power-of-2, each register bit of
+                 * interrupt priority is WARL (Write-Any-Read-Legal). Just
+                 * filter out the access to unsupported priority bits.
+                 */
+                plic->target_priority[addrid] = value %
+                                                (plic->num_priorities + 1);
+                sifive_plic_update(plic);
+            } else if (value <= plic->num_priorities) {
                 plic->target_priority[addrid] = value;
                 sifive_plic_update(plic);
             }
-- 
2.17.1

Re: [PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

[Clément Chigot]

On Mon, Oct 3, 2022 at 6:14 AM Jim Shu <jim.shu@sifive.com> wrote:
>
> PLIC spec [1] requires interrupt source priority registers are WARL
> field and the number of supported priority is power-of-2 to simplify SW
> discovery.
>
> Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
> spec, whose number of supported priority is not power-of-2. Just change
> each bit of interrupt priority register to WARL field when the number of
> supported priority is power-of-2.
>
> [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> ---
>  hw/intc/sifive_plic.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index f864efa761..c2dfacf028 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -180,7 +180,15 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
>      if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
>          uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
>
> -        if (value <= plic->num_priorities) {
> +        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
> +            /*
> +             * if "num_priorities + 1" is power-of-2, make each register bit of
> +             * interrupt priority WARL (Write-Any-Read-Legal). Just filter
> +             * out the access to unsupported priority bits.
> +             */
> +            plic->source_priority[irq] = value % (plic->num_priorities + 1);
> +            sifive_plic_update(plic);
> +        } else if (value <= plic->num_priorities) {
>              plic->source_priority[irq] = value;
>              sifive_plic_update(plic);
>          }
> @@ -207,7 +215,16 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
>          uint32_t contextid = (addr & (plic->context_stride - 1));
>
>          if (contextid == 0) {
> -            if (value <= plic->num_priorities) {
> +            if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
> +                /*
> +                 * if "num_priorities + 1" is power-of-2, each register bit of
> +                 * interrupt priority is WARL (Write-Any-Read-Legal). Just
> +                 * filter out the access to unsupported priority bits.
> +                 */
> +                plic->target_priority[addrid] = value %
> +                                                (plic->num_priorities + 1);
> +                sifive_plic_update(plic);
> +            } else if (value <= plic->num_priorities) {
>                  plic->target_priority[addrid] = value;
>                  sifive_plic_update(plic);
>              }
> --
> 2.17.1

Reviewed-by: Clément Chigot <chigot@adacore.com>

Re: [PATCH v3 0/2] Enhance maximum priority support of PLIC

[Jim Shu]

Gentle ping.

It's a patch for fix and spec alignment of PLIC.


On Mon, Oct 3, 2022 at 12:14 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
> Changelog:
>
> v3:
>   * fix opposite of power-of-2 max priority checking expression.
>
> v2:
>   * change interrupt priority register to WARL field.
>
> Jim Shu (2):
>   hw/intc: sifive_plic: fix hard-coded max priority level
>   hw/intc: sifive_plic: change interrupt priority register to WARL field
>
>  hw/intc/sifive_plic.c | 25 ++++++++++++++++++++++---
>  1 file changed, 22 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>

Re: [PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level

[Alistair Francis]

On Mon, Oct 3, 2022 at 2:16 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> The maximum priority level is hard-coded when writing to interrupt
> priority register. However, when writing to priority threshold register,
> the maximum priority level is from num_priorities Property which is
> configured by platform.
>
> Also change interrupt priority register to use num_priorities Property
> in maximum priority level.
>
> Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/intc/sifive_plic.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index af4ae3630e..f864efa761 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -180,8 +180,10 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
>      if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
>          uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
>
> -        plic->source_priority[irq] = value & 7;
> -        sifive_plic_update(plic);
> +        if (value <= plic->num_priorities) {
> +            plic->source_priority[irq] = value;
> +            sifive_plic_update(plic);
> +        }
>      } else if (addr_between(addr, plic->pending_base,
>                              plic->num_sources >> 3)) {
>          qemu_log_mask(LOG_GUEST_ERROR,
> --
> 2.17.1
>
>

Re: [PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

[Alistair Francis]

On Mon, Oct 3, 2022 at 5:07 PM Clément Chigot <chigot@adacore.com> wrote:
>
> On Mon, Oct 3, 2022 at 6:14 AM Jim Shu <jim.shu@sifive.com> wrote:
> >
> > PLIC spec [1] requires interrupt source priority registers are WARL
> > field and the number of supported priority is power-of-2 to simplify SW
> > discovery.
> >
> > Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
> > spec, whose number of supported priority is not power-of-2. Just change
> > each bit of interrupt priority register to WARL field when the number of
> > supported priority is power-of-2.
> >
> > [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> > ---
> >  hw/intc/sifive_plic.c | 21 +++++++++++++++++++--
> >  1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> > index f864efa761..c2dfacf028 100644
> > --- a/hw/intc/sifive_plic.c
> > +++ b/hw/intc/sifive_plic.c
> > @@ -180,7 +180,15 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
> >      if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
> >          uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
> >
> > -        if (value <= plic->num_priorities) {
> > +        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
> > +            /*
> > +             * if "num_priorities + 1" is power-of-2, make each register bit of
> > +             * interrupt priority WARL (Write-Any-Read-Legal). Just filter
> > +             * out the access to unsupported priority bits.
> > +             */
> > +            plic->source_priority[irq] = value % (plic->num_priorities + 1);
> > +            sifive_plic_update(plic);
> > +        } else if (value <= plic->num_priorities) {
> >              plic->source_priority[irq] = value;
> >              sifive_plic_update(plic);
> >          }
> > @@ -207,7 +215,16 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
> >          uint32_t contextid = (addr & (plic->context_stride - 1));
> >
> >          if (contextid == 0) {
> > -            if (value <= plic->num_priorities) {
> > +            if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
> > +                /*
> > +                 * if "num_priorities + 1" is power-of-2, each register bit of
> > +                 * interrupt priority is WARL (Write-Any-Read-Legal). Just
> > +                 * filter out the access to unsupported priority bits.
> > +                 */
> > +                plic->target_priority[addrid] = value %
> > +                                                (plic->num_priorities + 1);
> > +                sifive_plic_update(plic);
> > +            } else if (value <= plic->num_priorities) {
> >                  plic->target_priority[addrid] = value;
> >                  sifive_plic_update(plic);
> >              }
> > --
> > 2.17.1
>
> Reviewed-by: Clément Chigot <chigot@adacore.com>
>

Re: [PATCH v3 0/2] Enhance maximum priority support of PLIC

[Alistair Francis]

On Mon, Oct 3, 2022 at 2:18 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
> Changelog:
>
> v3:
>   * fix opposite of power-of-2 max priority checking expression.
>
> v2:
>   * change interrupt priority register to WARL field.
>
> Jim Shu (2):
>   hw/intc: sifive_plic: fix hard-coded max priority level
>   hw/intc: sifive_plic: change interrupt priority register to WARL field

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/intc/sifive_plic.c | 25 ++++++++++++++++++++++---
>  1 file changed, 22 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>
>