* [PULL 0/7] loongarch-to-apply queue
@ 2022-11-03 12:38 Song Gao
2022-11-03 12:38 ` [PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi Song Gao
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:38 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha
The following changes since commit a11f65ec1b8adcb012b89c92819cbda4dc25aaf1:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2022-11-01 13:49:33 -0400)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221103
for you to fetch changes up to d31e2b1af7e6db41e6088679babc3893bd69b4b3:
target/loongarch: Fix raise_mmu_exception() set wrong exception_index (2022-11-03 17:59:19 +0800)
----------------------------------------------------------------
pull-loongarch-20221103
----------------------------------------------------------------
Song Gao (2):
target/loongarch: Add exception subcode
target/loongarch: Fix raise_mmu_exception() set wrong exception_index
Xiaojuan Yang (5):
hw/intc: Convert the memops to with_attrs in LoongArch extioi
hw/intc: Fix LoongArch extioi coreisr accessing
hw/loongarch: Load FDT table into dram memory space
hw/loongarch: Improve fdt for LoongArch virt machine
hw/loongarch: Add TPM device for LoongArch virt machine
hw/intc/loongarch_extioi.c | 41 ++++++++++++++++-------------
hw/intc/trace-events | 3 +--
hw/loongarch/acpi-build.c | 50 +++++++++++++++++++++++++++++++++--
hw/loongarch/virt.c | 53 ++++++++++++++++++++++++++++++++-----
include/hw/loongarch/virt.h | 3 ---
include/hw/pci-host/ls7a.h | 1 +
target/loongarch/cpu.c | 8 ++++--
target/loongarch/cpu.h | 58 ++++++++++++++++++++++-------------------
target/loongarch/iocsr_helper.c | 19 ++++++++------
target/loongarch/tlb_helper.c | 5 ++--
10 files changed, 170 insertions(+), 71 deletions(-)
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
@ 2022-11-03 12:38 ` Song Gao
2022-11-03 12:38 ` [PULL 2/7] hw/intc: Fix LoongArch extioi coreisr accessing Song Gao
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:38 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, stefanha, Xiaojuan Yang, Philippe Mathieu-Daudé
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Converting the MemoryRegionOps read/write handlers to
with_attrs in LoongArch extioi emulation.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
hw/intc/trace-events | 3 +--
2 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 22803969bc..72f4b0cde5 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -68,44 +68,45 @@ static void extioi_setirq(void *opaque, int irq, int level)
extioi_update_irq(s, irq, level);
}
-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
{
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
unsigned long offset = addr & 0xffff;
- uint32_t index, cpu, ret = 0;
+ uint32_t index, cpu;
switch (offset) {
case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
index = (offset - EXTIOI_NODETYPE_START) >> 2;
- ret = s->nodetype[index];
+ *data = s->nodetype[index];
break;
case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
index = (offset - EXTIOI_IPMAP_START) >> 2;
- ret = s->ipmap[index];
+ *data = s->ipmap[index];
break;
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
index = (offset - EXTIOI_ENABLE_START) >> 2;
- ret = s->enable[index];
+ *data = s->enable[index];
break;
case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
index = (offset - EXTIOI_BOUNCE_START) >> 2;
- ret = s->bounce[index];
+ *data = s->bounce[index];
break;
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
- ret = s->coreisr[cpu][index];
+ *data = s->coreisr[cpu][index];
break;
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
index = (offset - EXTIOI_COREMAP_START) >> 2;
- ret = s->coremap[index];
+ *data = s->coremap[index];
break;
default:
break;
}
- trace_loongarch_extioi_readw(addr, ret);
- return ret;
+ trace_loongarch_extioi_readw(addr, *data);
+ return MEMTX_OK;
}
static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
@@ -127,8 +128,9 @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
}
}
-static void extioi_writew(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
+static MemTxResult extioi_writew(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
{
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
int i, cpu, index, old_data, irq;
@@ -231,11 +233,12 @@ static void extioi_writew(void *opaque, hwaddr addr,
default:
break;
}
+ return MEMTX_OK;
}
static const MemoryRegionOps extioi_ops = {
- .read = extioi_readw,
- .write = extioi_writew,
+ .read_with_attrs = extioi_readw,
+ .write_with_attrs = extioi_writew,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.valid.min_access_size = 4,
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 0a90c1cdec..6fbc2045e6 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -306,6 +306,5 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
# loongarch_extioi.c
loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
-
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 2/7] hw/intc: Fix LoongArch extioi coreisr accessing
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
2022-11-03 12:38 ` [PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi Song Gao
@ 2022-11-03 12:38 ` Song Gao
2022-11-03 12:38 ` [PULL 3/7] hw/loongarch: Load FDT table into dram memory space Song Gao
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:38 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha, Xiaojuan Yang
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' requester_id to get
the cpu index.
2. it need not to mask 0x1f when calculate the coreisr array index.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/loongarch_extioi.c | 10 ++++++----
target/loongarch/iocsr_helper.c | 19 +++++++++++--------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 72f4b0cde5..4b8ec3f28a 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -93,8 +93,9 @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
*data = s->bounce[index];
break;
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+ index = (offset - EXTIOI_COREISR_START) >> 2;
+ /* using attrs to get current cpu index */
+ cpu = attrs.requester_id;
*data = s->coreisr[cpu][index];
break;
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
@@ -185,8 +186,9 @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
s->bounce[index] = val;
break;
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+ index = (offset - EXTIOI_COREISR_START) >> 2;
+ /* using attrs to get current cpu index */
+ cpu = attrs.requester_id;
old_data = s->coreisr[cpu][index];
s->coreisr[cpu][index] = old_data & ~val;
/* write 1 to clear interrrupt */
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
index 0e9c537dc7..505853e17b 100644
--- a/target/loongarch/iocsr_helper.c
+++ b/target/loongarch/iocsr_helper.c
@@ -14,54 +14,57 @@
#include "exec/cpu_ldst.h"
#include "tcg/tcg-ldst.h"
+#define GET_MEMTXATTRS(cas) \
+ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
+
uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
{
return address_space_ldub(&env->address_space_iocsr, r_addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ GET_MEMTXATTRS(env), NULL);
}
uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
{
return address_space_lduw(&env->address_space_iocsr, r_addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ GET_MEMTXATTRS(env), NULL);
}
uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
{
return address_space_ldl(&env->address_space_iocsr, r_addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ GET_MEMTXATTRS(env), NULL);
}
uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
{
return address_space_ldq(&env->address_space_iocsr, r_addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ GET_MEMTXATTRS(env), NULL);
}
void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
target_ulong val)
{
address_space_stb(&env->address_space_iocsr, w_addr,
- val, MEMTXATTRS_UNSPECIFIED, NULL);
+ val, GET_MEMTXATTRS(env), NULL);
}
void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
target_ulong val)
{
address_space_stw(&env->address_space_iocsr, w_addr,
- val, MEMTXATTRS_UNSPECIFIED, NULL);
+ val, GET_MEMTXATTRS(env), NULL);
}
void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
target_ulong val)
{
address_space_stl(&env->address_space_iocsr, w_addr,
- val, MEMTXATTRS_UNSPECIFIED, NULL);
+ val, GET_MEMTXATTRS(env), NULL);
}
void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
target_ulong val)
{
address_space_stq(&env->address_space_iocsr, w_addr,
- val, MEMTXATTRS_UNSPECIFIED, NULL);
+ val, GET_MEMTXATTRS(env), NULL);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 3/7] hw/loongarch: Load FDT table into dram memory space
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
2022-11-03 12:38 ` [PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi Song Gao
2022-11-03 12:38 ` [PULL 2/7] hw/intc: Fix LoongArch extioi coreisr accessing Song Gao
@ 2022-11-03 12:38 ` Song Gao
2022-11-03 12:38 ` [PULL 4/7] hw/loongarch: Improve fdt for LoongArch virt machine Song Gao
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:38 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha, Xiaojuan Yang
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/virt.c | 18 +++++++++++-------
include/hw/loongarch/virt.h | 3 ---
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 4b595a9ea4..50e9829a94 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -159,7 +159,6 @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
2, base_mmio, 2, size_mmio);
g_free(nodename);
- qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
}
static void fdt_add_irqchip_node(LoongArchMachineState *lams)
@@ -656,6 +655,7 @@ static void loongarch_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
int i;
+ hwaddr fdt_base;
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -760,12 +760,16 @@ static void loongarch_init(MachineState *machine)
lams->machine_done.notify = virt_machine_done;
qemu_add_machine_init_done_notifier(&lams->machine_done);
fdt_add_pcie_node(lams);
-
- /* load fdt */
- MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
- memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
- memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
- rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
+ /*
+ * Since lowmem region starts from 0, FDT base address is located
+ * at 2 MiB to avoid NULL pointer access.
+ *
+ * Put the FDT into the memory map as a ROM image: this will ensure
+ * the FDT is copied again upon reset, even if addr points into RAM.
+ */
+ fdt_base = 2 * MiB;
+ qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
+ rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
}
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index 09f1c88ee5..45c383f5a7 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -28,9 +28,6 @@
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
-#define VIRT_FDT_BASE 0x1c400000
-#define VIRT_FDT_SIZE 0x100000
-
struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 4/7] hw/loongarch: Improve fdt for LoongArch virt machine
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
` (2 preceding siblings ...)
2022-11-03 12:38 ` [PULL 3/7] hw/loongarch: Load FDT table into dram memory space Song Gao
@ 2022-11-03 12:38 ` Song Gao
2022-11-03 12:38 ` [PULL 5/7] hw/loongarch: Add TPM device " Song Gao
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:38 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha, Xiaojuan Yang
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Add new items into LoongArch FDT, including rtc and uart info.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/virt.c | 31 +++++++++++++++++++++++++++++++
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 50e9829a94..afc1c8ac77 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -42,6 +42,35 @@
#include "hw/display/ramfb.h"
#include "hw/mem/pc-dimm.h"
+static void fdt_add_rtc_node(LoongArchMachineState *lams)
+{
+ char *nodename;
+ hwaddr base = VIRT_RTC_REG_BASE;
+ hwaddr size = VIRT_RTC_LEN;
+ MachineState *ms = MACHINE(lams);
+
+ nodename = g_strdup_printf("/rtc@%" PRIx64, base);
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
+ g_free(nodename);
+}
+
+static void fdt_add_uart_node(LoongArchMachineState *lams)
+{
+ char *nodename;
+ hwaddr base = VIRT_UART_BASE;
+ hwaddr size = VIRT_UART_SIZE;
+ MachineState *ms = MACHINE(lams);
+
+ nodename = g_strdup_printf("/serial@%" PRIx64, base);
+ qemu_fdt_add_subnode(ms->fdt, nodename);
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
+ g_free(nodename);
+}
+
static void create_fdt(LoongArchMachineState *lams)
{
MachineState *ms = MACHINE(lams);
@@ -422,6 +451,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
qdev_get_gpio_in(pch_pic,
VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ fdt_add_uart_node(lams);
/* Network init */
for (i = 0; i < nb_nics; i++) {
@@ -442,6 +472,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
qdev_get_gpio_in(pch_pic,
VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
+ fdt_add_rtc_node(lams);
pm_mem = g_new(MemoryRegion, 1);
memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index 9bd875ca8b..df7fa55a30 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -37,6 +37,7 @@
#define VIRT_PCI_IRQS 48
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
#define VIRT_UART_BASE 0x1fe001e0
+#define VIRT_UART_SIZE 0X100
#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 5/7] hw/loongarch: Add TPM device for LoongArch virt machine
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
` (3 preceding siblings ...)
2022-11-03 12:38 ` [PULL 4/7] hw/loongarch: Improve fdt for LoongArch virt machine Song Gao
@ 2022-11-03 12:38 ` Song Gao
2022-11-03 12:39 ` [PULL 6/7] target/loongarch: Add exception subcode Song Gao
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:38 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha, Xiaojuan Yang
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Add TPM device for LoongArch virt machine, including
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
to dynamic_sysbus_devices list.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/loongarch/acpi-build.c | 50 +++++++++++++++++++++++++++++++++++++--
hw/loongarch/virt.c | 4 ++++
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index 378a6d9d38..1d0e562435 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -31,6 +31,9 @@
#include "hw/acpi/generic_event_device.h"
#include "hw/pci-host/gpex.h"
+#include "sysemu/tpm.h"
+#include "hw/platform-bus.h"
+#include "hw/acpi/aml-build.h"
#define ACPI_BUILD_ALIGN_SIZE 0x1000
#define ACPI_BUILD_TABLE_SIZE 0x20000
@@ -275,6 +278,41 @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
acpi_dsdt_add_gpex(scope, &cfg);
}
+#ifdef CONFIG_TPM
+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
+{
+ PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
+ hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
+ SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
+ MemoryRegion *sbdev_mr;
+ hwaddr tpm_base;
+
+ if (!sbdev) {
+ return;
+ }
+
+ tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
+ assert(tpm_base != -1);
+
+ tpm_base += pbus_base;
+
+ sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
+
+ Aml *dev = aml_device("TPM0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+ aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs,
+ aml_memory32_fixed(tpm_base,
+ (uint32_t)memory_region_size(sbdev_mr),
+ AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+#endif
+
/* build DSDT */
static void
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
@@ -289,7 +327,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
build_uart_device_aml(dsdt);
build_pci_device_aml(dsdt, lams);
build_la_ged_aml(dsdt, machine);
-
+#ifdef CONFIG_TPM
+ acpi_dsdt_add_tpm(dsdt, lams);
+#endif
/* System State Package */
scope = aml_scope("\\");
pkg = aml_package(4);
@@ -358,7 +398,13 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id,
lams->oem_table_id);
}
-
+ /* TPM info */
+ if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_tpm2(tables_blob, tables->linker,
+ tables->tcpalog, lams->oem_id,
+ lams->oem_table_id);
+ }
/* Add tables supplied by user (if any) */
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
unsigned len = acpi_table_len(u);
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index afc1c8ac77..5e4c2790bf 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -41,6 +41,7 @@
#include "hw/platform-bus.h"
#include "hw/display/ramfb.h"
#include "hw/mem/pc-dimm.h"
+#include "sysemu/tpm.h"
static void fdt_add_rtc_node(LoongArchMachineState *lams)
{
@@ -960,6 +961,9 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
object_class_property_set_description(oc, "acpi",
"Enable ACPI");
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+#ifdef CONFIG_TPM
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
+#endif
}
static const TypeInfo loongarch_machine_types[] = {
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 6/7] target/loongarch: Add exception subcode
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
` (4 preceding siblings ...)
2022-11-03 12:38 ` [PULL 5/7] hw/loongarch: Add TPM device " Song Gao
@ 2022-11-03 12:39 ` Song Gao
2022-11-03 12:39 ` [PULL 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index Song Gao
2022-11-03 18:31 ` [PULL 0/7] loongarch-to-apply queue Stefan Hajnoczi
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:39 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha
We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
---
target/loongarch/cpu.c | 7 +++--
target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 49393d95d8..b28aaed5ba 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -220,7 +220,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
PC, (env->pc >> 2));
} else {
- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
+ EXCODE_MCODE(cause));
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
+ EXCODE_SUBCODE(cause));
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
@@ -257,7 +260,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
env->pc = env->CSR_TLBRENTRY;
} else {
env->pc = env->CSR_EENTRY;
- env->pc += cause * vec_size;
+ env->pc += EXCODE_MCODE(cause) * vec_size;
}
qemu_log_mask(CPU_LOG_INT,
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index dce999aaac..dbce176564 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -75,33 +75,37 @@ FIELD(FCSR0, CAUSE, 24, 5)
#define FP_DIV0 8
#define FP_INVALID 16
-#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
-#define EXCCODE_INT 0
-#define EXCCODE_PIL 1
-#define EXCCODE_PIS 2
-#define EXCCODE_PIF 3
-#define EXCCODE_PME 4
-#define EXCCODE_PNR 5
-#define EXCCODE_PNX 6
-#define EXCCODE_PPI 7
-#define EXCCODE_ADEF 8 /* Different exception subcode */
-#define EXCCODE_ADEM 8
-#define EXCCODE_ALE 9
-#define EXCCODE_BCE 10
-#define EXCCODE_SYS 11
-#define EXCCODE_BRK 12
-#define EXCCODE_INE 13
-#define EXCCODE_IPE 14
-#define EXCCODE_FPD 15
-#define EXCCODE_SXD 16
-#define EXCCODE_ASXD 17
-#define EXCCODE_FPE 18 /* Different exception subcode */
-#define EXCCODE_VFPE 18
-#define EXCCODE_WPEF 19 /* Different exception subcode */
-#define EXCCODE_WPEM 19
-#define EXCCODE_BTD 20
-#define EXCCODE_BTE 21
-#define EXCCODE_DBP 26 /* Reserved subcode used for debug */
+#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
+#define EXCODE_MCODE(code) ( (code) & 0x3f )
+#define EXCODE_SUBCODE(code) ( (code) >> 6 )
+
+#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
+#define EXCCODE_INT EXCODE(0, 0)
+#define EXCCODE_PIL EXCODE(1, 0)
+#define EXCCODE_PIS EXCODE(2, 0)
+#define EXCCODE_PIF EXCODE(3, 0)
+#define EXCCODE_PME EXCODE(4, 0)
+#define EXCCODE_PNR EXCODE(5, 0)
+#define EXCCODE_PNX EXCODE(6, 0)
+#define EXCCODE_PPI EXCODE(7, 0)
+#define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */
+#define EXCCODE_ADEM EXCODE(8, 1)
+#define EXCCODE_ALE EXCODE(9, 0)
+#define EXCCODE_BCE EXCODE(10, 0)
+#define EXCCODE_SYS EXCODE(11, 0)
+#define EXCCODE_BRK EXCODE(12, 0)
+#define EXCCODE_INE EXCODE(13, 0)
+#define EXCCODE_IPE EXCODE(14, 0)
+#define EXCCODE_FPD EXCODE(15, 0)
+#define EXCCODE_SXD EXCODE(16, 0)
+#define EXCCODE_ASXD EXCODE(17, 0)
+#define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */
+#define EXCCODE_VFPE EXCODE(18, 1)
+#define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */
+#define EXCCODE_WPEM EXCODE(19, 1)
+#define EXCCODE_BTD EXCODE(20, 0)
+#define EXCCODE_BTE EXCODE(21, 0)
+#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
/* cpucfg[0] bits */
FIELD(CPUCFG0, PRID, 0, 32)
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
` (5 preceding siblings ...)
2022-11-03 12:39 ` [PULL 6/7] target/loongarch: Add exception subcode Song Gao
@ 2022-11-03 12:39 ` Song Gao
2022-11-03 18:31 ` [PULL 0/7] loongarch-to-apply queue Stefan Hajnoczi
7 siblings, 0 replies; 9+ messages in thread
From: Song Gao @ 2022-11-03 12:39 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, stefanha
When the address is invalid address, We should set exception_index
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
Otherwise, The system enters an infinite loop. e.g:
run test.c on system mode
test.c:
#include<stdio.h>
void (*func)(int *);
int main()
{
int i = 8;
void *ptr = (void *)0x4000000000000000;
func = ptr;
func(&i);
return 0;
}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
---
target/loongarch/cpu.c | 1 +
target/loongarch/tlb_helper.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b28aaed5ba..1512664214 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -177,6 +177,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
}
QEMU_FALLTHROUGH;
case EXCCODE_PIF:
+ case EXCCODE_ADEF:
cause = cs->exception_index;
update_badinstr = 0;
break;
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 610b6d123c..d2f8fb0c60 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -229,7 +229,8 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
switch (tlb_error) {
default:
case TLBRET_BADADDR:
- cs->exception_index = EXCCODE_ADEM;
+ cs->exception_index = access_type == MMU_INST_FETCH
+ ? EXCCODE_ADEF : EXCCODE_ADEM;
break;
case TLBRET_NOMATCH:
/* No TLB match for a mapped address */
@@ -643,7 +644,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPULoongArchState *env = &cpu->env;
hwaddr physical;
int prot;
- int ret = TLBRET_BADADDR;
+ int ret;
/* Data access */
ret = get_physical_address(env, &physical, &prot, address,
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PULL 0/7] loongarch-to-apply queue
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
` (6 preceding siblings ...)
2022-11-03 12:39 ` [PULL 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index Song Gao
@ 2022-11-03 18:31 ` Stefan Hajnoczi
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Hajnoczi @ 2022-11-03 18:31 UTC (permalink / raw)
To: Song Gao; +Cc: qemu-devel, richard.henderson
The cross-win32-system GitLab CI job fails to build with the following error:
i686-w64-mingw32-gcc -m32 -Ilibqemu-loongarch64-softmmu.fa.p -I. -I..
-Itarget/loongarch -I../target/loongarch -I../dtc/libfdt -Iqapi
-Itrace -Iui -Iui/shader
-I/usr/i686-w64-mingw32/sys-root/mingw/include/pixman-1
-I/usr/i686-w64-mingw32/sys-root/mingw/include/glib-2.0
-I/usr/i686-w64-mingw32/sys-root/mingw/lib/glib-2.0/include
-fdiagnostics-color=auto -Wall -Winvalid-pch -Werror -std=gnu11 -O2 -g
-iquote . -iquote /builds/qemu-project/qemu -iquote
/builds/qemu-project/qemu/include -iquote
/builds/qemu-project/qemu/tcg/i386 -mms-bitfields -U_FORTIFY_SOURCE
-D_FORTIFY_SOURCE=2 -fno-pie -no-pie -D_GNU_SOURCE
-D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes
-Wredundant-decls -Wundef -Wwrite-strings -Wmissing-prototypes
-fno-strict-aliasing -fno-common -fwrapv -Wold-style-declaration
-Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k
-Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs
-Wendif-labels -Wexpansion-to-defined -Wimplicit-fallthrough=2
-Wno-missing-include-dirs -Wno-shift-negative-value -Wno-psabi
-fstack-protector-strong -DNEED_CPU_H
'-DCONFIG_TARGET="loongarch64-softmmu-config-target.h"'
'-DCONFIG_DEVICES="loongarch64-softmmu-config-devices.h"' -MD -MQ
libqemu-loongarch64-softmmu.fa.p/hw_loongarch_acpi-build.c.obj -MF
libqemu-loongarch64-softmmu.fa.p/hw_loongarch_acpi-build.c.obj.d -o
libqemu-loongarch64-softmmu.fa.p/hw_loongarch_acpi-build.c.obj -c
../hw/loongarch/acpi-build.c
../hw/loongarch/acpi-build.c: In function 'acpi_build':
../hw/loongarch/acpi-build.c:402:9: error: implicit declaration of
function 'tpm_get_version' [-Werror=implicit-function-declaration]
402 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
| ^~~~~~~~~~~~~~~
../hw/loongarch/acpi-build.c:402:9: error: nested extern declaration
of 'tpm_get_version' [-Werror=nested-externs]
../hw/loongarch/acpi-build.c:402:25: error: implicit declaration of
function 'tpm_find' [-Werror=implicit-function-declaration]
402 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
| ^~~~~~~~
../hw/loongarch/acpi-build.c:402:25: error: nested extern declaration
of 'tpm_find' [-Werror=nested-externs]
../hw/loongarch/acpi-build.c:402:40: error: 'TPM_VERSION_2_0'
undeclared (first use in this function); did you mean 'TP_VERSION'?
402 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
| ^~~~~~~~~~~~~~~
| TP_VERSION
../hw/loongarch/acpi-build.c:402:40: note: each undeclared identifier
is reported only once for each function it appears in
https://gitlab.com/qemu-project/qemu/-/jobs/3270049630
Stefan
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-11-03 18:34 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-03 12:38 [PULL 0/7] loongarch-to-apply queue Song Gao
2022-11-03 12:38 ` [PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi Song Gao
2022-11-03 12:38 ` [PULL 2/7] hw/intc: Fix LoongArch extioi coreisr accessing Song Gao
2022-11-03 12:38 ` [PULL 3/7] hw/loongarch: Load FDT table into dram memory space Song Gao
2022-11-03 12:38 ` [PULL 4/7] hw/loongarch: Improve fdt for LoongArch virt machine Song Gao
2022-11-03 12:38 ` [PULL 5/7] hw/loongarch: Add TPM device " Song Gao
2022-11-03 12:39 ` [PULL 6/7] target/loongarch: Add exception subcode Song Gao
2022-11-03 12:39 ` [PULL 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index Song Gao
2022-11-03 18:31 ` [PULL 0/7] loongarch-to-apply queue Stefan Hajnoczi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).