* [PULL v2 00/12] tcg patch queue
@ 2023-05-02 20:18 Richard Henderson
2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson
0 siblings, 2 replies; 6+ messages in thread
From: Richard Henderson @ 2023-05-02 20:18 UTC (permalink / raw)
To: qemu-devel
The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
----------------------------------------------------------------
Misc tcg-related patch queue.
v2: Update bitops.h rotate patch.
----------------------------------------------------------------
Dickon Hood (1):
qemu/bitops.h: Limit rotate amounts
Kiran Ostrolenk (1):
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
Nazar Kazakov (2):
tcg: Add tcg_gen_gvec_andcs
tcg: Add tcg_gen_gvec_rotrs
Richard Henderson (7):
softmmu: Tidy dirtylimit_dirty_ring_full_time
qemu/int128: Re-shuffle Int128Alias members
migration/xbzrle: Use __attribute__((target)) for avx512
accel/tcg: Add cpu_ld*_code_mmu
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
tcg/mips: Conditionalize tcg_out_exts_i32_i64
tcg: Introduce tcg_out_movext2
Weiwei Li (1):
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
meson.build | 5 +--
accel/tcg/tcg-runtime.h | 1 +
include/exec/cpu_ldst.h | 9 ++++++
include/qemu/bitops.h | 16 +++++-----
include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++
include/qemu/int128.h | 4 +--
include/tcg/tcg-op-gvec.h | 4 +++
accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++
accel/tcg/tcg-runtime-gvec.c | 11 +++++++
accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++
migration/xbzrle.c | 9 +++---
softmmu/dirtylimit.c | 15 ++++++---
tcg/tcg-op-gvec.c | 28 ++++++++++++++++
tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++---
tcg/arm/tcg-target.c.inc | 44 +++++++++++--------------
tcg/i386/tcg-target.c.inc | 19 +++++------
tcg/loongarch64/tcg-target.c.inc | 4 ++-
tcg/mips/tcg-target.c.inc | 4 ++-
18 files changed, 339 insertions(+), 68 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread* [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts 2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson @ 2023-05-02 20:18 ` Richard Henderson 2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson 1 sibling, 0 replies; 6+ messages in thread From: Richard Henderson @ 2023-05-02 20:18 UTC (permalink / raw) To: qemu-devel; +Cc: Dickon Hood From: Dickon Hood <dickon.hood@codethink.co.uk> Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk> [rth: Mask shifts in both directions.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/qemu/bitops.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 03213ce952..cb3526d1f4 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -218,7 +218,7 @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr, */ static inline uint8_t rol8(uint8_t word, unsigned int shift) { - return (word << shift) | (word >> ((8 - shift) & 7)); + return (word << (shift & 7)) | (word >> (-shift & 7)); } /** @@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift) */ static inline uint8_t ror8(uint8_t word, unsigned int shift) { - return (word >> shift) | (word << ((8 - shift) & 7)); + return (word >> (shift & 7)) | (word << (-shift & 7)); } /** @@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift) */ static inline uint16_t rol16(uint16_t word, unsigned int shift) { - return (word << shift) | (word >> ((16 - shift) & 15)); + return (word << (shift & 15)) | (word >> (-shift & 15)); } /** @@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift) */ static inline uint16_t ror16(uint16_t word, unsigned int shift) { - return (word >> shift) | (word << ((16 - shift) & 15)); + return (word >> (shift & 15)) | (word << (-shift & 15)); } /** @@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift) */ static inline uint32_t rol32(uint32_t word, unsigned int shift) { - return (word << shift) | (word >> ((32 - shift) & 31)); + return (word << (shift & 31)) | (word >> (-shift & 31)); } /** @@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift) */ static inline uint32_t ror32(uint32_t word, unsigned int shift) { - return (word >> shift) | (word << ((32 - shift) & 31)); + return (word >> (shift & 31)) | (word << (-shift & 31)); } /** @@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift) */ static inline uint64_t rol64(uint64_t word, unsigned int shift) { - return (word << shift) | (word >> ((64 - shift) & 63)); + return (word << (shift & 63)) | (word >> (-shift & 63)); } /** @@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift) */ static inline uint64_t ror64(uint64_t word, unsigned int shift) { - return (word >> shift) | (word << ((64 - shift) & 63)); + return (word >> (shift & 63)) | (word << (-shift & 63)); } /** -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PULL v2 00/12] tcg patch queue 2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson 2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson @ 2023-05-03 6:26 ` Richard Henderson 1 sibling, 0 replies; 6+ messages in thread From: Richard Henderson @ 2023-05-03 6:26 UTC (permalink / raw) To: qemu-devel On 5/2/23 21:18, Richard Henderson wrote: > The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43: > > Merge tag 'pull-target-arm-20230502-2' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100) > > are available in the Git repository at: > > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2 > > for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83: > > tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700) > > ---------------------------------------------------------------- > Misc tcg-related patch queue. > > v2: Update bitops.h rotate patch. Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PULL v2 00/12] tcg patch queue
@ 2019-10-28 14:59 Richard Henderson
2019-10-28 17:20 ` no-reply
2019-10-29 15:32 ` Peter Maydell
0 siblings, 2 replies; 6+ messages in thread
From: Richard Henderson @ 2019-10-28 14:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
V2 fixes a build problem that affected win32.
r~
The following changes since commit 187f35512106501fe9a11057f4d8705431e0026d:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-251019-3' into staging (2019-10-26 10:13:48 +0100)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-20191028
for you to fetch changes up to fe9b676fb3160496b4b2bf0c57d33be724bf04c3:
translate-all: Remove tb_alloc (2019-10-28 10:35:23 +0100)
----------------------------------------------------------------
Improvements for TARGET_PAGE_BITS_VARY
Fix for TCI ld16u_i64.
Fix for segv on icount execute from i/o memory.
Two misc cleanups.
----------------------------------------------------------------
Alex Bennée (1):
cputlb: ensure _cmmu helper functions follow the naming standard
Clement Deschamps (1):
translate-all: fix uninitialized tb->orig_tb
Richard Henderson (8):
exec: Split out variable page size support to exec-vary.c
configure: Detect compiler support for __attribute__((alias))
exec: Use const alias for TARGET_PAGE_BITS_VARY
exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG
exec: Promote TARGET_PAGE_MASK to target_long
exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY
cputlb: Fix tlb_vaddr_to_host
translate-all: Remove tb_alloc
Stefan Weil (1):
tci: Add implementation for INDEX_op_ld16u_i64
Wei Yang (1):
cpu: use ROUND_UP() to define xxx_PAGE_ALIGN
Makefile.target | 2 +-
include/exec/cpu-all.h | 33 ++++++++----
include/exec/cpu_ldst_template.h | 4 +-
include/qemu-common.h | 6 +++
tcg/tcg.h | 20 +++++---
accel/tcg/cputlb.c | 26 ++++++++--
accel/tcg/translate-all.c | 21 ++------
exec-vary.c | 108 +++++++++++++++++++++++++++++++++++++++
exec.c | 34 ------------
target/cris/translate_v10.inc.c | 3 +-
tcg/tci.c | 15 ++++++
configure | 19 +++++++
12 files changed, 214 insertions(+), 77 deletions(-)
create mode 100644 exec-vary.c
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PULL v2 00/12] tcg patch queue 2019-10-28 14:59 Richard Henderson @ 2019-10-28 17:20 ` no-reply 2019-10-29 15:32 ` Peter Maydell 1 sibling, 0 replies; 6+ messages in thread From: no-reply @ 2019-10-28 17:20 UTC (permalink / raw) To: richard.henderson; +Cc: peter.maydell, qemu-devel Patchew URL: https://patchew.org/QEMU/20191028145937.10914-1-richard.henderson@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PULL v2 00/12] tcg patch queue Type: series Message-id: 20191028145937.10914-1-richard.henderson@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' dddd2c9 translate-all: Remove tb_alloc ce663b2 translate-all: fix uninitialized tb->orig_tb 90c3eba cputlb: Fix tlb_vaddr_to_host d2b8cbd exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY 4ce23d0 exec: Promote TARGET_PAGE_MASK to target_long 7d2699f exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG b5f712d exec: Use const alias for TARGET_PAGE_BITS_VARY 8d1e9d0 configure: Detect compiler support for __attribute__((alias)) cad9025 exec: Split out variable page size support to exec-vary.c b290db4 cpu: use ROUND_UP() to define xxx_PAGE_ALIGN 60dbf14 cputlb: ensure _cmmu helper functions follow the naming standard cdaeeaf tci: Add implementation for INDEX_op_ld16u_i64 === OUTPUT BEGIN === 1/12 Checking commit cdaeeaf401d2 (tci: Add implementation for INDEX_op_ld16u_i64) 2/12 Checking commit 60dbf140a9ab (cputlb: ensure _cmmu helper functions follow the naming standard) 3/12 Checking commit b290db446298 (cpu: use ROUND_UP() to define xxx_PAGE_ALIGN) 4/12 Checking commit cad9025d89cb (exec: Split out variable page size support to exec-vary.c) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 total: 0 errors, 1 warnings, 125 lines checked Patch 4/12 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 5/12 Checking commit 8d1e9d07c296 (configure: Detect compiler support for __attribute__((alias))) 6/12 Checking commit b5f712d02e4f (exec: Use const alias for TARGET_PAGE_BITS_VARY) ERROR: externs should be avoided in .c files #66: FILE: exec-vary.c:57: +extern const TargetPageBits target_page total: 1 errors, 0 warnings, 109 lines checked Patch 6/12 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 7/12 Checking commit 7d2699f55dd2 (exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG) 8/12 Checking commit 4ce23d02a238 (exec: Promote TARGET_PAGE_MASK to target_long) 9/12 Checking commit d2b8cbd91572 (exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY) 10/12 Checking commit 90c3eba34f5f (cputlb: Fix tlb_vaddr_to_host) 11/12 Checking commit ce663b281c78 (translate-all: fix uninitialized tb->orig_tb) 12/12 Checking commit dddd2c942dd5 (translate-all: Remove tb_alloc) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20191028145937.10914-1-richard.henderson@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PULL v2 00/12] tcg patch queue 2019-10-28 14:59 Richard Henderson 2019-10-28 17:20 ` no-reply @ 2019-10-29 15:32 ` Peter Maydell 1 sibling, 0 replies; 6+ messages in thread From: Peter Maydell @ 2019-10-29 15:32 UTC (permalink / raw) To: Richard Henderson; +Cc: QEMU Developers On Mon, 28 Oct 2019 at 14:59, Richard Henderson <richard.henderson@linaro.org> wrote: > > V2 fixes a build problem that affected win32. > > > r~ > > > The following changes since commit 187f35512106501fe9a11057f4d8705431e0026d: > > Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-251019-3' into staging (2019-10-26 10:13:48 +0100) > > are available in the Git repository at: > > https://github.com/rth7680/qemu.git tags/pull-tcg-20191028 > > for you to fetch changes up to fe9b676fb3160496b4b2bf0c57d33be724bf04c3: > > translate-all: Remove tb_alloc (2019-10-28 10:35:23 +0100) > > ---------------------------------------------------------------- > Improvements for TARGET_PAGE_BITS_VARY > Fix for TCI ld16u_i64. > Fix for segv on icount execute from i/o memory. > Two misc cleanups. > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 6+ messages in thread
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