* [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c
@ 2023-09-20 11:20 Daniel Henrique Barboza
2023-09-20 11:20 ` [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
` (19 more replies)
0 siblings, 20 replies; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
Hi,
In this version we changed patch 10 (remove kvm-stub.c) as suggested by
Phil to not include non-KVM stubs in kvm_riscv.h. A change in patch 05
requested by Zhiwei was also made.
Patches based on Alistair's riscv-to-apply.next.
Patches missing acks: patch 10
Changes from v2:
- patch 05:
- remove riscv_cpu_add_user_properties() from riscv_host_cpu_init()
- patch 10:
- do not add non-KVM stubs in kvm_riscv.h
- v2 link: https://lore.kernel.org/qemu-riscv/20230906091647.1667171-1-dbarboza@ventanamicro.com/
Daniel Henrique Barboza (19):
target/riscv: introduce TCG AccelCPUClass
target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
target/riscv: move riscv_tcg_ops to tcg-cpu.c
target/riscv/cpu.c: add .instance_post_init()
target/riscv: move 'host' CPU declaration to kvm.c
target/riscv/cpu.c: mark extensions arrays as 'const'
target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
target/riscv: make riscv_add_satp_mode_properties() public
target/riscv: remove kvm-stub.c
target/riscv: introduce KVM AccelCPUClass
target/riscv: move KVM only files to kvm subdir
target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
target/riscv/cpu.c: export set_misa()
target/riscv/tcg: introduce tcg_cpu_instance_init()
target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
target/riscv/cpu.c: export isa_edata_arr[]
target/riscv/cpu: move priv spec functions to tcg-cpu.c
hw/intc/riscv_aplic.c | 2 +-
hw/riscv/virt.c | 2 +-
target/riscv/cpu.c | 988 ++------------------------
target/riscv/cpu.h | 30 +-
target/riscv/csr.c | 1 +
target/riscv/kvm-stub.c | 30 -
target/riscv/{kvm.c => kvm/kvm-cpu.c} | 120 +++-
target/riscv/{ => kvm}/kvm_riscv.h | 4 -
target/riscv/kvm/meson.build | 1 +
target/riscv/meson.build | 4 +-
target/riscv/tcg/meson.build | 2 +
target/riscv/tcg/tcg-cpu.c | 883 +++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.h | 27 +
13 files changed, 1113 insertions(+), 981 deletions(-)
delete mode 100644 target/riscv/kvm-stub.c
rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (91%)
rename target/riscv/{ => kvm}/kvm_riscv.h (89%)
create mode 100644 target/riscv/kvm/meson.build
create mode 100644 target/riscv/tcg/meson.build
create mode 100644 target/riscv/tcg/tcg-cpu.c
create mode 100644 target/riscv/tcg/tcg-cpu.h
--
2.41.0
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:24 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
` (18 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitting
acceleration specific code from cpu.c to its own file will help to
declutter the existing code and it will also make it easier to support
KVM/TCG only builds in the future.
We'll start by adding a new subdir called 'tcg' and a new file called
'tcg-cpu.c'. This file will be used to introduce a new accelerator class
for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
code in its file instead of using 'cpu.c' for everything. This design is
inpired by the work Claudio Fontana did in x86 a few years ago in commit
f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass").
To avoid moving too much code at once we'll start by adding the new file
and TCG AccelCPUClass declaration. The 'class_init' from the accel class
will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
doing it.
'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
to deal with moving code and files around right now. We'll focus on
decoupling the realize() logic first.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 5 +---
target/riscv/cpu.h | 4 +++
target/riscv/meson.build | 2 ++
target/riscv/tcg/meson.build | 2 ++
target/riscv/tcg/tcg-cpu.c | 58 ++++++++++++++++++++++++++++++++++++
5 files changed, 67 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/tcg/meson.build
create mode 100644 target/riscv/tcg/tcg-cpu.c
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2644638b11..e72c49c881 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2288,9 +2288,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-#include "hw/core/tcg-cpu-ops.h"
-
-static const struct TCGCPUOps riscv_tcg_ops = {
+const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.restore_state_to_opc = riscv_restore_state_to_opc,
@@ -2449,7 +2447,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
- cc->tcg_ops = &riscv_tcg_ops;
object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
cpu_set_mvendorid, NULL, NULL);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d6cfb07ea..16a2dfa8c7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -707,6 +707,10 @@ enum riscv_pmu_event_idx {
RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
};
+/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
+#include "hw/core/tcg-cpu-ops.h"
+extern const struct TCGCPUOps riscv_tcg_ops;
+
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 660078bda1..f0486183fa 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -38,5 +38,7 @@ riscv_system_ss.add(files(
'riscv-qmp-cmds.c',
))
+subdir('tcg')
+
target_arch += {'riscv': riscv_ss}
target_softmmu_arch += {'riscv': riscv_system_ss}
diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
new file mode 100644
index 0000000000..061df3d74a
--- /dev/null
+++ b/target/riscv/tcg/meson.build
@@ -0,0 +1,2 @@
+riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'tcg-cpu.c'))
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
new file mode 100644
index 0000000000..0326cead0d
--- /dev/null
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -0,0 +1,58 @@
+/*
+ * riscv TCG cpu class initialization
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/accel.h"
+#include "hw/core/accel-cpu.h"
+
+static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
+{
+ /*
+ * All cpus use the same set of operations.
+ * riscv_tcg_ops is being imported from cpu.c for now.
+ */
+ cc->tcg_ops = &riscv_tcg_ops;
+}
+
+static void tcg_cpu_class_init(CPUClass *cc)
+{
+ cc->init_accel_cpu = tcg_cpu_init_ops;
+}
+
+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_class_init = tcg_cpu_class_init;
+}
+
+static const TypeInfo tcg_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = tcg_cpu_accel_class_init,
+ .abstract = true,
+};
+
+static void tcg_cpu_accel_register_types(void)
+{
+ type_register_static(&tcg_cpu_accel_type_info);
+}
+type_init(tcg_cpu_accel_register_types);
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-20 11:20 ` [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:29 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
` (17 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
realize() path during the common riscv_cpu_realize(), making it a good
choice to start moving TCG exclusive code to tcg-cpu.c.
Rename it to tcg_cpu_realizefn() and assign it as a implementation of
accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
approach with KVM in the near future.
riscv_cpu_validate_set_extensions() is too big and with too many
dependencies to be moved in this same patch. We'll do that next.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 128 -----------------------------------
target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
2 files changed, 133 insertions(+), 128 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e72c49c881..030629294f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -23,9 +23,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "cpu_vendorid.h"
-#include "pmu.h"
#include "internals.h"
-#include "time_helper.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
@@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
}
}
-static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
-{
- CPURISCVState *env = &cpu->env;
- int priv_version = -1;
-
- if (cpu->cfg.priv_spec) {
- if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
- priv_version = PRIV_VERSION_1_12_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
- priv_version = PRIV_VERSION_1_11_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
- priv_version = PRIV_VERSION_1_10_0;
- } else {
- error_setg(errp,
- "Unsupported privilege spec version '%s'",
- cpu->cfg.priv_spec);
- return;
- }
-
- env->priv_ver = priv_version;
- }
-}
-
static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
{
CPURISCVState *env = &cpu->env;
@@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
}
}
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
-{
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
- CPUClass *cc = CPU_CLASS(mcc);
- CPURISCVState *env = &cpu->env;
-
- /* Validate that MISA_MXL is set properly. */
- switch (env->misa_mxl_max) {
-#ifdef TARGET_RISCV64
- case MXL_RV64:
- case MXL_RV128:
- cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
- break;
-#endif
- case MXL_RV32:
- cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
- default:
- g_assert_not_reached();
- }
-
- if (env->misa_mxl_max != env->misa_mxl) {
- error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
- return;
- }
-}
-
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
#endif
}
-static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
-{
- if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
- error_setg(errp, "H extension requires priv spec 1.12.0");
- return;
- }
-}
-
-static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
-{
- RISCVCPU *cpu = RISCV_CPU(dev);
- CPURISCVState *env = &cpu->env;
- Error *local_err = NULL;
-
- if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
- error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
- return;
- }
-
- riscv_cpu_validate_misa_mxl(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
- riscv_cpu_validate_priv_spec(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
- riscv_cpu_validate_misa_priv(env, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
- if (cpu->cfg.epmp && !cpu->cfg.pmp) {
- /*
- * Enhanced PMP should only be available
- * on harts with PMP support
- */
- error_setg(errp, "Invalid configuration: EPMP requires PMP support");
- return;
- }
-
- riscv_cpu_validate_set_extensions(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
-#ifndef CONFIG_USER_ONLY
- CPU(dev)->tcg_cflags |= CF_PCREL;
-
- if (cpu->cfg.ext_sstc) {
- riscv_timer_init(cpu);
- }
-
- if (cpu->cfg.pmu_num) {
- if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- riscv_pmu_timer_cb, cpu);
- }
- }
-#endif
-}
-
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- if (tcg_enabled()) {
- riscv_cpu_realize_tcg(dev, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
- }
-
riscv_cpu_finalize_features(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 0326cead0d..f47dc2064f 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -18,10 +18,142 @@
*/
#include "qemu/osdep.h"
+#include "exec/exec-all.h"
#include "cpu.h"
+#include "pmu.h"
+#include "time_helper.h"
+#include "qapi/error.h"
#include "qemu/accel.h"
#include "hw/core/accel-cpu.h"
+
+static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
+{
+ if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
+ error_setg(errp, "H extension requires priv spec 1.12.0");
+ return;
+ }
+}
+
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ CPUClass *cc = CPU_CLASS(mcc);
+ CPURISCVState *env = &cpu->env;
+
+ /* Validate that MISA_MXL is set properly. */
+ switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ case MXL_RV128:
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+ break;
+#endif
+ case MXL_RV32:
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (env->misa_mxl_max != env->misa_mxl) {
+ error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
+ return;
+ }
+}
+
+static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+{
+ CPURISCVState *env = &cpu->env;
+ int priv_version = -1;
+
+ if (cpu->cfg.priv_spec) {
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+ priv_version = PRIV_VERSION_1_12_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+ priv_version = PRIV_VERSION_1_11_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+ priv_version = PRIV_VERSION_1_10_0;
+ } else {
+ error_setg(errp,
+ "Unsupported privilege spec version '%s'",
+ cpu->cfg.priv_spec);
+ return;
+ }
+
+ env->priv_ver = priv_version;
+ }
+}
+
+/*
+ * We'll get here via the following path:
+ *
+ * riscv_cpu_realize()
+ * -> cpu_exec_realizefn()
+ * -> tcg_cpu_realizefn() (via accel_cpu_realizefn())
+ */
+static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ Error *local_err = NULL;
+
+ if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
+ error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
+ return false;
+ }
+
+ riscv_cpu_validate_misa_mxl(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return false;
+ }
+
+ riscv_cpu_validate_priv_spec(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return false;
+ }
+
+ riscv_cpu_validate_misa_priv(env, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return false;
+ }
+
+ if (cpu->cfg.epmp && !cpu->cfg.pmp) {
+ /*
+ * Enhanced PMP should only be available
+ * on harts with PMP support
+ */
+ error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+ return false;
+ }
+
+ riscv_cpu_validate_set_extensions(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return false;
+ }
+
+#ifndef CONFIG_USER_ONLY
+ CPU(cs)->tcg_cflags |= CF_PCREL;
+
+ if (cpu->cfg.ext_sstc) {
+ riscv_timer_init(cpu);
+ }
+
+ if (cpu->cfg.pmu_num) {
+ if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_pmu_timer_cb, cpu);
+ }
+ }
+#endif
+
+ return true;
+}
+
static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/*
@@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
acc->cpu_class_init = tcg_cpu_class_init;
+ acc->cpu_realizefn = tcg_cpu_realizefn;
}
static const TypeInfo tcg_cpu_accel_type_info = {
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-20 11:20 ` [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-09-20 11:20 ` [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:32 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
` (16 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
This function is the core of the RISC-V validations for TCG CPUs, and it
has a lot going on.
Functions in cpu.c were made public to allow them to be used by the KVM
accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
hard to move it to another file due to its dependency with isa_edata_arr[]
array, thus make it public and use it as is for now.
riscv_cpu_validate_set_extensions() is kept public because it's used by
csr.c in write_misa().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 361 +------------------------------------
target/riscv/cpu.h | 8 +-
target/riscv/csr.c | 1 +
target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.h | 27 +++
5 files changed, 397 insertions(+), 357 deletions(-)
create mode 100644 target/riscv/tcg/tcg-cpu.h
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 030629294f..7215a29324 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] = {
/* Hash that stores user set extensions */
static GHashTable *multi_ext_user_opts;
-static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
{
bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
return *ext_enabled;
}
-static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
- bool en)
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
{
bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
*ext_enabled = en;
}
-static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
{
int i;
@@ -193,38 +192,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
g_assert_not_reached();
}
-static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
{
return g_hash_table_contains(multi_ext_user_opts,
GUINT_TO_POINTER(ext_offset));
}
-static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
- bool value)
-{
- CPURISCVState *env = &cpu->env;
- bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
- int min_version;
-
- if (prev_val == value) {
- return;
- }
-
- if (cpu_cfg_ext_is_user_set(ext_offset)) {
- return;
- }
-
- if (value && env->priv_ver != PRIV_VERSION_LATEST) {
- /* Do not enable it if priv_ver is older than min_version */
- min_version = cpu_cfg_ext_get_min_version(ext_offset);
- if (env->priv_ver < min_version) {
- return;
- }
- }
-
- isa_ext_update_enabled(cpu, ext_offset, value);
-}
-
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -1023,46 +996,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
-static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
- Error **errp)
-{
- if (!is_power_of_2(cfg->vlen)) {
- error_setg(errp, "Vector extension VLEN must be power of 2");
- return;
- }
- if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
- error_setg(errp,
- "Vector extension implementation only supports VLEN "
- "in the range [128, %d]", RV_VLEN_MAX);
- return;
- }
- if (!is_power_of_2(cfg->elen)) {
- error_setg(errp, "Vector extension ELEN must be power of 2");
- return;
- }
- if (cfg->elen > 64 || cfg->elen < 8) {
- error_setg(errp,
- "Vector extension implementation only supports ELEN "
- "in the range [8, 64]");
- return;
- }
- if (cfg->vext_spec) {
- if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
- env->vext_ver = VEXT_VERSION_1_00_0;
- } else {
- error_setg(errp, "Unsupported vector spec version '%s'",
- cfg->vext_spec);
- return;
- }
- } else if (env->vext_ver == 0) {
- qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-
- env->vext_ver = VEXT_VERSION_1_00_0;
- }
-}
-
-static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
{
CPURISCVState *env = &cpu->env;
int i;
@@ -1086,291 +1020,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
}
}
-/*
- * Check consistency between chosen extensions while setting
- * cpu->cfg accordingly.
- */
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-{
- CPURISCVState *env = &cpu->env;
- Error *local_err = NULL;
-
- /* Do some ISA extension error checking */
- if (riscv_has_ext(env, RVG) &&
- !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
- riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
- riscv_has_ext(env, RVD) &&
- cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
-
- if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
- !cpu->cfg.ext_icsr) {
- error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
- return;
- }
-
- if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
- !cpu->cfg.ext_ifencei) {
- error_setg(errp, "RVG requires Zifencei but user set "
- "Zifencei to false");
- return;
- }
-
- warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
-
- env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
- env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
- }
-
- if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
- error_setg(errp,
- "I and E extensions are incompatible");
- return;
- }
-
- if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
- error_setg(errp,
- "Either I or E extension must be set");
- return;
- }
-
- if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
- error_setg(errp,
- "Setting S extension without U extension is illegal");
- return;
- }
-
- if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
- error_setg(errp,
- "H depends on an I base integer ISA with 32 x registers");
- return;
- }
-
- if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
- error_setg(errp, "H extension implicitly requires S-mode");
- return;
- }
-
- if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
- error_setg(errp, "F extension requires Zicsr");
- return;
- }
-
- if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
- error_setg(errp, "Zawrs extension requires A extension");
- return;
- }
-
- if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
- error_setg(errp, "Zfa extension requires F extension");
- return;
- }
-
- if (cpu->cfg.ext_zfh) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
- }
-
- if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
- error_setg(errp, "Zfh/Zfhmin extensions require F extension");
- return;
- }
-
- if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
- error_setg(errp, "Zfbfmin extension depends on F extension");
- return;
- }
-
- if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
- error_setg(errp, "D extension requires F extension");
- return;
- }
-
- if (riscv_has_ext(env, RVV)) {
- riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return;
- }
-
- /* The V vector extension depends on the Zve64d extension */
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
- }
-
- /* The Zve64d extension depends on the Zve64f extension */
- if (cpu->cfg.ext_zve64d) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
- }
-
- /* The Zve64f extension depends on the Zve32f extension */
- if (cpu->cfg.ext_zve64f) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
- }
-
- if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
- error_setg(errp, "Zve64d/V extensions require D extension");
- return;
- }
-
- if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
- error_setg(errp, "Zve32f/Zve64f extensions require F extension");
- return;
- }
-
- if (cpu->cfg.ext_zvfh) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
- }
-
- if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
- error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
- return;
- }
-
- if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
- error_setg(errp, "Zvfh extensions requires Zfhmin extension");
- return;
- }
-
- if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
- error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
- return;
- }
-
- if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
- error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
- return;
- }
-
- if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
- error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
- return;
- }
-
- /* Set the ISA extensions, checks should have happened above */
- if (cpu->cfg.ext_zhinx) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- }
-
- if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
- error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
- return;
- }
-
- if (cpu->cfg.ext_zfinx) {
- if (!cpu->cfg.ext_icsr) {
- error_setg(errp, "Zfinx extension requires Zicsr");
- return;
- }
- if (riscv_has_ext(env, RVF)) {
- error_setg(errp,
- "Zfinx cannot be supported together with F extension");
- return;
- }
- }
-
- if (cpu->cfg.ext_zce) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
- if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
- }
- }
-
- /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
- if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
- }
- if (riscv_has_ext(env, RVD)) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
- }
- }
-
- if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
- error_setg(errp, "Zcf extension is only relevant to RV32");
- return;
- }
-
- if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
- error_setg(errp, "Zcf extension requires F extension");
- return;
- }
-
- if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
- error_setg(errp, "Zcd extension requires D extension");
- return;
- }
-
- if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
- cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
- error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
- "extension");
- return;
- }
-
- if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
- error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
- "Zcd extension");
- return;
- }
-
- if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
- error_setg(errp, "Zcmt extension requires Zicsr extension");
- return;
- }
-
- /*
- * In principle Zve*x would also suffice here, were they supported
- * in qemu
- */
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
- cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
- !cpu->cfg.ext_zve32f) {
- error_setg(errp,
- "Vector crypto extensions require V or Zve* extensions");
- return;
- }
-
- if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
- error_setg(
- errp,
- "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
- return;
- }
-
- if (cpu->cfg.ext_zk) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
- }
-
- if (cpu->cfg.ext_zkn) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
- }
-
- if (cpu->cfg.ext_zks) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
- }
-
- /*
- * Disable isa extensions based on priv spec after we
- * validated and set everything we need.
- */
- riscv_cpu_disable_priv_spec_isa_exts(cpu);
-}
-
#ifndef CONFIG_USER_ONLY
static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
{
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 16a2dfa8c7..409d198635 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -445,7 +445,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
-void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
@@ -711,6 +710,13 @@ enum riscv_pmu_event_idx {
#include "hw/core/tcg-cpu-ops.h"
extern const struct TCGCPUOps riscv_tcg_ops;
+/* used by tcg/tcg-cpu.c*/
+void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
+bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
+bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
+int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
+
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 85a31dc420..4b4ab56c40 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -21,6 +21,7 @@
#include "qemu/log.h"
#include "qemu/timer.h"
#include "cpu.h"
+#include "tcg/tcg-cpu.h"
#include "pmu.h"
#include "time_helper.h"
#include "exec/exec-all.h"
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f47dc2064f..d86172f725 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -19,14 +19,43 @@
#include "qemu/osdep.h"
#include "exec/exec-all.h"
+#include "tcg-cpu.h"
#include "cpu.h"
#include "pmu.h"
#include "time_helper.h"
#include "qapi/error.h"
#include "qemu/accel.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
#include "hw/core/accel-cpu.h"
+static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
+ bool value)
+{
+ CPURISCVState *env = &cpu->env;
+ bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
+ int min_version;
+
+ if (prev_val == value) {
+ return;
+ }
+
+ if (cpu_cfg_ext_is_user_set(ext_offset)) {
+ return;
+ }
+
+ if (value && env->priv_ver != PRIV_VERSION_LATEST) {
+ /* Do not enable it if priv_ver is older than min_version */
+ min_version = cpu_cfg_ext_get_min_version(ext_offset);
+ if (env->priv_ver < min_version) {
+ return;
+ }
+ }
+
+ isa_ext_update_enabled(cpu, ext_offset, value);
+}
+
static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
{
if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
@@ -85,6 +114,334 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
}
}
+static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+ Error **errp)
+{
+ if (!is_power_of_2(cfg->vlen)) {
+ error_setg(errp, "Vector extension VLEN must be power of 2");
+ return;
+ }
+
+ if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
+ error_setg(errp,
+ "Vector extension implementation only supports VLEN "
+ "in the range [128, %d]", RV_VLEN_MAX);
+ return;
+ }
+
+ if (!is_power_of_2(cfg->elen)) {
+ error_setg(errp, "Vector extension ELEN must be power of 2");
+ return;
+ }
+
+ if (cfg->elen > 64 || cfg->elen < 8) {
+ error_setg(errp,
+ "Vector extension implementation only supports ELEN "
+ "in the range [8, 64]");
+ return;
+ }
+
+ if (cfg->vext_spec) {
+ if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
+ env->vext_ver = VEXT_VERSION_1_00_0;
+ } else {
+ error_setg(errp, "Unsupported vector spec version '%s'",
+ cfg->vext_spec);
+ return;
+ }
+ } else if (env->vext_ver == 0) {
+ qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
+
+ env->vext_ver = VEXT_VERSION_1_00_0;
+ }
+}
+
+/*
+ * Check consistency between chosen extensions while setting
+ * cpu->cfg accordingly.
+ */
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+{
+ CPURISCVState *env = &cpu->env;
+ Error *local_err = NULL;
+
+ /* Do some ISA extension error checking */
+ if (riscv_has_ext(env, RVG) &&
+ !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
+ riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
+ riscv_has_ext(env, RVD) &&
+ cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+ !cpu->cfg.ext_icsr) {
+ error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+ return;
+ }
+
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+ !cpu->cfg.ext_ifencei) {
+ error_setg(errp, "RVG requires Zifencei but user set "
+ "Zifencei to false");
+ return;
+ }
+
+ warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
+
+ env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
+ env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
+ }
+
+ if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
+ error_setg(errp,
+ "I and E extensions are incompatible");
+ return;
+ }
+
+ if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
+ error_setg(errp,
+ "Either I or E extension must be set");
+ return;
+ }
+
+ if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
+ error_setg(errp,
+ "Setting S extension without U extension is illegal");
+ return;
+ }
+
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
+ error_setg(errp,
+ "H depends on an I base integer ISA with 32 x registers");
+ return;
+ }
+
+ if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
+ error_setg(errp, "H extension implicitly requires S-mode");
+ return;
+ }
+
+ if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
+ error_setg(errp, "F extension requires Zicsr");
+ return;
+ }
+
+ if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
+ error_setg(errp, "Zawrs extension requires A extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zfa extension requires F extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zfh) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
+ }
+
+ if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zfh/Zfhmin extensions require F extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zfbfmin extension depends on F extension");
+ return;
+ }
+
+ if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "D extension requires F extension");
+ return;
+ }
+
+ if (riscv_has_ext(env, RVV)) {
+ riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ /* The V vector extension depends on the Zve64d extension */
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
+ }
+
+ /* The Zve64d extension depends on the Zve64f extension */
+ if (cpu->cfg.ext_zve64d) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
+ }
+
+ /* The Zve64f extension depends on the Zve32f extension */
+ if (cpu->cfg.ext_zve64f) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
+ }
+
+ if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
+ error_setg(errp, "Zve64d/V extensions require D extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
+ error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfh) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
+ }
+
+ if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+ error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+ error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
+ error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
+ error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
+ error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
+ return;
+ }
+
+ /* Set the ISA extensions, checks should have happened above */
+ if (cpu->cfg.ext_zhinx) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ }
+
+ if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
+ error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
+ return;
+ }
+
+ if (cpu->cfg.ext_zfinx) {
+ if (!cpu->cfg.ext_icsr) {
+ error_setg(errp, "Zfinx extension requires Zicsr");
+ return;
+ }
+ if (riscv_has_ext(env, RVF)) {
+ error_setg(errp,
+ "Zfinx cannot be supported together with F extension");
+ return;
+ }
+ }
+
+ if (cpu->cfg.ext_zce) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+ if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+ }
+
+ /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
+ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+ if (riscv_has_ext(env, RVD)) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+ }
+ }
+
+ if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+ error_setg(errp, "Zcf extension is only relevant to RV32");
+ return;
+ }
+
+ if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
+ error_setg(errp, "Zcf extension requires F extension");
+ return;
+ }
+
+ if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
+ error_setg(errp, "Zcd extension requires D extension");
+ return;
+ }
+
+ if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
+ cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
+ error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
+ "extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
+ error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
+ "Zcd extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+ error_setg(errp, "Zcmt extension requires Zicsr extension");
+ return;
+ }
+
+ /*
+ * In principle Zve*x would also suffice here, were they supported
+ * in qemu
+ */
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
+ cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
+ !cpu->cfg.ext_zve32f) {
+ error_setg(errp,
+ "Vector crypto extensions require V or Zve* extensions");
+ return;
+ }
+
+ if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
+ error_setg(
+ errp,
+ "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
+ return;
+ }
+
+ if (cpu->cfg.ext_zk) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
+ }
+
+ /*
+ * Disable isa extensions based on priv spec after we
+ * validated and set everything we need.
+ */
+ riscv_cpu_disable_priv_spec_isa_exts(cpu);
+}
+
/*
* We'll get here via the following path:
*
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
new file mode 100644
index 0000000000..630184759d
--- /dev/null
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -0,0 +1,27 @@
+/*
+ * riscv TCG cpu class initialization
+ *
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_TCG_CPU_H
+#define RISCV_TCG_CPU_H
+
+#include "cpu.h"
+
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+
+#endif
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (2 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:34 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
` (15 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 58 ------------------------------------
target/riscv/cpu.h | 4 ---
target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
3 files changed, 59 insertions(+), 63 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7215a29324..9426b3b9d6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
return env->pc;
}
-static void riscv_cpu_synchronize_from_tb(CPUState *cs,
- const TranslationBlock *tb)
-{
- if (!(tb_cflags(tb) & CF_PCREL)) {
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
-
- if (xl == MXL_RV32) {
- env->pc = (int32_t) tb->pc;
- } else {
- env->pc = tb->pc;
- }
- }
-}
-
static bool riscv_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
@@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs)
#endif
}
-static void riscv_restore_state_to_opc(CPUState *cs,
- const TranslationBlock *tb,
- const uint64_t *data)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
- target_ulong pc;
-
- if (tb_cflags(tb) & CF_PCREL) {
- pc = (env->pc & TARGET_PAGE_MASK) | data[0];
- } else {
- pc = data[0];
- }
-
- if (xl == MXL_RV32) {
- env->pc = (int32_t)pc;
- } else {
- env->pc = pc;
- }
- env->bins = data[1];
-}
-
static void riscv_cpu_reset_hold(Object *obj)
{
#ifndef CONFIG_USER_ONLY
@@ -1809,23 +1768,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-const struct TCGCPUOps riscv_tcg_ops = {
- .initialize = riscv_translate_init,
- .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- .restore_state_to_opc = riscv_restore_state_to_opc,
-
-#ifndef CONFIG_USER_ONLY
- .tlb_fill = riscv_cpu_tlb_fill,
- .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
- .do_interrupt = riscv_cpu_do_interrupt,
- .do_transaction_failed = riscv_cpu_do_transaction_failed,
- .do_unaligned_access = riscv_cpu_do_unaligned_access,
- .debug_excp_handler = riscv_cpu_debug_excp_handler,
- .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
- .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-
static bool riscv_cpu_is_dynamic(Object *cpu_obj)
{
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 409d198635..b2e558f730 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -706,10 +706,6 @@ enum riscv_pmu_event_idx {
RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
};
-/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
-#include "hw/core/tcg-cpu-ops.h"
-extern const struct TCGCPUOps riscv_tcg_ops;
-
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index d86172f725..e480b9f726 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -28,7 +28,66 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "hw/core/accel-cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg.h"
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ if (!(tb_cflags(tb) & CF_PCREL)) {
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+ tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t) tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
+ }
+}
+
+static void riscv_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ target_ulong pc;
+
+ if (tb_cflags(tb) & CF_PCREL) {
+ pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+ } else {
+ pc = data[0];
+ }
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)pc;
+ } else {
+ env->pc = pc;
+ }
+ env->bins = data[1];
+}
+
+static const struct TCGCPUOps riscv_tcg_ops = {
+ .initialize = riscv_translate_init,
+ .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+ .restore_state_to_opc = riscv_restore_state_to_opc,
+
+#ifndef CONFIG_USER_ONLY
+ .tlb_fill = riscv_cpu_tlb_fill,
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+ .do_interrupt = riscv_cpu_do_interrupt,
+ .do_transaction_failed = riscv_cpu_do_transaction_failed,
+ .do_unaligned_access = riscv_cpu_do_unaligned_access,
+ .debug_excp_handler = riscv_cpu_debug_excp_handler,
+ .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+ .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
bool value)
@@ -515,7 +574,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/*
* All cpus use the same set of operations.
- * riscv_tcg_ops is being imported from cpu.c for now.
*/
cc->tcg_ops = &riscv_tcg_ops;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init()
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (3 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:51 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
` (14 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:
riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
In the near future riscv_cpu_post_init() will call the init() function
of the current accelerator, providing a hook for KVM and TCG accel
classes to change the init() process of the CPU.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9426b3b9d6..848b58e7c4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj)
mlx = MXL_RV32;
#endif
set_misa(env, mlx, 0);
- riscv_cpu_add_user_properties(obj);
- riscv_init_max_cpu_extensions(obj);
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
- riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
- riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
- riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -666,7 +661,6 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
- riscv_cpu_add_user_properties(obj);
}
#endif /* CONFIG_KVM */
@@ -1215,6 +1209,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
}
#endif /* CONFIG_USER_ONLY */
+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+ if (kvm_enabled() &&
+ object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
+ return true;
+ }
+
+ return riscv_cpu_is_dynamic(cpu_obj);
+}
+
+static void riscv_cpu_post_init(Object *obj)
+{
+ if (riscv_cpu_has_user_properties(obj)) {
+ riscv_cpu_add_user_properties(obj);
+ }
+
+ if (riscv_cpu_has_max_extensions(obj)) {
+ riscv_init_max_cpu_extensions(obj);
+ }
+}
+
static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -1768,11 +1793,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-{
- return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2009,6 +2029,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_size = sizeof(RISCVCPU),
.instance_align = __alignof__(RISCVCPU),
.instance_init = riscv_cpu_init,
+ .instance_post_init = riscv_cpu_post_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (4 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:53 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
` (13 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
This CPU only exists if we're compiling with KVM so move it to the kvm
specific file.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 15 ---------------
target/riscv/kvm.c | 21 +++++++++++++++++++++
2 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 848b58e7c4..f8368ce274 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -652,18 +652,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
}
#endif
-#if defined(CONFIG_KVM)
-static void riscv_host_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
-#if defined(TARGET_RISCV32)
- set_misa(env, MXL_RV32, 0);
-#elif defined(TARGET_RISCV64)
- set_misa(env, MXL_RV64, 0);
-#endif
-}
-#endif /* CONFIG_KVM */
-
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -2041,9 +2029,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
},
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
-#if defined(CONFIG_KVM)
- DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
-#endif
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 1e4e4456b3..31d2ede4b6 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -1271,3 +1271,24 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
}
+
+static void riscv_host_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+
+#if defined(TARGET_RISCV32)
+ env->misa_mxl_max = env->misa_mxl = MXL_RV32;
+#elif defined(TARGET_RISCV64)
+ env->misa_mxl_max = env->misa_mxl = MXL_RV64;
+#endif
+}
+
+static const TypeInfo riscv_kvm_cpu_type_infos[] = {
+ {
+ .name = TYPE_RISCV_CPU_HOST,
+ .parent = TYPE_RISCV_CPU,
+ .instance_init = riscv_host_cpu_init,
+ }
+};
+
+DEFINE_TYPES(riscv_kvm_cpu_type_infos)
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const'
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (5 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:54 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
` (12 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.
Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8368ce274..048a2dbc77 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig {
{.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.enabled = _defval}
-static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
};
/* These are experimental so mark with 'x-' */
-static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
/* ePMP 0.9.3 */
MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
}
static void cpu_add_multi_ext_prop(Object *cpu_obj,
- RISCVCPUMultiExtConfig *multi_cfg)
+ const RISCVCPUMultiExtConfig *multi_cfg)
{
object_property_add(cpu_obj, multi_cfg->name, "bool",
cpu_get_multi_ext_cfg,
@@ -1575,11 +1575,13 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
}
static void riscv_cpu_add_multiext_prop_array(Object *obj,
- RISCVCPUMultiExtConfig *array)
+ const RISCVCPUMultiExtConfig *array)
{
+ const RISCVCPUMultiExtConfig *prop;
+
g_assert(array);
- for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+ for (prop = array; prop && prop->name; prop++) {
cpu_add_multi_ext_prop(obj, prop);
}
}
@@ -1620,11 +1622,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
}
static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
- RISCVCPUMultiExtConfig *array)
+ const RISCVCPUMultiExtConfig *array)
{
+ const RISCVCPUMultiExtConfig *prop;
+
g_assert(array);
- for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+ for (prop = array; prop && prop->name; prop++) {
riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
}
}
@@ -1687,7 +1691,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- RISCVCPUMultiExtConfig *prop;
+ const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (6 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 5:55 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
` (11 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
We'll introduce the KVM accelerator class with a 'cpu_instance_init'
implementation that is going to be invoked during the common
riscv_cpu_post_init() (via accel_cpu_instance_init()). This
instance_init will execute KVM exclusive code that TCG doesn't care
about, such as adding KVM specific properties, initing registers using a
KVM scratch CPU and so on.
The core of the forementioned cpu_instance_init impl is the current
riscv_cpu_add_kvm_properties() that is being used by the common code via
riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
will all the relevant artifacts, exporting and renaming it to
kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.
To make this work we'll need to export riscv_cpu_extensions,
riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
well. The TCG accelerator will also need to access those in the near
future so this export will benefit us in the long run.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 85 +++-------------------------------------
target/riscv/cpu.h | 14 +++++++
target/riscv/kvm.c | 68 +++++++++++++++++++++++++++++++-
target/riscv/kvm_riscv.h | 3 --
4 files changed, 86 insertions(+), 84 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 048a2dbc77..0dc9b3201d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1370,7 +1370,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
* change MISA bits during realize() (RVG enables MISA
* bits but the user is warned about it).
*/
-static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
int i;
@@ -1397,17 +1397,11 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
}
}
-typedef struct RISCVCPUMultiExtConfig {
- const char *name;
- uint32_t offset;
- bool enabled;
-} RISCVCPUMultiExtConfig;
-
#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
{.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.enabled = _defval}
-static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -1469,7 +1463,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
};
/* These are experimental so mark with 'x-' */
-static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
/* ePMP 0.9.3 */
MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -1513,7 +1507,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static Property riscv_cpu_options[] = {
+Property riscv_cpu_options[] = {
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
@@ -1586,75 +1580,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
}
}
-#ifdef CONFIG_KVM
-static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
- const char *name,
- void *opaque, Error **errp)
-{
- const char *propname = opaque;
- bool value;
-
- if (!visit_type_bool(v, name, &value, errp)) {
- return;
- }
-
- if (value) {
- error_setg(errp, "extension %s is not available with KVM",
- propname);
- }
-}
-
-static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
-{
- /* Check if KVM created the property already */
- if (object_property_find(obj, prop_name)) {
- return;
- }
-
- /*
- * Set the default to disabled for every extension
- * unknown to KVM and error out if the user attempts
- * to enable any of them.
- */
- object_property_add(obj, prop_name, "bool",
- NULL, cpu_set_cfg_unavailable,
- NULL, (void *)prop_name);
-}
-
-static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
- const RISCVCPUMultiExtConfig *array)
-{
- const RISCVCPUMultiExtConfig *prop;
-
- g_assert(array);
-
- for (prop = array; prop && prop->name; prop++) {
- riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
- }
-}
-
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
-{
- Property *prop;
- DeviceState *dev = DEVICE(obj);
-
- kvm_riscv_init_user_properties(obj);
- riscv_cpu_add_misa_properties(obj);
-
- riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
- riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
- riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
-
- for (prop = riscv_cpu_options; prop && prop->name; prop++) {
- /* Check if KVM created the property already */
- if (object_property_find(obj, prop->name)) {
- continue;
- }
- qdev_property_add_static(dev, prop);
- }
-}
-#endif
-
/*
* Add CPU properties with user-facing flags.
*
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b2e558f730..9dc4113812 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -22,6 +22,7 @@
#include "hw/core/cpu.h"
#include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#include "qom/object.h"
@@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
+typedef struct RISCVCPUMultiExtConfig {
+ const char *name;
+ uint32_t offset;
+ bool enabled;
+} RISCVCPUMultiExtConfig;
+
+extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern Property riscv_cpu_options[];
+
+void riscv_cpu_add_misa_properties(Object *cpu_obj);
+
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 31d2ede4b6..e682a70311 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -345,6 +345,52 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
}
}
+static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+ const char *propname = opaque;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+
+ if (value) {
+ error_setg(errp, "extension %s is not available with KVM",
+ propname);
+ }
+}
+
+static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
+{
+ /* Check if KVM created the property already */
+ if (object_property_find(obj, prop_name)) {
+ return;
+ }
+
+ /*
+ * Set the default to disabled for every extension
+ * unknown to KVM and error out if the user attempts
+ * to enable any of them.
+ */
+ object_property_add(obj, prop_name, "bool",
+ NULL, cpu_set_cfg_unavailable,
+ NULL, (void *)prop_name);
+}
+
+static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
+ const RISCVCPUMultiExtConfig *array)
+{
+ const RISCVCPUMultiExtConfig *prop;
+
+ g_assert(array);
+
+ for (prop = array; prop && prop->name; prop++) {
+ riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
+ }
+}
+
static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
{
int i;
@@ -754,7 +800,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
}
}
-void kvm_riscv_init_user_properties(Object *cpu_obj)
+static void riscv_init_user_properties(Object *cpu_obj)
{
RISCVCPU *cpu = RISCV_CPU(cpu_obj);
KVMScratchCPU kvmcpu;
@@ -1272,6 +1318,26 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
}
+void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+{
+ DeviceState *dev = DEVICE(obj);
+
+ riscv_init_user_properties(obj);
+ riscv_cpu_add_misa_properties(obj);
+
+ riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
+ riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
+ riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+
+ for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+ /* Check if KVM created the property already */
+ if (object_property_find(obj, prop->name)) {
+ continue;
+ }
+ qdev_property_add_static(dev, prop);
+ }
+}
+
static void riscv_host_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index 44b850a046..da9630c4af 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -19,10 +19,7 @@
#ifndef QEMU_KVM_RISCV_H
#define QEMU_KVM_RISCV_H
-/* Temporarily implemented in cpu.c */
void kvm_riscv_cpu_add_kvm_properties(Object *obj);
-
-void kvm_riscv_init_user_properties(Object *cpu_obj);
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (7 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 6:03 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
` (10 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 5 ++---
target/riscv/cpu.h | 1 +
target/riscv/kvm.c | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dc9b3201d..50be127f36 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
satp_map->init |= 1 << satp;
}
-static void riscv_add_satp_mode_properties(Object *obj)
+void riscv_add_satp_mode_properties(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
static void riscv_cpu_add_user_properties(Object *obj)
{
#ifndef CONFIG_USER_ONLY
- riscv_add_satp_mode_properties(obj);
-
if (kvm_enabled()) {
kvm_riscv_cpu_add_kvm_properties(obj);
return;
}
+ riscv_add_satp_mode_properties(obj);
#endif
riscv_cpu_add_misa_properties(obj);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9dc4113812..cb13464ba6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
extern Property riscv_cpu_options[];
void riscv_cpu_add_misa_properties(Object *cpu_obj);
+void riscv_add_satp_mode_properties(Object *obj);
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index e682a70311..e5e957121f 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -1323,6 +1323,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
DeviceState *dev = DEVICE(obj);
riscv_init_user_properties(obj);
+ riscv_add_satp_mode_properties(obj);
riscv_cpu_add_misa_properties(obj);
riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 10/19] target/riscv: remove kvm-stub.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (8 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 6:06 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
` (9 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
in non-KVM builds.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/kvm-stub.c | 30 ------------------------------
target/riscv/meson.build | 2 +-
2 files changed, 1 insertion(+), 31 deletions(-)
delete mode 100644 target/riscv/kvm-stub.c
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
deleted file mode 100644
index 4e8fc31a21..0000000000
--- a/target/riscv/kvm-stub.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * QEMU KVM RISC-V specific function stubs
- *
- * Copyright (c) 2020 Huawei Technologies Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "kvm_riscv.h"
-
-void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
-{
- abort();
-}
-
-void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
-{
- abort();
-}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index f0486183fa..3323b78b84 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -24,7 +24,7 @@ riscv_ss.add(files(
'zce_helper.c',
'vcrypto_helper.c'
))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
riscv_system_ss = ss.source_set()
riscv_system_ss.add(files(
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (9 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 6:08 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
` (8 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
Add a KVM accelerator class like we did with TCG. The difference is
that, at least for now, we won't be using a realize() implementation for
this accelerator.
We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
through the 'cpu_instance_init' impl of the current acceleration (if
available) and execute it. The end result is that the KVM initial setup,
i.e. starting registers and adding its specific properties, will be done
via this hook.
Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
calling riscv_cpu_add_user_properties() when running KVM. We'll remove
this condition when the TCG accel class get its own 'cpu_instance_init'
implementation.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 8 +++-----
target/riscv/kvm.c | 26 ++++++++++++++++++++++++--
target/riscv/kvm_riscv.h | 1 -
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 50be127f36..c8a19be1af 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1219,7 +1219,9 @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
static void riscv_cpu_post_init(Object *obj)
{
- if (riscv_cpu_has_user_properties(obj)) {
+ accel_cpu_instance_init(CPU(obj));
+
+ if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
riscv_cpu_add_user_properties(obj);
}
@@ -1589,10 +1591,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
static void riscv_cpu_add_user_properties(Object *obj)
{
#ifndef CONFIG_USER_ONLY
- if (kvm_enabled()) {
- kvm_riscv_cpu_add_kvm_properties(obj);
- return;
- }
riscv_add_satp_mode_properties(obj);
#endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index e5e957121f..606fdab223 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -31,6 +31,7 @@
#include "sysemu/kvm_int.h"
#include "cpu.h"
#include "trace.h"
+#include "hw/core/accel-cpu.h"
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "exec/address-spaces.h"
@@ -1318,8 +1319,9 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
}
-void kvm_riscv_cpu_add_kvm_properties(Object *obj)
+static void kvm_cpu_instance_init(CPUState *cs)
{
+ Object *obj = OBJECT(RISCV_CPU(cs));
DeviceState *dev = DEVICE(obj);
riscv_init_user_properties(obj);
@@ -1331,7 +1333,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
- /* Check if KVM created the property already */
+ /* Check if we have a specific KVM handler for the option */
if (object_property_find(obj, prop->name)) {
continue;
}
@@ -1339,6 +1341,26 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
}
}
+static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+ acc->cpu_instance_init = kvm_cpu_instance_init;
+}
+
+static const TypeInfo kvm_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = kvm_cpu_accel_class_init,
+ .abstract = true,
+};
+static void kvm_cpu_accel_register_types(void)
+{
+ type_register_static(&kvm_cpu_accel_type_info);
+}
+type_init(kvm_cpu_accel_register_types);
+
static void riscv_host_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index da9630c4af..8329cfab82 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -19,7 +19,6 @@
#ifndef QEMU_KVM_RISCV_H
#define QEMU_KVM_RISCV_H
-void kvm_riscv_cpu_add_kvm_properties(Object *obj);
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (10 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 1:26 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
` (7 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
hw/intc/riscv_aplic.c | 2 +-
hw/riscv/virt.c | 2 +-
target/riscv/cpu.c | 2 +-
target/riscv/{kvm.c => kvm/kvm-cpu.c} | 0
target/riscv/{ => kvm}/kvm_riscv.h | 0
target/riscv/kvm/meson.build | 1 +
target/riscv/meson.build | 2 +-
7 files changed, 5 insertions(+), 4 deletions(-)
rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (100%)
rename target/riscv/{ => kvm}/kvm_riscv.h (100%)
create mode 100644 target/riscv/kvm/meson.build
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 99aae8ccbe..c677b5cfbb 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -32,7 +32,7 @@
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
#include "migration/vmstate.h"
#define APLIC_MAX_IDC (1UL << 14)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5edc1d98d2..9de578c756 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -35,7 +35,7 @@
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
#include "hw/intc/riscv_imsic.h"
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c8a19be1af..51567c2f12 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -33,7 +33,7 @@
#include "fpu/softfloat-helpers.h"
#include "sysemu/kvm.h"
#include "sysemu/tcg.h"
-#include "kvm_riscv.h"
+#include "kvm/kvm_riscv.h"
#include "tcg/tcg.h"
/* RISC-V CPU definitions */
diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c
similarity index 100%
rename from target/riscv/kvm.c
rename to target/riscv/kvm/kvm-cpu.c
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
similarity index 100%
rename from target/riscv/kvm_riscv.h
rename to target/riscv/kvm/kvm_riscv.h
diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
new file mode 100644
index 0000000000..7e92415091
--- /dev/null
+++ b/target/riscv/kvm/meson.build
@@ -0,0 +1 @@
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 3323b78b84..c53962215f 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -24,7 +24,6 @@ riscv_ss.add(files(
'zce_helper.c',
'vcrypto_helper.c'
))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
riscv_system_ss = ss.source_set()
riscv_system_ss.add(files(
@@ -39,6 +38,7 @@ riscv_system_ss.add(files(
))
subdir('tcg')
+subdir('kvm')
target_arch += {'riscv': riscv_ss}
target_softmmu_arch += {'riscv': riscv_system_ss}
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (11 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 1:32 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
` (6 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
riscv_cpu_add_misa_properties() is being used to fill the missing KVM
MISA properties but it is a TCG helper that was adapted to do so. We'll
move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
the remaining MISA properties on its own.
Do not use riscv_cpu_add_misa_properties(). Let's create a new array
with all available MISA bits we support that can be read by KVM. The
array is zero terminate to allow us to iterate through it without
knowing its size.
Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
MISA properties as usual and then use this array to add any missing MISA
properties with the riscv_cpu_add_kvm_unavail_prop() helper.
Note that we're creating misa_bits[], and not using the existing
'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
related functions and it doesn't have all MISA bits we support. Commit
0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
full context.
While we're at it, move both satp and the multi-letter extension
properties to kvm_riscv_add_cpu_user_properties() as well.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 3 ++-
target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++--------
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 51567c2f12..665c21af6a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -38,6 +38,8 @@
/* RISC-V CPU definitions */
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
+const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
+ RVC, RVS, RVU, RVH, RVJ, RVG, 0};
struct isa_ext_data {
const char *name;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cb13464ba6..7235eafc1a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -43,7 +43,7 @@
#define RV(x) ((target_ulong)1 << (x - 'A'))
/*
- * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[]
+ * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
* when adding new MISA bits here.
*/
#define RVI RV('I')
@@ -60,6 +60,7 @@
#define RVJ RV('J')
#define RVG RV('G')
+extern const uint32_t misa_bits[];
const char *riscv_get_misa_ext_name(uint32_t bit);
const char *riscv_get_misa_ext_description(uint32_t bit);
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 606fdab223..c6615cb807 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -396,6 +396,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
{
int i;
+ riscv_add_satp_mode_properties(cpu_obj);
+
for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i];
int bit = misa_cfg->offset;
@@ -411,6 +413,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
misa_cfg->description);
}
+ for (i = 0; misa_bits[i] != 0; i++) {
+ const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]);
+ riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name);
+ }
+
for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
@@ -427,6 +434,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
object_property_add(cpu_obj, "cboz_blocksize", "uint16",
NULL, kvm_cpu_set_cbomz_blksize,
NULL, &kvm_cboz_blocksize);
+
+ riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions);
+ riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts);
+ riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts);
}
static int kvm_riscv_get_regs_core(CPUState *cs)
@@ -801,7 +812,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
}
}
-static void riscv_init_user_properties(Object *cpu_obj)
+static void riscv_init_kvm_registers(Object *cpu_obj)
{
RISCVCPU *cpu = RISCV_CPU(cpu_obj);
KVMScratchCPU kvmcpu;
@@ -810,7 +821,6 @@ static void riscv_init_user_properties(Object *cpu_obj)
return;
}
- kvm_riscv_add_cpu_user_properties(cpu_obj);
kvm_riscv_init_machine_ids(cpu, &kvmcpu);
kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
@@ -1324,13 +1334,9 @@ static void kvm_cpu_instance_init(CPUState *cs)
Object *obj = OBJECT(RISCV_CPU(cs));
DeviceState *dev = DEVICE(obj);
- riscv_init_user_properties(obj);
- riscv_add_satp_mode_properties(obj);
- riscv_cpu_add_misa_properties(obj);
+ riscv_init_kvm_registers(obj);
- riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
- riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
- riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
+ kvm_riscv_add_cpu_user_properties(obj);
for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
/* Check if we have a specific KVM handler for the option */
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 14/19] target/riscv/cpu.c: export set_misa()
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (12 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 1:36 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
` (5 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.
Rename it to riscv_cpu_set_misa() and make it public.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 34 ++++++++++++++++++----------------
target/riscv/cpu.h | 1 +
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 665c21af6a..cf191d576e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
}
}
-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{
env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext;
@@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32)
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64)
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
#ifndef CONFIG_USER_ONLY
@@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj)
#ifdef TARGET_RISCV32
mlx = MXL_RV32;
#endif
- set_misa(env, mlx, 0);
+ riscv_cpu_set_misa(env, mlx, 0);
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, MXL_RV64, 0);
+ riscv_cpu_set_misa(env, MXL_RV64, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64,
+ RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfa = true;
@@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+ riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
env->priv_ver = PRIV_VERSION_1_12_0;
/* Enable ISA extensions */
@@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj)
}
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, MXL_RV128, 0);
+ riscv_cpu_set_misa(env, MXL_RV128, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, MXL_RV32, 0);
+ riscv_cpu_set_misa(env, MXL_RV32, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32,
+ RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
- set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+ riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7235eafc1a..9ec0805596 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
typedef struct RISCVCPUMultiExtConfig {
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init()
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (13 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 1:56 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
` (4 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
accelerator. It'll be called from within riscv_cpu_post_init(), via
accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
preserve behavior, the implementation will be similar to what
riscv_cpu_post_init() already does.
In this patch we'll move riscv_cpu_add_user_properties() and
riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
All multi-extension properties code was moved. The 'multi_ext_user_opts'
hash table was also moved to tcg-cpu.c since it's a TCG only structure,
meaning that we won't have to worry about initializing a TCG hash table
when running a KVM CPU anymore.
riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
much code it requires to be moved at the same time. We'll do that in the
next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 150 -------------------------------------
target/riscv/cpu.h | 1 -
target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++
3 files changed, 149 insertions(+), 151 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cf191d576e..8616c9e2f5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
-/* Hash that stores user set extensions */
-static GHashTable *multi_ext_user_opts;
-
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
{
bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
@@ -194,12 +191,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
g_assert_not_reached();
}
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
-{
- return g_hash_table_contains(multi_ext_user_opts,
- GUINT_TO_POINTER(ext_offset));
-}
-
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -280,9 +271,6 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
-static void riscv_cpu_add_user_properties(Object *obj);
-static void riscv_init_max_cpu_extensions(Object *obj);
-
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
if (async) {
@@ -1206,32 +1194,9 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
}
-static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
-{
- return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
-}
-
-static bool riscv_cpu_has_user_properties(Object *cpu_obj)
-{
- if (kvm_enabled() &&
- object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
- return true;
- }
-
- return riscv_cpu_is_dynamic(cpu_obj);
-}
-
static void riscv_cpu_post_init(Object *obj)
{
accel_cpu_instance_init(CPU(obj));
-
- if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
- riscv_cpu_add_user_properties(obj);
- }
-
- if (riscv_cpu_has_max_extensions(obj)) {
- riscv_init_max_cpu_extensions(obj);
- }
}
static void riscv_cpu_init(Object *obj)
@@ -1244,8 +1209,6 @@ static void riscv_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
#endif /* CONFIG_USER_ONLY */
-
- multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
}
typedef struct RISCVCPUMisaExtConfig {
@@ -1531,119 +1494,6 @@ Property riscv_cpu_options[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
- bool value;
-
- if (!visit_type_bool(v, name, &value, errp)) {
- return;
- }
-
- isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
-
- g_hash_table_insert(multi_ext_user_opts,
- GUINT_TO_POINTER(multi_ext_cfg->offset),
- (gpointer)value);
-}
-
-static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
- bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
-
- visit_type_bool(v, name, &value, errp);
-}
-
-static void cpu_add_multi_ext_prop(Object *cpu_obj,
- const RISCVCPUMultiExtConfig *multi_cfg)
-{
- object_property_add(cpu_obj, multi_cfg->name, "bool",
- cpu_get_multi_ext_cfg,
- cpu_set_multi_ext_cfg,
- NULL, (void *)multi_cfg);
-
- /*
- * Set def val directly instead of using
- * object_property_set_bool() to save the set()
- * callback hash for user inputs.
- */
- isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
- multi_cfg->enabled);
-}
-
-static void riscv_cpu_add_multiext_prop_array(Object *obj,
- const RISCVCPUMultiExtConfig *array)
-{
- const RISCVCPUMultiExtConfig *prop;
-
- g_assert(array);
-
- for (prop = array; prop && prop->name; prop++) {
- cpu_add_multi_ext_prop(obj, prop);
- }
-}
-
-/*
- * Add CPU properties with user-facing flags.
- *
- * This will overwrite existing env->misa_ext values with the
- * defaults set via riscv_cpu_add_misa_properties().
- */
-static void riscv_cpu_add_user_properties(Object *obj)
-{
-#ifndef CONFIG_USER_ONLY
- riscv_add_satp_mode_properties(obj);
-#endif
-
- riscv_cpu_add_misa_properties(obj);
-
- riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
- riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
- riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
-
- for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
- qdev_property_add_static(DEVICE(obj), prop);
- }
-}
-
-/*
- * The 'max' type CPU will have all possible ratified
- * non-vendor extensions enabled.
- */
-static void riscv_init_max_cpu_extensions(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- const RISCVCPUMultiExtConfig *prop;
-
- /* Enable RVG, RVJ and RVV that are disabled by default */
- riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-
- for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
- isa_ext_update_enabled(cpu, prop->offset, true);
- }
-
- /* set vector version */
- env->vext_ver = VEXT_VERSION_1_00_0;
-
- /* Zfinx is not compatible with F. Disable it */
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
-
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
-
- if (env->misa_mxl != MXL_RV32) {
- isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
- }
-}
-
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9ec0805596..01cbcbe119 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -710,7 +710,6 @@ enum riscv_pmu_event_idx {
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
-bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index e480b9f726..5d71ff2cce 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -24,6 +24,7 @@
#include "pmu.h"
#include "time_helper.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "qemu/accel.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
@@ -31,6 +32,15 @@
#include "hw/core/tcg-cpu-ops.h"
#include "tcg/tcg.h"
+/* Hash that stores user set extensions */
+static GHashTable *multi_ext_user_opts;
+
+static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
+{
+ return g_hash_table_contains(multi_ext_user_opts,
+ GUINT_TO_POINTER(ext_offset));
+}
+
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -570,6 +580,144 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
return true;
}
+static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+
+ isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
+
+ g_hash_table_insert(multi_ext_user_opts,
+ GUINT_TO_POINTER(multi_ext_cfg->offset),
+ (gpointer)value);
+}
+
+static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
+ bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_add_multi_ext_prop(Object *cpu_obj,
+ const RISCVCPUMultiExtConfig *multi_cfg)
+{
+ object_property_add(cpu_obj, multi_cfg->name, "bool",
+ cpu_get_multi_ext_cfg,
+ cpu_set_multi_ext_cfg,
+ NULL, (void *)multi_cfg);
+
+ /*
+ * Set def val directly instead of using
+ * object_property_set_bool() to save the set()
+ * callback hash for user inputs.
+ */
+ isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
+ multi_cfg->enabled);
+}
+
+static void riscv_cpu_add_multiext_prop_array(Object *obj,
+ const RISCVCPUMultiExtConfig *array)
+{
+ const RISCVCPUMultiExtConfig *prop;
+
+ g_assert(array);
+
+ for (prop = array; prop && prop->name; prop++) {
+ cpu_add_multi_ext_prop(obj, prop);
+ }
+}
+
+/*
+ * Add CPU properties with user-facing flags.
+ *
+ * This will overwrite existing env->misa_ext values with the
+ * defaults set via riscv_cpu_add_misa_properties().
+ */
+static void riscv_cpu_add_user_properties(Object *obj)
+{
+#ifndef CONFIG_USER_ONLY
+ riscv_add_satp_mode_properties(obj);
+#endif
+
+ riscv_cpu_add_misa_properties(obj);
+
+ riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
+ riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
+ riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
+
+ for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
+ qdev_property_add_static(DEVICE(obj), prop);
+ }
+}
+
+/*
+ * The 'max' type CPU will have all possible ratified
+ * non-vendor extensions enabled.
+ */
+static void riscv_init_max_cpu_extensions(Object *obj)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ const RISCVCPUMultiExtConfig *prop;
+
+ /* Enable RVG, RVJ and RVV that are disabled by default */
+ riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+
+ for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+ isa_ext_update_enabled(cpu, prop->offset, true);
+ }
+
+ /* set vector version */
+ env->vext_ver = VEXT_VERSION_1_00_0;
+
+ /* Zfinx is not compatible with F. Disable it */
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
+
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
+
+ if (env->misa_mxl != MXL_RV32) {
+ isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
+ }
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static void tcg_cpu_instance_init(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ Object *obj = OBJECT(cpu);
+
+ if (riscv_cpu_has_user_properties(obj)) {
+ multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+ riscv_cpu_add_user_properties(obj);
+ }
+
+ if (riscv_cpu_has_max_extensions(obj)) {
+ riscv_init_max_cpu_extensions(obj);
+ }
+}
+
static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/*
@@ -588,6 +736,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
acc->cpu_class_init = tcg_cpu_class_init;
+ acc->cpu_instance_init = tcg_cpu_instance_init;
acc->cpu_realizefn = tcg_cpu_realizefn;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (14 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 1:37 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
` (3 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
The array isn't marked as 'const' because we're initializing their
elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
fields.
In a closer look we can see that we're not using these 2 fields after
creating the MISA properties. And we can create the properties by using
riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
directly.
Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
and make misa_ext_cfgs[] a const array.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8616c9e2f5..4875feded7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1212,8 +1212,6 @@ static void riscv_cpu_init(Object *obj)
}
typedef struct RISCVCPUMisaExtConfig {
- const char *name;
- const char *description;
target_ulong misa_bit;
bool enabled;
} RISCVCPUMisaExtConfig;
@@ -1317,7 +1315,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
#define MISA_CFG(_bit, _enabled) \
{.misa_bit = _bit, .enabled = _enabled}
-static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
MISA_CFG(RVA, true),
MISA_CFG(RVC, true),
MISA_CFG(RVD, true),
@@ -1344,25 +1342,22 @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
int i;
for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
- RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+ const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
int bit = misa_cfg->misa_bit;
-
- misa_cfg->name = riscv_get_misa_ext_name(bit);
- misa_cfg->description = riscv_get_misa_ext_description(bit);
+ const char *name = riscv_get_misa_ext_name(bit);
+ const char *desc = riscv_get_misa_ext_description(bit);
/* Check if KVM already created the property */
- if (object_property_find(cpu_obj, misa_cfg->name)) {
+ if (object_property_find(cpu_obj, name)) {
continue;
}
- object_property_add(cpu_obj, misa_cfg->name, "bool",
+ object_property_add(cpu_obj, name, "bool",
cpu_get_misa_ext_cfg,
cpu_set_misa_ext_cfg,
NULL, (void *)misa_cfg);
- object_property_set_description(cpu_obj, misa_cfg->name,
- misa_cfg->description);
- object_property_set_bool(cpu_obj, misa_cfg->name,
- misa_cfg->enabled, NULL);
+ object_property_set_description(cpu_obj, name, desc);
+ object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (15 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 1:57 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
` (2 subsequent siblings)
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
All code related to MISA TCG properties is also moved.
At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 90 --------------------------------------
target/riscv/cpu.h | 1 -
target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+), 91 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4875feded7..46263e55d5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj)
#endif /* CONFIG_USER_ONLY */
}
-typedef struct RISCVCPUMisaExtConfig {
- target_ulong misa_bit;
- bool enabled;
-} RISCVCPUMisaExtConfig;
-
-static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
- target_ulong misa_bit = misa_ext_cfg->misa_bit;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- bool value;
-
- if (!visit_type_bool(v, name, &value, errp)) {
- return;
- }
-
- if (value) {
- env->misa_ext |= misa_bit;
- env->misa_ext_mask |= misa_bit;
- } else {
- env->misa_ext &= ~misa_bit;
- env->misa_ext_mask &= ~misa_bit;
- }
-}
-
-static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
- target_ulong misa_bit = misa_ext_cfg->misa_bit;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- bool value;
-
- value = env->misa_ext & misa_bit;
-
- visit_type_bool(v, name, &value, errp);
-}
-
typedef struct misa_ext_info {
const char *name;
const char *description;
@@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
return val;
}
-#define MISA_CFG(_bit, _enabled) \
- {.misa_bit = _bit, .enabled = _enabled}
-
-static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
- MISA_CFG(RVA, true),
- MISA_CFG(RVC, true),
- MISA_CFG(RVD, true),
- MISA_CFG(RVF, true),
- MISA_CFG(RVI, true),
- MISA_CFG(RVE, false),
- MISA_CFG(RVM, true),
- MISA_CFG(RVS, true),
- MISA_CFG(RVU, true),
- MISA_CFG(RVH, true),
- MISA_CFG(RVJ, false),
- MISA_CFG(RVV, false),
- MISA_CFG(RVG, false),
-};
-
-/*
- * We do not support user choice tracking for MISA
- * extensions yet because, so far, we do not silently
- * change MISA bits during realize() (RVG enables MISA
- * bits but the user is warned about it).
- */
-void riscv_cpu_add_misa_properties(Object *cpu_obj)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
- const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
- int bit = misa_cfg->misa_bit;
- const char *name = riscv_get_misa_ext_name(bit);
- const char *desc = riscv_get_misa_ext_description(bit);
-
- /* Check if KVM already created the property */
- if (object_property_find(cpu_obj, name)) {
- continue;
- }
-
- object_property_add(cpu_obj, name, "bool",
- cpu_get_misa_ext_cfg,
- cpu_set_misa_ext_cfg,
- NULL, (void *)misa_cfg);
- object_property_set_description(cpu_obj, name, desc);
- object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
- }
-}
-
#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
{.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.enabled = _defval}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 01cbcbe119..aba8192c74 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
extern Property riscv_cpu_options[];
-void riscv_cpu_add_misa_properties(Object *cpu_obj);
void riscv_add_satp_mode_properties(Object *obj);
/* CSR function table */
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 5d71ff2cce..c326ab37a2 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -580,6 +580,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
return true;
}
+typedef struct RISCVCPUMisaExtConfig {
+ target_ulong misa_bit;
+ bool enabled;
+} RISCVCPUMisaExtConfig;
+
+static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+
+ if (value) {
+ env->misa_ext |= misa_bit;
+ env->misa_ext_mask |= misa_bit;
+ } else {
+ env->misa_ext &= ~misa_bit;
+ env->misa_ext_mask &= ~misa_bit;
+ }
+}
+
+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ bool value;
+
+ value = env->misa_ext & misa_bit;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+#define MISA_CFG(_bit, _enabled) \
+ {.misa_bit = _bit, .enabled = _enabled}
+
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+ MISA_CFG(RVA, true),
+ MISA_CFG(RVC, true),
+ MISA_CFG(RVD, true),
+ MISA_CFG(RVF, true),
+ MISA_CFG(RVI, true),
+ MISA_CFG(RVE, false),
+ MISA_CFG(RVM, true),
+ MISA_CFG(RVS, true),
+ MISA_CFG(RVU, true),
+ MISA_CFG(RVH, true),
+ MISA_CFG(RVJ, false),
+ MISA_CFG(RVV, false),
+ MISA_CFG(RVG, false),
+};
+
+/*
+ * We do not support user choice tracking for MISA
+ * extensions yet because, so far, we do not silently
+ * change MISA bits during realize() (RVG enables MISA
+ * bits but the user is warned about it).
+ */
+static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+ const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+ int bit = misa_cfg->misa_bit;
+ const char *name = riscv_get_misa_ext_name(bit);
+ const char *desc = riscv_get_misa_ext_description(bit);
+
+ /* Check if KVM already created the property */
+ if (object_property_find(cpu_obj, name)) {
+ continue;
+ }
+
+ object_property_add(cpu_obj, name, "bool",
+ cpu_get_misa_ext_cfg,
+ cpu_set_misa_ext_cfg,
+ NULL, (void *)misa_cfg);
+ object_property_set_description(cpu_obj, name, desc);
+ object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+ }
+}
+
static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[]
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (16 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-25 2:00 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
2023-09-25 3:30 ` [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Alistair Francis
19 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
This array will be read by the TCG accel class, allowing it to handle
priv spec verifications on its own. The array will remain here in cpu.c
because it's also used by the riscv,isa string function.
To export it we'll finish it with an empty element since ARRAY_SIZE()
won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
alleviate the changes for the next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
target/riscv/cpu.h | 7 +++++++
2 files changed, 28 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 46263e55d5..e97ba3df93 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
RVC, RVS, RVU, RVH, RVJ, RVG, 0};
-struct isa_ext_data {
- const char *name;
- int min_version;
- int ext_enable_offset;
-};
-
-#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
- {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
-
/*
* From vector_helper.c
* Note that vector data is stored in host-endian 64-bit chunks,
@@ -61,6 +52,9 @@ struct isa_ext_data {
#define BYTE(x) (x)
#endif
+#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
+ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
+
/*
* Here are the ordering rules of extension naming defined by RISC-V
* specification :
@@ -81,7 +75,7 @@ struct isa_ext_data {
* Single letter extensions are checked in riscv_cpu_validate_misa_priv()
* instead.
*/
-static const struct isa_ext_data isa_edata_arr[] = {
+const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
@@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+
+ DEFINE_PROP_END_OF_LIST(),
};
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
@@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
{
- int i;
+ const RISCVIsaExtData *edata;
- for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
+ if (edata->ext_enable_offset != ext_offset) {
continue;
}
- return isa_edata_arr[i].min_version;
+ return edata->min_version;
}
g_assert_not_reached();
@@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
{
CPURISCVState *env = &cpu->env;
- int i;
+ const RISCVIsaExtData *edata;
/* Force disable extensions if priv spec version does not match */
- for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
- (env->priv_ver < isa_edata_arr[i].min_version)) {
- isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
- false);
+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
+ if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
+ (env->priv_ver < edata->min_version)) {
+ isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
#ifndef CONFIG_USER_ONLY
warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
" because privilege spec version does not match",
- isa_edata_arr[i].name, env->mhartid);
+ edata->name, env->mhartid);
#else
warn_report("disabling %s extension because "
"privilege spec version does not match",
- isa_edata_arr[i].name);
+ edata->name);
#endif
}
}
@@ -1619,13 +1614,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int max_str_len)
{
+ const RISCVIsaExtData *edata;
char *old = *isa_str;
char *new = *isa_str;
- int i;
- for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
- new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
+ if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
+ new = g_strconcat(old, "_", edata->name, NULL);
g_free(old);
old = new;
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index aba8192c74..3dfcd0732f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
extern Property riscv_cpu_options[];
+typedef struct isa_ext_data {
+ const char *name;
+ int min_version;
+ int ext_enable_offset;
+} RISCVIsaExtData;
+extern const RISCVIsaExtData isa_edata_arr[];
+
void riscv_add_satp_mode_properties(Object *obj);
/* CSR function table */
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (17 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
@ 2023-09-20 11:20 ` Daniel Henrique Barboza
2023-09-22 10:55 ` Philippe Mathieu-Daudé
2023-09-25 2:00 ` Alistair Francis
2023-09-25 3:30 ` [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Alistair Francis
19 siblings, 2 replies; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-20 11:20 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, philmd, ajones, Daniel Henrique Barboza
Priv spec validation is TCG specific. Move it to the TCG accel class.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 38 --------------------------------------
target/riscv/cpu.h | 2 --
target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
3 files changed, 38 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e97ba3df93..eeeb08a35a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
*ext_enabled = en;
}
-int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
-{
- const RISCVIsaExtData *edata;
-
- for (edata = isa_edata_arr; edata && edata->name; edata++) {
- if (edata->ext_enable_offset != ext_offset) {
- continue;
- }
-
- return edata->min_version;
- }
-
- g_assert_not_reached();
-}
-
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
-void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
-{
- CPURISCVState *env = &cpu->env;
- const RISCVIsaExtData *edata;
-
- /* Force disable extensions if priv spec version does not match */
- for (edata = isa_edata_arr; edata && edata->name; edata++) {
- if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
- (env->priv_ver < edata->min_version)) {
- isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
-#ifndef CONFIG_USER_ONLY
- warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
- " because privilege spec version does not match",
- edata->name, env->mhartid);
-#else
- warn_report("disabling %s extension because "
- "privilege spec version does not match",
- edata->name);
-#endif
- }
- }
-}
-
#ifndef CONFIG_USER_ONLY
static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
{
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dfcd0732f..219fe2e9b5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -711,9 +711,7 @@ enum riscv_pmu_event_idx {
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
-int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
-void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
typedef struct RISCVCPUMultiExtConfig {
const char *name;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c326ab37a2..8c052d6fcd 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -99,6 +99,21 @@ static const struct TCGCPUOps riscv_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
+static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+{
+ const RISCVIsaExtData *edata;
+
+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
+ if (edata->ext_enable_offset != ext_offset) {
+ continue;
+ }
+
+ return edata->min_version;
+ }
+
+ g_assert_not_reached();
+}
+
static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
bool value)
{
@@ -226,6 +241,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
}
}
+static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+{
+ CPURISCVState *env = &cpu->env;
+ const RISCVIsaExtData *edata;
+
+ /* Force disable extensions if priv spec version does not match */
+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
+ if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
+ (env->priv_ver < edata->min_version)) {
+ isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
+#ifndef CONFIG_USER_ONLY
+ warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+ " because privilege spec version does not match",
+ edata->name, env->mhartid);
+#else
+ warn_report("disabling %s extension because "
+ "privilege spec version does not match",
+ edata->name);
+#endif
+ }
+ }
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
--
2.41.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass
2023-09-20 11:20 ` [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
@ 2023-09-22 5:24 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:24 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:22 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> target/riscv/cpu.c needs to handle all possible accelerators (TCG and
> KVM at this moment) during both init() and realize() time. This forces
> us to resort to a lot of "if tcg" and "if kvm" throughout the code,
> which isn't wrong, but can get cluttered over time. Splitting
> acceleration specific code from cpu.c to its own file will help to
> declutter the existing code and it will also make it easier to support
> KVM/TCG only builds in the future.
>
> We'll start by adding a new subdir called 'tcg' and a new file called
> 'tcg-cpu.c'. This file will be used to introduce a new accelerator class
> for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
> code in its file instead of using 'cpu.c' for everything. This design is
> inpired by the work Claudio Fontana did in x86 a few years ago in commit
> f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
> AccelCPUClass").
>
> To avoid moving too much code at once we'll start by adding the new file
> and TCG AccelCPUClass declaration. The 'class_init' from the accel class
> will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
> doing it.
>
> 'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
> to deal with moving code and files around right now. We'll focus on
> decoupling the realize() logic first.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 5 +---
> target/riscv/cpu.h | 4 +++
> target/riscv/meson.build | 2 ++
> target/riscv/tcg/meson.build | 2 ++
> target/riscv/tcg/tcg-cpu.c | 58 ++++++++++++++++++++++++++++++++++++
> 5 files changed, 67 insertions(+), 4 deletions(-)
> create mode 100644 target/riscv/tcg/meson.build
> create mode 100644 target/riscv/tcg/tcg-cpu.c
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2644638b11..e72c49c881 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2288,9 +2288,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> };
> #endif
>
> -#include "hw/core/tcg-cpu-ops.h"
> -
> -static const struct TCGCPUOps riscv_tcg_ops = {
> +const struct TCGCPUOps riscv_tcg_ops = {
> .initialize = riscv_translate_init,
> .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> .restore_state_to_opc = riscv_restore_state_to_opc,
> @@ -2449,7 +2447,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> #endif
> cc->gdb_arch_name = riscv_gdb_arch_name;
> cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
> - cc->tcg_ops = &riscv_tcg_ops;
>
> object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
> cpu_set_mvendorid, NULL, NULL);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7d6cfb07ea..16a2dfa8c7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -707,6 +707,10 @@ enum riscv_pmu_event_idx {
> RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
> };
>
> +/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
> +#include "hw/core/tcg-cpu-ops.h"
> +extern const struct TCGCPUOps riscv_tcg_ops;
> +
> /* CSR function table */
> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
>
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 660078bda1..f0486183fa 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -38,5 +38,7 @@ riscv_system_ss.add(files(
> 'riscv-qmp-cmds.c',
> ))
>
> +subdir('tcg')
> +
> target_arch += {'riscv': riscv_ss}
> target_softmmu_arch += {'riscv': riscv_system_ss}
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> new file mode 100644
> index 0000000000..061df3d74a
> --- /dev/null
> +++ b/target/riscv/tcg/meson.build
> @@ -0,0 +1,2 @@
> +riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
> + 'tcg-cpu.c'))
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> new file mode 100644
> index 0000000000..0326cead0d
> --- /dev/null
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -0,0 +1,58 @@
> +/*
> + * riscv TCG cpu class initialization
> + *
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "qemu/accel.h"
> +#include "hw/core/accel-cpu.h"
> +
> +static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
> +{
> + /*
> + * All cpus use the same set of operations.
> + * riscv_tcg_ops is being imported from cpu.c for now.
> + */
> + cc->tcg_ops = &riscv_tcg_ops;
> +}
> +
> +static void tcg_cpu_class_init(CPUClass *cc)
> +{
> + cc->init_accel_cpu = tcg_cpu_init_ops;
> +}
> +
> +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
> +{
> + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
> +
> + acc->cpu_class_init = tcg_cpu_class_init;
> +}
> +
> +static const TypeInfo tcg_cpu_accel_type_info = {
> + .name = ACCEL_CPU_NAME("tcg"),
> +
> + .parent = TYPE_ACCEL_CPU,
> + .class_init = tcg_cpu_accel_class_init,
> + .abstract = true,
> +};
> +
> +static void tcg_cpu_accel_register_types(void)
> +{
> + type_register_static(&tcg_cpu_accel_type_info);
> +}
> +type_init(tcg_cpu_accel_register_types);
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
2023-09-20 11:20 ` [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
@ 2023-09-22 5:29 ` Alistair Francis
2023-09-25 9:17 ` Daniel Henrique Barboza
0 siblings, 1 reply; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:29 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
> realize() path during the common riscv_cpu_realize(), making it a good
> choice to start moving TCG exclusive code to tcg-cpu.c.
>
> Rename it to tcg_cpu_realizefn() and assign it as a implementation of
> accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
> riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
> approach with KVM in the near future.
>
> riscv_cpu_validate_set_extensions() is too big and with too many
> dependencies to be moved in this same patch. We'll do that next.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/cpu.c | 128 -----------------------------------
> target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 133 insertions(+), 128 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e72c49c881..030629294f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -23,9 +23,7 @@
> #include "qemu/log.h"
> #include "cpu.h"
> #include "cpu_vendorid.h"
> -#include "pmu.h"
> #include "internals.h"
> -#include "time_helper.h"
> #include "exec/exec-all.h"
> #include "qapi/error.h"
> #include "qapi/visitor.h"
> @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> }
> }
>
> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> -{
> - CPURISCVState *env = &cpu->env;
> - int priv_version = -1;
> -
> - if (cpu->cfg.priv_spec) {
> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> - priv_version = PRIV_VERSION_1_12_0;
> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> - priv_version = PRIV_VERSION_1_11_0;
> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> - priv_version = PRIV_VERSION_1_10_0;
> - } else {
> - error_setg(errp,
> - "Unsupported privilege spec version '%s'",
> - cpu->cfg.priv_spec);
> - return;
> - }
> -
> - env->priv_ver = priv_version;
> - }
> -}
> -
> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> {
> CPURISCVState *env = &cpu->env;
> @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> }
> }
>
> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> -{
> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> - CPUClass *cc = CPU_CLASS(mcc);
> - CPURISCVState *env = &cpu->env;
> -
> - /* Validate that MISA_MXL is set properly. */
> - switch (env->misa_mxl_max) {
> -#ifdef TARGET_RISCV64
> - case MXL_RV64:
> - case MXL_RV128:
> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> - break;
> -#endif
> - case MXL_RV32:
> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> - break;
> - default:
> - g_assert_not_reached();
> - }
> -
> - if (env->misa_mxl_max != env->misa_mxl) {
> - error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
> - return;
> - }
> -}
> -
> /*
> * Check consistency between chosen extensions while setting
> * cpu->cfg accordingly.
> @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> #endif
> }
>
> -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> -{
> - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> - error_setg(errp, "H extension requires priv spec 1.12.0");
> - return;
> - }
> -}
> -
> -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
> -{
> - RISCVCPU *cpu = RISCV_CPU(dev);
> - CPURISCVState *env = &cpu->env;
> - Error *local_err = NULL;
> -
> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
> - error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
> - return;
> - }
> -
> - riscv_cpu_validate_misa_mxl(cpu, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> - riscv_cpu_validate_priv_spec(cpu, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> - riscv_cpu_validate_misa_priv(env, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> - /*
> - * Enhanced PMP should only be available
> - * on harts with PMP support
> - */
> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> - return;
> - }
> -
> - riscv_cpu_validate_set_extensions(cpu, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> -#ifndef CONFIG_USER_ONLY
> - CPU(dev)->tcg_cflags |= CF_PCREL;
> -
> - if (cpu->cfg.ext_sstc) {
> - riscv_timer_init(cpu);
> - }
> -
> - if (cpu->cfg.pmu_num) {
> - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
> - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> - riscv_pmu_timer_cb, cpu);
> - }
> - }
> -#endif
> -}
> -
> static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> {
> CPUState *cs = CPU(dev);
> @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (tcg_enabled()) {
> - riscv_cpu_realize_tcg(dev, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> - }
> -
> riscv_cpu_finalize_features(cpu, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 0326cead0d..f47dc2064f 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -18,10 +18,142 @@
> */
I do think we should keep the Copyright statements from cpu.c in this
new file as you are now copying across the majority of code from there
Alistair
>
> #include "qemu/osdep.h"
> +#include "exec/exec-all.h"
> #include "cpu.h"
> +#include "pmu.h"
> +#include "time_helper.h"
> +#include "qapi/error.h"
> #include "qemu/accel.h"
> #include "hw/core/accel-cpu.h"
>
> +
> +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> +{
> + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> + error_setg(errp, "H extension requires priv spec 1.12.0");
> + return;
> + }
> +}
> +
> +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> + CPUClass *cc = CPU_CLASS(mcc);
> + CPURISCVState *env = &cpu->env;
> +
> + /* Validate that MISA_MXL is set properly. */
> + switch (env->misa_mxl_max) {
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + case MXL_RV128:
> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> + break;
> +#endif
> + case MXL_RV32:
> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + if (env->misa_mxl_max != env->misa_mxl) {
> + error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
> + return;
> + }
> +}
> +
> +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> +{
> + CPURISCVState *env = &cpu->env;
> + int priv_version = -1;
> +
> + if (cpu->cfg.priv_spec) {
> + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> + priv_version = PRIV_VERSION_1_12_0;
> + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> + priv_version = PRIV_VERSION_1_11_0;
> + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> + priv_version = PRIV_VERSION_1_10_0;
> + } else {
> + error_setg(errp,
> + "Unsupported privilege spec version '%s'",
> + cpu->cfg.priv_spec);
> + return;
> + }
> +
> + env->priv_ver = priv_version;
> + }
> +}
> +
> +/*
> + * We'll get here via the following path:
> + *
> + * riscv_cpu_realize()
> + * -> cpu_exec_realizefn()
> + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn())
> + */
> +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + Error *local_err = NULL;
> +
> + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
> + error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
> + return false;
> + }
> +
> + riscv_cpu_validate_misa_mxl(cpu, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return false;
> + }
> +
> + riscv_cpu_validate_priv_spec(cpu, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return false;
> + }
> +
> + riscv_cpu_validate_misa_priv(env, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return false;
> + }
> +
> + if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> + /*
> + * Enhanced PMP should only be available
> + * on harts with PMP support
> + */
> + error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> + return false;
> + }
> +
> + riscv_cpu_validate_set_extensions(cpu, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return false;
> + }
> +
> +#ifndef CONFIG_USER_ONLY
> + CPU(cs)->tcg_cflags |= CF_PCREL;
> +
> + if (cpu->cfg.ext_sstc) {
> + riscv_timer_init(cpu);
> + }
> +
> + if (cpu->cfg.pmu_num) {
> + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
> + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> + riscv_pmu_timer_cb, cpu);
> + }
> + }
> +#endif
> +
> + return true;
> +}
> +
> static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
> {
> /*
> @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
> AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
>
> acc->cpu_class_init = tcg_cpu_class_init;
> + acc->cpu_realizefn = tcg_cpu_realizefn;
> }
>
> static const TypeInfo tcg_cpu_accel_type_info = {
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
2023-09-20 11:20 ` [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
@ 2023-09-22 5:32 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:32 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 10:25 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This function is the core of the RISC-V validations for TCG CPUs, and it
> has a lot going on.
>
> Functions in cpu.c were made public to allow them to be used by the KVM
> accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably
> hard to move it to another file due to its dependency with isa_edata_arr[]
> array, thus make it public and use it as is for now.
>
> riscv_cpu_validate_set_extensions() is kept public because it's used by
> csr.c in write_misa().
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 361 +------------------------------------
> target/riscv/cpu.h | 8 +-
> target/riscv/csr.c | 1 +
> target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++
> target/riscv/tcg/tcg-cpu.h | 27 +++
> 5 files changed, 397 insertions(+), 357 deletions(-)
> create mode 100644 target/riscv/tcg/tcg-cpu.h
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 030629294f..7215a29324 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] = {
> /* Hash that stores user set extensions */
> static GHashTable *multi_ext_user_opts;
>
> -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> {
> bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
>
> return *ext_enabled;
> }
>
> -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
> - bool en)
> +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
> {
> bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
>
> *ext_enabled = en;
> }
>
> -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> +int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> {
> int i;
>
> @@ -193,38 +192,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> g_assert_not_reached();
> }
>
> -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> {
> return g_hash_table_contains(multi_ext_user_opts,
> GUINT_TO_POINTER(ext_offset));
> }
>
> -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> - bool value)
> -{
> - CPURISCVState *env = &cpu->env;
> - bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
> - int min_version;
> -
> - if (prev_val == value) {
> - return;
> - }
> -
> - if (cpu_cfg_ext_is_user_set(ext_offset)) {
> - return;
> - }
> -
> - if (value && env->priv_ver != PRIV_VERSION_LATEST) {
> - /* Do not enable it if priv_ver is older than min_version */
> - min_version = cpu_cfg_ext_get_min_version(ext_offset);
> - if (env->priv_ver < min_version) {
> - return;
> - }
> - }
> -
> - isa_ext_update_enabled(cpu, ext_offset, value);
> -}
> -
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -1023,46 +996,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> }
> }
>
> -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> - Error **errp)
> -{
> - if (!is_power_of_2(cfg->vlen)) {
> - error_setg(errp, "Vector extension VLEN must be power of 2");
> - return;
> - }
> - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
> - error_setg(errp,
> - "Vector extension implementation only supports VLEN "
> - "in the range [128, %d]", RV_VLEN_MAX);
> - return;
> - }
> - if (!is_power_of_2(cfg->elen)) {
> - error_setg(errp, "Vector extension ELEN must be power of 2");
> - return;
> - }
> - if (cfg->elen > 64 || cfg->elen < 8) {
> - error_setg(errp,
> - "Vector extension implementation only supports ELEN "
> - "in the range [8, 64]");
> - return;
> - }
> - if (cfg->vext_spec) {
> - if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
> - env->vext_ver = VEXT_VERSION_1_00_0;
> - } else {
> - error_setg(errp, "Unsupported vector spec version '%s'",
> - cfg->vext_spec);
> - return;
> - }
> - } else if (env->vext_ver == 0) {
> - qemu_log("vector version is not specified, "
> - "use the default value v1.0\n");
> -
> - env->vext_ver = VEXT_VERSION_1_00_0;
> - }
> -}
> -
> -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> {
> CPURISCVState *env = &cpu->env;
> int i;
> @@ -1086,291 +1020,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> }
> }
>
> -/*
> - * Check consistency between chosen extensions while setting
> - * cpu->cfg accordingly.
> - */
> -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> -{
> - CPURISCVState *env = &cpu->env;
> - Error *local_err = NULL;
> -
> - /* Do some ISA extension error checking */
> - if (riscv_has_ext(env, RVG) &&
> - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
> - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
> - riscv_has_ext(env, RVD) &&
> - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> -
> - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
> - !cpu->cfg.ext_icsr) {
> - error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
> - return;
> - }
> -
> - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
> - !cpu->cfg.ext_ifencei) {
> - error_setg(errp, "RVG requires Zifencei but user set "
> - "Zifencei to false");
> - return;
> - }
> -
> - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
> -
> - env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
> - env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> - }
> -
> - if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
> - error_setg(errp,
> - "I and E extensions are incompatible");
> - return;
> - }
> -
> - if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
> - error_setg(errp,
> - "Either I or E extension must be set");
> - return;
> - }
> -
> - if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
> - error_setg(errp,
> - "Setting S extension without U extension is illegal");
> - return;
> - }
> -
> - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
> - error_setg(errp,
> - "H depends on an I base integer ISA with 32 x registers");
> - return;
> - }
> -
> - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
> - error_setg(errp, "H extension implicitly requires S-mode");
> - return;
> - }
> -
> - if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
> - error_setg(errp, "F extension requires Zicsr");
> - return;
> - }
> -
> - if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
> - error_setg(errp, "Zawrs extension requires A extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
> - error_setg(errp, "Zfa extension requires F extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zfh) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
> - }
> -
> - if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
> - error_setg(errp, "Zfh/Zfhmin extensions require F extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
> - error_setg(errp, "Zfbfmin extension depends on F extension");
> - return;
> - }
> -
> - if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
> - error_setg(errp, "D extension requires F extension");
> - return;
> - }
> -
> - if (riscv_has_ext(env, RVV)) {
> - riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> - /* The V vector extension depends on the Zve64d extension */
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
> - }
> -
> - /* The Zve64d extension depends on the Zve64f extension */
> - if (cpu->cfg.ext_zve64d) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
> - }
> -
> - /* The Zve64f extension depends on the Zve32f extension */
> - if (cpu->cfg.ext_zve64f) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
> - }
> -
> - if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
> - error_setg(errp, "Zve64d/V extensions require D extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
> - error_setg(errp, "Zve32f/Zve64f extensions require F extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zvfh) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
> - }
> -
> - if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
> - error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
> - error_setg(errp, "Zvfh extensions requires Zfhmin extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
> - error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
> - error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
> - error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
> - return;
> - }
> -
> - /* Set the ISA extensions, checks should have happened above */
> - if (cpu->cfg.ext_zhinx) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> - }
> -
> - if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
> - error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zfinx) {
> - if (!cpu->cfg.ext_icsr) {
> - error_setg(errp, "Zfinx extension requires Zicsr");
> - return;
> - }
> - if (riscv_has_ext(env, RVF)) {
> - error_setg(errp,
> - "Zfinx cannot be supported together with F extension");
> - return;
> - }
> - }
> -
> - if (cpu->cfg.ext_zce) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
> - if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> - }
> - }
> -
> - /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
> - if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> - if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> - }
> - if (riscv_has_ext(env, RVD)) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
> - }
> - }
> -
> - if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> - error_setg(errp, "Zcf extension is only relevant to RV32");
> - return;
> - }
> -
> - if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
> - error_setg(errp, "Zcf extension requires F extension");
> - return;
> - }
> -
> - if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
> - error_setg(errp, "Zcd extension requires D extension");
> - return;
> - }
> -
> - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
> - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
> - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
> - "extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
> - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
> - "Zcd extension");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
> - error_setg(errp, "Zcmt extension requires Zicsr extension");
> - return;
> - }
> -
> - /*
> - * In principle Zve*x would also suffice here, were they supported
> - * in qemu
> - */
> - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
> - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
> - !cpu->cfg.ext_zve32f) {
> - error_setg(errp,
> - "Vector crypto extensions require V or Zve* extensions");
> - return;
> - }
> -
> - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
> - error_setg(
> - errp,
> - "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
> - return;
> - }
> -
> - if (cpu->cfg.ext_zk) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
> - }
> -
> - if (cpu->cfg.ext_zkn) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
> - }
> -
> - if (cpu->cfg.ext_zks) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
> - }
> -
> - /*
> - * Disable isa extensions based on priv spec after we
> - * validated and set everything we need.
> - */
> - riscv_cpu_disable_priv_spec_isa_exts(cpu);
> -}
> -
> #ifndef CONFIG_USER_ONLY
> static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
> {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 16a2dfa8c7..409d198635 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -445,7 +445,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> bool probe, uintptr_t retaddr);
> char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(void);
> -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
>
> #define cpu_list riscv_cpu_list
> #define cpu_mmu_index riscv_cpu_mmu_index
> @@ -711,6 +710,13 @@ enum riscv_pmu_event_idx {
> #include "hw/core/tcg-cpu-ops.h"
> extern const struct TCGCPUOps riscv_tcg_ops;
>
> +/* used by tcg/tcg-cpu.c*/
> +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
> +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> +int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
> +
> /* CSR function table */
> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 85a31dc420..4b4ab56c40 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -21,6 +21,7 @@
> #include "qemu/log.h"
> #include "qemu/timer.h"
> #include "cpu.h"
> +#include "tcg/tcg-cpu.h"
> #include "pmu.h"
> #include "time_helper.h"
> #include "exec/exec-all.h"
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index f47dc2064f..d86172f725 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -19,14 +19,43 @@
>
> #include "qemu/osdep.h"
> #include "exec/exec-all.h"
> +#include "tcg-cpu.h"
> #include "cpu.h"
> #include "pmu.h"
> #include "time_helper.h"
> #include "qapi/error.h"
> #include "qemu/accel.h"
> +#include "qemu/error-report.h"
> +#include "qemu/log.h"
> #include "hw/core/accel-cpu.h"
>
>
> +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> + bool value)
> +{
> + CPURISCVState *env = &cpu->env;
> + bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
> + int min_version;
> +
> + if (prev_val == value) {
> + return;
> + }
> +
> + if (cpu_cfg_ext_is_user_set(ext_offset)) {
> + return;
> + }
> +
> + if (value && env->priv_ver != PRIV_VERSION_LATEST) {
> + /* Do not enable it if priv_ver is older than min_version */
> + min_version = cpu_cfg_ext_get_min_version(ext_offset);
> + if (env->priv_ver < min_version) {
> + return;
> + }
> + }
> +
> + isa_ext_update_enabled(cpu, ext_offset, value);
> +}
> +
> static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> {
> if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> @@ -85,6 +114,334 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> }
> }
>
> +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> + Error **errp)
> +{
> + if (!is_power_of_2(cfg->vlen)) {
> + error_setg(errp, "Vector extension VLEN must be power of 2");
> + return;
> + }
> +
> + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
> + error_setg(errp,
> + "Vector extension implementation only supports VLEN "
> + "in the range [128, %d]", RV_VLEN_MAX);
> + return;
> + }
> +
> + if (!is_power_of_2(cfg->elen)) {
> + error_setg(errp, "Vector extension ELEN must be power of 2");
> + return;
> + }
> +
> + if (cfg->elen > 64 || cfg->elen < 8) {
> + error_setg(errp,
> + "Vector extension implementation only supports ELEN "
> + "in the range [8, 64]");
> + return;
> + }
> +
> + if (cfg->vext_spec) {
> + if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
> + env->vext_ver = VEXT_VERSION_1_00_0;
> + } else {
> + error_setg(errp, "Unsupported vector spec version '%s'",
> + cfg->vext_spec);
> + return;
> + }
> + } else if (env->vext_ver == 0) {
> + qemu_log("vector version is not specified, "
> + "use the default value v1.0\n");
> +
> + env->vext_ver = VEXT_VERSION_1_00_0;
> + }
> +}
> +
> +/*
> + * Check consistency between chosen extensions while setting
> + * cpu->cfg accordingly.
> + */
> +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> +{
> + CPURISCVState *env = &cpu->env;
> + Error *local_err = NULL;
> +
> + /* Do some ISA extension error checking */
> + if (riscv_has_ext(env, RVG) &&
> + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
> + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
> + riscv_has_ext(env, RVD) &&
> + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> +
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
> + !cpu->cfg.ext_icsr) {
> + error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
> + return;
> + }
> +
> + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
> + !cpu->cfg.ext_ifencei) {
> + error_setg(errp, "RVG requires Zifencei but user set "
> + "Zifencei to false");
> + return;
> + }
> +
> + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
> +
> + env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
> + env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> + }
> +
> + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
> + error_setg(errp,
> + "I and E extensions are incompatible");
> + return;
> + }
> +
> + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
> + error_setg(errp,
> + "Either I or E extension must be set");
> + return;
> + }
> +
> + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
> + error_setg(errp,
> + "Setting S extension without U extension is illegal");
> + return;
> + }
> +
> + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
> + error_setg(errp,
> + "H depends on an I base integer ISA with 32 x registers");
> + return;
> + }
> +
> + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
> + error_setg(errp, "H extension implicitly requires S-mode");
> + return;
> + }
> +
> + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
> + error_setg(errp, "F extension requires Zicsr");
> + return;
> + }
> +
> + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
> + error_setg(errp, "Zawrs extension requires A extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "Zfa extension requires F extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zfh) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
> + }
> +
> + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "Zfh/Zfhmin extensions require F extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "Zfbfmin extension depends on F extension");
> + return;
> + }
> +
> + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "D extension requires F extension");
> + return;
> + }
> +
> + if (riscv_has_ext(env, RVV)) {
> + riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + /* The V vector extension depends on the Zve64d extension */
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
> + }
> +
> + /* The Zve64d extension depends on the Zve64f extension */
> + if (cpu->cfg.ext_zve64d) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
> + }
> +
> + /* The Zve64f extension depends on the Zve32f extension */
> + if (cpu->cfg.ext_zve64f) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
> + }
> +
> + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
> + error_setg(errp, "Zve64d/V extensions require D extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
> + error_setg(errp, "Zve32f/Zve64f extensions require F extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfh) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
> + }
> +
> + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
> + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
> + error_setg(errp, "Zvfh extensions requires Zfhmin extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
> + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
> + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
> + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
> + return;
> + }
> +
> + /* Set the ISA extensions, checks should have happened above */
> + if (cpu->cfg.ext_zhinx) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> + }
> +
> + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
> + error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zfinx) {
> + if (!cpu->cfg.ext_icsr) {
> + error_setg(errp, "Zfinx extension requires Zicsr");
> + return;
> + }
> + if (riscv_has_ext(env, RVF)) {
> + error_setg(errp,
> + "Zfinx cannot be supported together with F extension");
> + return;
> + }
> + }
> +
> + if (cpu->cfg.ext_zce) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
> + if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> + }
> + }
> +
> + /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
> + if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> + if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> + }
> + if (riscv_has_ext(env, RVD)) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
> + }
> + }
> +
> + if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> + error_setg(errp, "Zcf extension is only relevant to RV32");
> + return;
> + }
> +
> + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
> + error_setg(errp, "Zcf extension requires F extension");
> + return;
> + }
> +
> + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
> + error_setg(errp, "Zcd extension requires D extension");
> + return;
> + }
> +
> + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
> + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
> + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
> + "extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
> + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
> + "Zcd extension");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
> + error_setg(errp, "Zcmt extension requires Zicsr extension");
> + return;
> + }
> +
> + /*
> + * In principle Zve*x would also suffice here, were they supported
> + * in qemu
> + */
> + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
> + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
> + !cpu->cfg.ext_zve32f) {
> + error_setg(errp,
> + "Vector crypto extensions require V or Zve* extensions");
> + return;
> + }
> +
> + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
> + error_setg(
> + errp,
> + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zk) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
> + }
> +
> + if (cpu->cfg.ext_zkn) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
> + }
> +
> + if (cpu->cfg.ext_zks) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
> + }
> +
> + /*
> + * Disable isa extensions based on priv spec after we
> + * validated and set everything we need.
> + */
> + riscv_cpu_disable_priv_spec_isa_exts(cpu);
> +}
> +
> /*
> * We'll get here via the following path:
> *
> diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
> new file mode 100644
> index 0000000000..630184759d
> --- /dev/null
> +++ b/target/riscv/tcg/tcg-cpu.h
> @@ -0,0 +1,27 @@
> +/*
> + * riscv TCG cpu class initialization
> + *
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef RISCV_TCG_CPU_H
> +#define RISCV_TCG_CPU_H
> +
> +#include "cpu.h"
> +
> +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
> +
> +#endif
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c
2023-09-20 11:20 ` [PATCH v3 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
@ 2023-09-22 5:34 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:34 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:21 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Move the remaining of riscv_tcg_ops now that we have a working realize()
> implementation.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 58 ------------------------------------
> target/riscv/cpu.h | 4 ---
> target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
> 3 files changed, 59 insertions(+), 63 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7215a29324..9426b3b9d6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
> return env->pc;
> }
>
> -static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> - const TranslationBlock *tb)
> -{
> - if (!(tb_cflags(tb) & CF_PCREL)) {
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> - RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> -
> - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> -
> - if (xl == MXL_RV32) {
> - env->pc = (int32_t) tb->pc;
> - } else {
> - env->pc = tb->pc;
> - }
> - }
> -}
> -
> static bool riscv_cpu_has_work(CPUState *cs)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs)
> #endif
> }
>
> -static void riscv_restore_state_to_opc(CPUState *cs,
> - const TranslationBlock *tb,
> - const uint64_t *data)
> -{
> - RISCVCPU *cpu = RISCV_CPU(cs);
> - CPURISCVState *env = &cpu->env;
> - RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> - target_ulong pc;
> -
> - if (tb_cflags(tb) & CF_PCREL) {
> - pc = (env->pc & TARGET_PAGE_MASK) | data[0];
> - } else {
> - pc = data[0];
> - }
> -
> - if (xl == MXL_RV32) {
> - env->pc = (int32_t)pc;
> - } else {
> - env->pc = pc;
> - }
> - env->bins = data[1];
> -}
> -
> static void riscv_cpu_reset_hold(Object *obj)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -1809,23 +1768,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> };
> #endif
>
> -const struct TCGCPUOps riscv_tcg_ops = {
> - .initialize = riscv_translate_init,
> - .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> - .restore_state_to_opc = riscv_restore_state_to_opc,
> -
> -#ifndef CONFIG_USER_ONLY
> - .tlb_fill = riscv_cpu_tlb_fill,
> - .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> - .do_interrupt = riscv_cpu_do_interrupt,
> - .do_transaction_failed = riscv_cpu_do_transaction_failed,
> - .do_unaligned_access = riscv_cpu_do_unaligned_access,
> - .debug_excp_handler = riscv_cpu_debug_excp_handler,
> - .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
> - .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
> -#endif /* !CONFIG_USER_ONLY */
> -};
> -
> static bool riscv_cpu_is_dynamic(Object *cpu_obj)
> {
> return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 409d198635..b2e558f730 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -706,10 +706,6 @@ enum riscv_pmu_event_idx {
> RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
> };
>
> -/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
> -#include "hw/core/tcg-cpu-ops.h"
> -extern const struct TCGCPUOps riscv_tcg_ops;
> -
> /* used by tcg/tcg-cpu.c*/
> void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index d86172f725..e480b9f726 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -28,7 +28,66 @@
> #include "qemu/error-report.h"
> #include "qemu/log.h"
> #include "hw/core/accel-cpu.h"
> +#include "hw/core/tcg-cpu-ops.h"
> +#include "tcg/tcg.h"
>
> +static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> + const TranslationBlock *tb)
> +{
> + if (!(tb_cflags(tb) & CF_PCREL)) {
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +
> + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> +
> + if (xl == MXL_RV32) {
> + env->pc = (int32_t) tb->pc;
> + } else {
> + env->pc = tb->pc;
> + }
> + }
> +}
> +
> +static void riscv_restore_state_to_opc(CPUState *cs,
> + const TranslationBlock *tb,
> + const uint64_t *data)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> + target_ulong pc;
> +
> + if (tb_cflags(tb) & CF_PCREL) {
> + pc = (env->pc & TARGET_PAGE_MASK) | data[0];
> + } else {
> + pc = data[0];
> + }
> +
> + if (xl == MXL_RV32) {
> + env->pc = (int32_t)pc;
> + } else {
> + env->pc = pc;
> + }
> + env->bins = data[1];
> +}
> +
> +static const struct TCGCPUOps riscv_tcg_ops = {
> + .initialize = riscv_translate_init,
> + .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> + .restore_state_to_opc = riscv_restore_state_to_opc,
> +
> +#ifndef CONFIG_USER_ONLY
> + .tlb_fill = riscv_cpu_tlb_fill,
> + .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> + .do_interrupt = riscv_cpu_do_interrupt,
> + .do_transaction_failed = riscv_cpu_do_transaction_failed,
> + .do_unaligned_access = riscv_cpu_do_unaligned_access,
> + .debug_excp_handler = riscv_cpu_debug_excp_handler,
> + .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
> + .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
> +#endif /* !CONFIG_USER_ONLY */
> +};
>
> static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> bool value)
> @@ -515,7 +574,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
> {
> /*
> * All cpus use the same set of operations.
> - * riscv_tcg_ops is being imported from cpu.c for now.
> */
> cc->tcg_ops = &riscv_tcg_ops;
> }
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init()
2023-09-20 11:20 ` [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
@ 2023-09-22 5:51 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:51 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
> calls riscv_init_max_cpu_extensions(). Both can be moved to a common
> instance_post_init() callback, implemented in riscv_cpu_post_init(),
> called by all CPUs. The call order then becomes:
>
> riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
>
> In the near future riscv_cpu_post_init() will call the init() function
> of the current accelerator, providing a hook for KVM and TCG accel
> classes to change the init() process of the CPU.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
> 1 file changed, 32 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9426b3b9d6..848b58e7c4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj)
> mlx = MXL_RV32;
> #endif
> set_misa(env, mlx, 0);
> - riscv_cpu_add_user_properties(obj);
> - riscv_init_max_cpu_extensions(obj);
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
> @@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> set_misa(env, MXL_RV64, 0);
> - riscv_cpu_add_user_properties(obj);
> /* Set latest version of privileged specification */
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> @@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> set_misa(env, MXL_RV128, 0);
> - riscv_cpu_add_user_properties(obj);
> /* Set latest version of privileged specification */
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> @@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> set_misa(env, MXL_RV32, 0);
> - riscv_cpu_add_user_properties(obj);
> /* Set latest version of privileged specification */
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> @@ -666,7 +661,6 @@ static void riscv_host_cpu_init(Object *obj)
> #elif defined(TARGET_RISCV64)
> set_misa(env, MXL_RV64, 0);
> #endif
> - riscv_cpu_add_user_properties(obj);
> }
> #endif /* CONFIG_KVM */
>
> @@ -1215,6 +1209,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
> }
> #endif /* CONFIG_USER_ONLY */
>
> +static bool riscv_cpu_is_dynamic(Object *cpu_obj)
> +{
> + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
> +}
> +
> +static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
> +{
> + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
> +}
> +
> +static bool riscv_cpu_has_user_properties(Object *cpu_obj)
> +{
> + if (kvm_enabled() &&
> + object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
> + return true;
> + }
> +
> + return riscv_cpu_is_dynamic(cpu_obj);
> +}
> +
> +static void riscv_cpu_post_init(Object *obj)
> +{
> + if (riscv_cpu_has_user_properties(obj)) {
> + riscv_cpu_add_user_properties(obj);
> + }
> +
> + if (riscv_cpu_has_max_extensions(obj)) {
> + riscv_init_max_cpu_extensions(obj);
> + }
> +}
> +
> static void riscv_cpu_init(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> @@ -1768,11 +1793,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> };
> #endif
>
> -static bool riscv_cpu_is_dynamic(Object *cpu_obj)
> -{
> - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
> -}
> -
> static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
> void *opaque, Error **errp)
> {
> @@ -2009,6 +2029,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .instance_size = sizeof(RISCVCPU),
> .instance_align = __alignof__(RISCVCPU),
> .instance_init = riscv_cpu_init,
> + .instance_post_init = riscv_cpu_post_init,
> .abstract = true,
> .class_size = sizeof(RISCVCPUClass),
> .class_init = riscv_cpu_class_init,
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c
2023-09-20 11:20 ` [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
@ 2023-09-22 5:53 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:53 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:22 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This CPU only exists if we're compiling with KVM so move it to the kvm
> specific file.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 15 ---------------
> target/riscv/kvm.c | 21 +++++++++++++++++++++
> 2 files changed, 21 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 848b58e7c4..f8368ce274 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -652,18 +652,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> }
> #endif
>
> -#if defined(CONFIG_KVM)
> -static void riscv_host_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> -#if defined(TARGET_RISCV32)
> - set_misa(env, MXL_RV32, 0);
> -#elif defined(TARGET_RISCV64)
> - set_misa(env, MXL_RV64, 0);
> -#endif
> -}
> -#endif /* CONFIG_KVM */
> -
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> {
> ObjectClass *oc;
> @@ -2041,9 +2029,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> },
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
> -#if defined(CONFIG_KVM)
> - DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
> -#endif
> #if defined(TARGET_RISCV32)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 1e4e4456b3..31d2ede4b6 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -1271,3 +1271,24 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
>
> kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
> }
> +
> +static void riscv_host_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> +
> +#if defined(TARGET_RISCV32)
> + env->misa_mxl_max = env->misa_mxl = MXL_RV32;
> +#elif defined(TARGET_RISCV64)
> + env->misa_mxl_max = env->misa_mxl = MXL_RV64;
> +#endif
> +}
> +
> +static const TypeInfo riscv_kvm_cpu_type_infos[] = {
> + {
> + .name = TYPE_RISCV_CPU_HOST,
> + .parent = TYPE_RISCV_CPU,
> + .instance_init = riscv_host_cpu_init,
> + }
> +};
> +
> +DEFINE_TYPES(riscv_kvm_cpu_type_infos)
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const'
2023-09-20 11:20 ` [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
@ 2023-09-22 5:54 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:54 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:21 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We'll need to export these arrays to the accelerator classes in the next
> patches. Mark them as 'const' now because they should not be modified at
> runtime.
>
> Note that 'riscv_cpu_options' will also be exported, but can't be marked
> as 'const', because the properties are changed via
> qdev_property_add_static().
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 22 +++++++++++++---------
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f8368ce274..048a2dbc77 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig {
> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
> .enabled = _defval}
>
> -static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> +static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> /* Defaults for standard extensions */
> MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
> @@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> +static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
> MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
> MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
> @@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> };
>
> /* These are experimental so mark with 'x-' */
> -static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> +static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> /* ePMP 0.9.3 */
> MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
> MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
> @@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> }
>
> static void cpu_add_multi_ext_prop(Object *cpu_obj,
> - RISCVCPUMultiExtConfig *multi_cfg)
> + const RISCVCPUMultiExtConfig *multi_cfg)
> {
> object_property_add(cpu_obj, multi_cfg->name, "bool",
> cpu_get_multi_ext_cfg,
> @@ -1575,11 +1575,13 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
> }
>
> static void riscv_cpu_add_multiext_prop_array(Object *obj,
> - RISCVCPUMultiExtConfig *array)
> + const RISCVCPUMultiExtConfig *array)
> {
> + const RISCVCPUMultiExtConfig *prop;
> +
> g_assert(array);
>
> - for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
> + for (prop = array; prop && prop->name; prop++) {
> cpu_add_multi_ext_prop(obj, prop);
> }
> }
> @@ -1620,11 +1622,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
> }
>
> static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
> - RISCVCPUMultiExtConfig *array)
> + const RISCVCPUMultiExtConfig *array)
> {
> + const RISCVCPUMultiExtConfig *prop;
> +
> g_assert(array);
>
> - for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
> + for (prop = array; prop && prop->name; prop++) {
> riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
> }
> }
> @@ -1687,7 +1691,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> CPURISCVState *env = &cpu->env;
> - RISCVCPUMultiExtConfig *prop;
> + const RISCVCPUMultiExtConfig *prop;
>
> /* Enable RVG, RVJ and RVV that are disabled by default */
> set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
2023-09-20 11:20 ` [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
@ 2023-09-22 5:55 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 5:55 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 10:47 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We'll introduce the KVM accelerator class with a 'cpu_instance_init'
> implementation that is going to be invoked during the common
> riscv_cpu_post_init() (via accel_cpu_instance_init()). This
> instance_init will execute KVM exclusive code that TCG doesn't care
> about, such as adding KVM specific properties, initing registers using a
> KVM scratch CPU and so on.
>
> The core of the forementioned cpu_instance_init impl is the current
> riscv_cpu_add_kvm_properties() that is being used by the common code via
> riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together
> will all the relevant artifacts, exporting and renaming it to
> kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now.
>
> To make this work we'll need to export riscv_cpu_extensions,
> riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as
> well. The TCG accelerator will also need to access those in the near
> future so this export will benefit us in the long run.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 85 +++-------------------------------------
> target/riscv/cpu.h | 14 +++++++
> target/riscv/kvm.c | 68 +++++++++++++++++++++++++++++++-
> target/riscv/kvm_riscv.h | 3 --
> 4 files changed, 86 insertions(+), 84 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 048a2dbc77..0dc9b3201d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1370,7 +1370,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> * change MISA bits during realize() (RVG enables MISA
> * bits but the user is warned about it).
> */
> -static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> +void riscv_cpu_add_misa_properties(Object *cpu_obj)
> {
> int i;
>
> @@ -1397,17 +1397,11 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> }
> }
>
> -typedef struct RISCVCPUMultiExtConfig {
> - const char *name;
> - uint32_t offset;
> - bool enabled;
> -} RISCVCPUMultiExtConfig;
> -
> #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
> .enabled = _defval}
>
> -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> /* Defaults for standard extensions */
> MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
> @@ -1469,7 +1463,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
> MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
> MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
> @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> };
>
> /* These are experimental so mark with 'x-' */
> -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> /* ePMP 0.9.3 */
> MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
> MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
> @@ -1513,7 +1507,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static Property riscv_cpu_options[] = {
> +Property riscv_cpu_options[] = {
> DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> @@ -1586,75 +1580,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
> }
> }
>
> -#ifdef CONFIG_KVM
> -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
> - const char *name,
> - void *opaque, Error **errp)
> -{
> - const char *propname = opaque;
> - bool value;
> -
> - if (!visit_type_bool(v, name, &value, errp)) {
> - return;
> - }
> -
> - if (value) {
> - error_setg(errp, "extension %s is not available with KVM",
> - propname);
> - }
> -}
> -
> -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
> -{
> - /* Check if KVM created the property already */
> - if (object_property_find(obj, prop_name)) {
> - return;
> - }
> -
> - /*
> - * Set the default to disabled for every extension
> - * unknown to KVM and error out if the user attempts
> - * to enable any of them.
> - */
> - object_property_add(obj, prop_name, "bool",
> - NULL, cpu_set_cfg_unavailable,
> - NULL, (void *)prop_name);
> -}
> -
> -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
> - const RISCVCPUMultiExtConfig *array)
> -{
> - const RISCVCPUMultiExtConfig *prop;
> -
> - g_assert(array);
> -
> - for (prop = array; prop && prop->name; prop++) {
> - riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
> - }
> -}
> -
> -void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> -{
> - Property *prop;
> - DeviceState *dev = DEVICE(obj);
> -
> - kvm_riscv_init_user_properties(obj);
> - riscv_cpu_add_misa_properties(obj);
> -
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
> -
> - for (prop = riscv_cpu_options; prop && prop->name; prop++) {
> - /* Check if KVM created the property already */
> - if (object_property_find(obj, prop->name)) {
> - continue;
> - }
> - qdev_property_add_static(dev, prop);
> - }
> -}
> -#endif
> -
> /*
> * Add CPU properties with user-facing flags.
> *
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b2e558f730..9dc4113812 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -22,6 +22,7 @@
>
> #include "hw/core/cpu.h"
> #include "hw/registerfields.h"
> +#include "hw/qdev-properties.h"
> #include "exec/cpu-defs.h"
> #include "qemu/cpu-float.h"
> #include "qom/object.h"
> @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
>
> +typedef struct RISCVCPUMultiExtConfig {
> + const char *name;
> + uint32_t offset;
> + bool enabled;
> +} RISCVCPUMultiExtConfig;
> +
> +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
> +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
> +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
> +extern Property riscv_cpu_options[];
> +
> +void riscv_cpu_add_misa_properties(Object *cpu_obj);
> +
> /* CSR function table */
> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 31d2ede4b6..e682a70311 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -345,6 +345,52 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
> }
> }
>
> +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
> + const char *name,
> + void *opaque, Error **errp)
> +{
> + const char *propname = opaque;
> + bool value;
> +
> + if (!visit_type_bool(v, name, &value, errp)) {
> + return;
> + }
> +
> + if (value) {
> + error_setg(errp, "extension %s is not available with KVM",
> + propname);
> + }
> +}
> +
> +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
> +{
> + /* Check if KVM created the property already */
> + if (object_property_find(obj, prop_name)) {
> + return;
> + }
> +
> + /*
> + * Set the default to disabled for every extension
> + * unknown to KVM and error out if the user attempts
> + * to enable any of them.
> + */
> + object_property_add(obj, prop_name, "bool",
> + NULL, cpu_set_cfg_unavailable,
> + NULL, (void *)prop_name);
> +}
> +
> +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
> + const RISCVCPUMultiExtConfig *array)
> +{
> + const RISCVCPUMultiExtConfig *prop;
> +
> + g_assert(array);
> +
> + for (prop = array; prop && prop->name; prop++) {
> + riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
> + }
> +}
> +
> static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
> @@ -754,7 +800,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
> }
>
> -void kvm_riscv_init_user_properties(Object *cpu_obj)
> +static void riscv_init_user_properties(Object *cpu_obj)
> {
> RISCVCPU *cpu = RISCV_CPU(cpu_obj);
> KVMScratchCPU kvmcpu;
> @@ -1272,6 +1318,26 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
> }
>
> +void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> +{
> + DeviceState *dev = DEVICE(obj);
> +
> + riscv_init_user_properties(obj);
> + riscv_cpu_add_misa_properties(obj);
> +
> + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
> + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
> +
> + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> + /* Check if KVM created the property already */
> + if (object_property_find(obj, prop->name)) {
> + continue;
> + }
> + qdev_property_add_static(dev, prop);
> + }
> +}
> +
> static void riscv_host_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index 44b850a046..da9630c4af 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -19,10 +19,7 @@
> #ifndef QEMU_KVM_RISCV_H
> #define QEMU_KVM_RISCV_H
>
> -/* Temporarily implemented in cpu.c */
> void kvm_riscv_cpu_add_kvm_properties(Object *obj);
> -
> -void kvm_riscv_init_user_properties(Object *cpu_obj);
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public
2023-09-20 11:20 ` [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
@ 2023-09-22 6:03 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 6:03 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This function is used for both accelerators. Make it public, and call it
> from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
> split KVM specific code for the KVM accelerator class in the next patch.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 5 ++---
> target/riscv/cpu.h | 1 +
> target/riscv/kvm.c | 1 +
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0dc9b3201d..50be127f36 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
> satp_map->init |= 1 << satp;
> }
>
> -static void riscv_add_satp_mode_properties(Object *obj)
> +void riscv_add_satp_mode_properties(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
> static void riscv_cpu_add_user_properties(Object *obj)
> {
> #ifndef CONFIG_USER_ONLY
> - riscv_add_satp_mode_properties(obj);
> -
> if (kvm_enabled()) {
> kvm_riscv_cpu_add_kvm_properties(obj);
> return;
> }
> + riscv_add_satp_mode_properties(obj);
> #endif
>
> riscv_cpu_add_misa_properties(obj);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9dc4113812..cb13464ba6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
> extern Property riscv_cpu_options[];
>
> void riscv_cpu_add_misa_properties(Object *cpu_obj);
> +void riscv_add_satp_mode_properties(Object *obj);
>
> /* CSR function table */
> extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index e682a70311..e5e957121f 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -1323,6 +1323,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> DeviceState *dev = DEVICE(obj);
>
> riscv_init_user_properties(obj);
> + riscv_add_satp_mode_properties(obj);
> riscv_cpu_add_misa_properties(obj);
>
> riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 10/19] target/riscv: remove kvm-stub.c
2023-09-20 11:20 ` [PATCH v3 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
@ 2023-09-22 6:06 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 6:06 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:22 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This file is not needed for some time now. Both kvm_riscv_reset_vcpu()
> and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are
> wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out
> in non-KVM builds.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/kvm-stub.c | 30 ------------------------------
> target/riscv/meson.build | 2 +-
> 2 files changed, 1 insertion(+), 31 deletions(-)
> delete mode 100644 target/riscv/kvm-stub.c
>
> diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
> deleted file mode 100644
> index 4e8fc31a21..0000000000
> --- a/target/riscv/kvm-stub.c
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -/*
> - * QEMU KVM RISC-V specific function stubs
> - *
> - * Copyright (c) 2020 Huawei Technologies Co., Ltd
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2 or later, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program. If not, see <http://www.gnu.org/licenses/>.
> - */
> -#include "qemu/osdep.h"
> -#include "cpu.h"
> -#include "kvm_riscv.h"
> -
> -void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> -{
> - abort();
> -}
> -
> -void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> -{
> - abort();
> -}
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index f0486183fa..3323b78b84 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -24,7 +24,7 @@ riscv_ss.add(files(
> 'zce_helper.c',
> 'vcrypto_helper.c'
> ))
> -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
> +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
>
> riscv_system_ss = ss.source_set()
> riscv_system_ss.add(files(
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass
2023-09-20 11:20 ` [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
@ 2023-09-22 6:08 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-22 6:08 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add a KVM accelerator class like we did with TCG. The difference is
> that, at least for now, we won't be using a realize() implementation for
> this accelerator.
>
> We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to
> kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change
> riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go
> through the 'cpu_instance_init' impl of the current acceleration (if
> available) and execute it. The end result is that the KVM initial setup,
> i.e. starting registers and adding its specific properties, will be done
> via this hook.
>
> Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid
> calling riscv_cpu_add_user_properties() when running KVM. We'll remove
> this condition when the TCG accel class get its own 'cpu_instance_init'
> implementation.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 8 +++-----
> target/riscv/kvm.c | 26 ++++++++++++++++++++++++--
> target/riscv/kvm_riscv.h | 1 -
> 3 files changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 50be127f36..c8a19be1af 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1219,7 +1219,9 @@ static bool riscv_cpu_has_user_properties(Object *cpu_obj)
>
> static void riscv_cpu_post_init(Object *obj)
> {
> - if (riscv_cpu_has_user_properties(obj)) {
> + accel_cpu_instance_init(CPU(obj));
> +
> + if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
> riscv_cpu_add_user_properties(obj);
> }
>
> @@ -1589,10 +1591,6 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj,
> static void riscv_cpu_add_user_properties(Object *obj)
> {
> #ifndef CONFIG_USER_ONLY
> - if (kvm_enabled()) {
> - kvm_riscv_cpu_add_kvm_properties(obj);
> - return;
> - }
> riscv_add_satp_mode_properties(obj);
> #endif
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index e5e957121f..606fdab223 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -31,6 +31,7 @@
> #include "sysemu/kvm_int.h"
> #include "cpu.h"
> #include "trace.h"
> +#include "hw/core/accel-cpu.h"
> #include "hw/pci/pci.h"
> #include "exec/memattrs.h"
> #include "exec/address-spaces.h"
> @@ -1318,8 +1319,9 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
> }
>
> -void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> +static void kvm_cpu_instance_init(CPUState *cs)
> {
> + Object *obj = OBJECT(RISCV_CPU(cs));
> DeviceState *dev = DEVICE(obj);
>
> riscv_init_user_properties(obj);
> @@ -1331,7 +1333,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
>
> for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> - /* Check if KVM created the property already */
> + /* Check if we have a specific KVM handler for the option */
> if (object_property_find(obj, prop->name)) {
> continue;
> }
> @@ -1339,6 +1341,26 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> }
> }
>
> +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
> +{
> + AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
> +
> + acc->cpu_instance_init = kvm_cpu_instance_init;
> +}
> +
> +static const TypeInfo kvm_cpu_accel_type_info = {
> + .name = ACCEL_CPU_NAME("kvm"),
> +
> + .parent = TYPE_ACCEL_CPU,
> + .class_init = kvm_cpu_accel_class_init,
> + .abstract = true,
> +};
> +static void kvm_cpu_accel_register_types(void)
> +{
> + type_register_static(&kvm_cpu_accel_type_info);
> +}
> +type_init(kvm_cpu_accel_register_types);
> +
> static void riscv_host_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index da9630c4af..8329cfab82 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -19,7 +19,6 @@
> #ifndef QEMU_KVM_RISCV_H
> #define QEMU_KVM_RISCV_H
>
> -void kvm_riscv_cpu_add_kvm_properties(Object *obj);
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c
2023-09-20 11:20 ` [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
@ 2023-09-22 10:55 ` Philippe Mathieu-Daudé
2023-09-25 2:00 ` Alistair Francis
1 sibling, 0 replies; 43+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-09-22 10:55 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liweiwei, zhiwei_liu,
palmer, ajones
On 20/9/23 13:20, Daniel Henrique Barboza wrote:
> Priv spec validation is TCG specific. Move it to the TCG accel class.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> target/riscv/cpu.c | 38 --------------------------------------
> target/riscv/cpu.h | 2 --
> target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 38 insertions(+), 40 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir
2023-09-20 11:20 ` [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
@ 2023-09-25 1:26 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 1:26 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Move the files to a 'kvm' dir to promote more code separation between
> accelerators and making our lives easier supporting build options such
> as --disable-tcg.
>
> Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/riscv_aplic.c | 2 +-
> hw/riscv/virt.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/riscv/{kvm.c => kvm/kvm-cpu.c} | 0
> target/riscv/{ => kvm}/kvm_riscv.h | 0
> target/riscv/kvm/meson.build | 1 +
> target/riscv/meson.build | 2 +-
> 7 files changed, 5 insertions(+), 4 deletions(-)
> rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (100%)
> rename target/riscv/{ => kvm}/kvm_riscv.h (100%)
> create mode 100644 target/riscv/kvm/meson.build
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index 99aae8ccbe..c677b5cfbb 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -32,7 +32,7 @@
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> #include "sysemu/kvm.h"
> -#include "kvm_riscv.h"
> +#include "kvm/kvm_riscv.h"
> #include "migration/vmstate.h"
>
> #define APLIC_MAX_IDC (1UL << 14)
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5edc1d98d2..9de578c756 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -35,7 +35,7 @@
> #include "hw/riscv/virt.h"
> #include "hw/riscv/boot.h"
> #include "hw/riscv/numa.h"
> -#include "kvm_riscv.h"
> +#include "kvm/kvm_riscv.h"
> #include "hw/intc/riscv_aclint.h"
> #include "hw/intc/riscv_aplic.h"
> #include "hw/intc/riscv_imsic.h"
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c8a19be1af..51567c2f12 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -33,7 +33,7 @@
> #include "fpu/softfloat-helpers.h"
> #include "sysemu/kvm.h"
> #include "sysemu/tcg.h"
> -#include "kvm_riscv.h"
> +#include "kvm/kvm_riscv.h"
> #include "tcg/tcg.h"
>
> /* RISC-V CPU definitions */
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c
> similarity index 100%
> rename from target/riscv/kvm.c
> rename to target/riscv/kvm/kvm-cpu.c
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h
> similarity index 100%
> rename from target/riscv/kvm_riscv.h
> rename to target/riscv/kvm/kvm_riscv.h
> diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
> new file mode 100644
> index 0000000000..7e92415091
> --- /dev/null
> +++ b/target/riscv/kvm/meson.build
> @@ -0,0 +1 @@
> +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 3323b78b84..c53962215f 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -24,7 +24,6 @@ riscv_ss.add(files(
> 'zce_helper.c',
> 'vcrypto_helper.c'
> ))
> -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
>
> riscv_system_ss = ss.source_set()
> riscv_system_ss.add(files(
> @@ -39,6 +38,7 @@ riscv_system_ss.add(files(
> ))
>
> subdir('tcg')
> +subdir('kvm')
>
> target_arch += {'riscv': riscv_ss}
> target_softmmu_arch += {'riscv': riscv_system_ss}
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
2023-09-20 11:20 ` [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
@ 2023-09-25 1:32 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 1:32 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> riscv_cpu_add_misa_properties() is being used to fill the missing KVM
> MISA properties but it is a TCG helper that was adapted to do so. We'll
> move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill
> the remaining MISA properties on its own.
>
> Do not use riscv_cpu_add_misa_properties(). Let's create a new array
> with all available MISA bits we support that can be read by KVM. The
> array is zero terminate to allow us to iterate through it without
> knowing its size.
>
> Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM
> MISA properties as usual and then use this array to add any missing MISA
> properties with the riscv_cpu_add_kvm_unavail_prop() helper.
>
> Note that we're creating misa_bits[], and not using the existing
> 'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa
> related functions and it doesn't have all MISA bits we support. Commit
> 0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the
> full context.
>
> While we're at it, move both satp and the multi-letter extension
> properties to kvm_riscv_add_cpu_user_properties() as well.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 3 ++-
> target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++--------
> 3 files changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 51567c2f12..665c21af6a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -38,6 +38,8 @@
>
> /* RISC-V CPU definitions */
> static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
> +const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
> + RVC, RVS, RVU, RVH, RVJ, RVG, 0};
>
> struct isa_ext_data {
> const char *name;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index cb13464ba6..7235eafc1a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -43,7 +43,7 @@
> #define RV(x) ((target_ulong)1 << (x - 'A'))
>
> /*
> - * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[]
> + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
> * when adding new MISA bits here.
> */
> #define RVI RV('I')
> @@ -60,6 +60,7 @@
> #define RVJ RV('J')
> #define RVG RV('G')
>
> +extern const uint32_t misa_bits[];
> const char *riscv_get_misa_ext_name(uint32_t bit);
> const char *riscv_get_misa_ext_description(uint32_t bit);
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 606fdab223..c6615cb807 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -396,6 +396,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
>
> + riscv_add_satp_mode_properties(cpu_obj);
> +
> for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) {
> KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i];
> int bit = misa_cfg->offset;
> @@ -411,6 +413,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> misa_cfg->description);
> }
>
> + for (i = 0; misa_bits[i] != 0; i++) {
> + const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]);
> + riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name);
> + }
> +
> for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
> KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i];
>
> @@ -427,6 +434,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> object_property_add(cpu_obj, "cboz_blocksize", "uint16",
> NULL, kvm_cpu_set_cbomz_blksize,
> NULL, &kvm_cboz_blocksize);
> +
> + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions);
> + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts);
> + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts);
> }
>
> static int kvm_riscv_get_regs_core(CPUState *cs)
> @@ -801,7 +812,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
> }
>
> -static void riscv_init_user_properties(Object *cpu_obj)
> +static void riscv_init_kvm_registers(Object *cpu_obj)
> {
> RISCVCPU *cpu = RISCV_CPU(cpu_obj);
> KVMScratchCPU kvmcpu;
> @@ -810,7 +821,6 @@ static void riscv_init_user_properties(Object *cpu_obj)
> return;
> }
>
> - kvm_riscv_add_cpu_user_properties(cpu_obj);
> kvm_riscv_init_machine_ids(cpu, &kvmcpu);
> kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
> kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
> @@ -1324,13 +1334,9 @@ static void kvm_cpu_instance_init(CPUState *cs)
> Object *obj = OBJECT(RISCV_CPU(cs));
> DeviceState *dev = DEVICE(obj);
>
> - riscv_init_user_properties(obj);
> - riscv_add_satp_mode_properties(obj);
> - riscv_cpu_add_misa_properties(obj);
> + riscv_init_kvm_registers(obj);
>
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
> - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
> + kvm_riscv_add_cpu_user_properties(obj);
>
> for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> /* Check if we have a specific KVM handler for the option */
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 14/19] target/riscv/cpu.c: export set_misa()
2023-09-20 11:20 ` [PATCH v3 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
@ 2023-09-25 1:36 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 1:36 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
> patch and set_misa() needs to be usable from there.
>
> Rename it to riscv_cpu_set_misa() and make it public.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 34 ++++++++++++++++++----------------
> target/riscv/cpu.h | 1 +
> 2 files changed, 19 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 665c21af6a..cf191d576e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
> }
> }
>
> -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> {
> env->misa_mxl_max = env->misa_mxl = mxl;
> env->misa_ext_mask = env->misa_ext = ext;
> @@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
> CPURISCVState *env = &cpu->env;
> #if defined(TARGET_RISCV32)
> - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #elif defined(TARGET_RISCV64)
> - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #endif
>
> #ifndef CONFIG_USER_ONLY
> @@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj)
> #ifdef TARGET_RISCV32
> mlx = MXL_RV32;
> #endif
> - set_misa(env, mlx, 0);
> + riscv_cpu_set_misa(env, mlx, 0);
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
> @@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, MXL_RV64, 0);
> + riscv_cpu_set_misa(env, MXL_RV64, 0);
> /* Set latest version of privileged specification */
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> @@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> CPURISCVState *env = &cpu->env;
> - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + riscv_cpu_set_misa(env, MXL_RV64,
> + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> @@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
> + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
> env->priv_ver = PRIV_VERSION_1_11_0;
>
> cpu->cfg.ext_zfa = true;
> @@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
> + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
> env->priv_ver = PRIV_VERSION_1_12_0;
>
> /* Enable ISA extensions */
> @@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj)
> }
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, MXL_RV128, 0);
> + riscv_cpu_set_misa(env, MXL_RV128, 0);
> /* Set latest version of privileged specification */
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> @@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, MXL_RV32, 0);
> + riscv_cpu_set_misa(env, MXL_RV32, 0);
> /* Set latest version of privileged specification */
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> @@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> CPURISCVState *env = &cpu->env;
> - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + riscv_cpu_set_misa(env, MXL_RV32,
> + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> @@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> env->priv_ver = PRIV_VERSION_1_11_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
> const RISCVCPUMultiExtConfig *prop;
>
> /* Enable RVG, RVJ and RVV that are disabled by default */
> - set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
> + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
>
> for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
> isa_ext_update_enabled(cpu, prop->offset, true);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7235eafc1a..9ec0805596 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
> void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
>
> typedef struct RISCVCPUMultiExtConfig {
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
2023-09-20 11:20 ` [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
@ 2023-09-25 1:37 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 1:37 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 10:46 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The array isn't marked as 'const' because we're initializing their
> elements in riscv_cpu_add_misa_properties(), 'name' and 'description'
> fields.
>
> In a closer look we can see that we're not using these 2 fields after
> creating the MISA properties. And we can create the properties by using
> riscv_get_misa_ext_name() and riscv_get_misa_ext_description()
> directly.
>
> Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig
> and make misa_ext_cfgs[] a const array.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 21 ++++++++-------------
> 1 file changed, 8 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8616c9e2f5..4875feded7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1212,8 +1212,6 @@ static void riscv_cpu_init(Object *obj)
> }
>
> typedef struct RISCVCPUMisaExtConfig {
> - const char *name;
> - const char *description;
> target_ulong misa_bit;
> bool enabled;
> } RISCVCPUMisaExtConfig;
> @@ -1317,7 +1315,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
> #define MISA_CFG(_bit, _enabled) \
> {.misa_bit = _bit, .enabled = _enabled}
>
> -static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> MISA_CFG(RVA, true),
> MISA_CFG(RVC, true),
> MISA_CFG(RVD, true),
> @@ -1344,25 +1342,22 @@ void riscv_cpu_add_misa_properties(Object *cpu_obj)
> int i;
>
> for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> - RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
> + const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
> int bit = misa_cfg->misa_bit;
> -
> - misa_cfg->name = riscv_get_misa_ext_name(bit);
> - misa_cfg->description = riscv_get_misa_ext_description(bit);
> + const char *name = riscv_get_misa_ext_name(bit);
> + const char *desc = riscv_get_misa_ext_description(bit);
>
> /* Check if KVM already created the property */
> - if (object_property_find(cpu_obj, misa_cfg->name)) {
> + if (object_property_find(cpu_obj, name)) {
> continue;
> }
>
> - object_property_add(cpu_obj, misa_cfg->name, "bool",
> + object_property_add(cpu_obj, name, "bool",
> cpu_get_misa_ext_cfg,
> cpu_set_misa_ext_cfg,
> NULL, (void *)misa_cfg);
> - object_property_set_description(cpu_obj, misa_cfg->name,
> - misa_cfg->description);
> - object_property_set_bool(cpu_obj, misa_cfg->name,
> - misa_cfg->enabled, NULL);
> + object_property_set_description(cpu_obj, name, desc);
> + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> }
> }
>
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init()
2023-09-20 11:20 ` [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
@ 2023-09-25 1:56 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 1:56 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG
> accelerator. It'll be called from within riscv_cpu_post_init(), via
> accel_cpu_instance_init(), similar to what happens with KVM. In fact, to
> preserve behavior, the implementation will be similar to what
> riscv_cpu_post_init() already does.
>
> In this patch we'll move riscv_cpu_add_user_properties() and
> riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c.
> All multi-extension properties code was moved. The 'multi_ext_user_opts'
> hash table was also moved to tcg-cpu.c since it's a TCG only structure,
> meaning that we won't have to worry about initializing a TCG hash table
> when running a KVM CPU anymore.
>
> riscv_cpu_add_user_properties() will remain in cpu.c for now due to how
> much code it requires to be moved at the same time. We'll do that in the
> next patch.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 150 -------------------------------------
> target/riscv/cpu.h | 1 -
> target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 149 insertions(+), 151 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cf191d576e..8616c9e2f5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
> };
>
> -/* Hash that stores user set extensions */
> -static GHashTable *multi_ext_user_opts;
> -
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> {
> bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
> @@ -194,12 +191,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> g_assert_not_reached();
> }
>
> -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> -{
> - return g_hash_table_contains(multi_ext_user_opts,
> - GUINT_TO_POINTER(ext_offset));
> -}
> -
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -280,9 +271,6 @@ static const char * const riscv_intr_names[] = {
> "reserved"
> };
>
> -static void riscv_cpu_add_user_properties(Object *obj);
> -static void riscv_init_max_cpu_extensions(Object *obj);
> -
> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
> {
> if (async) {
> @@ -1206,32 +1194,9 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
> return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
> }
>
> -static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
> -{
> - return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
> -}
> -
> -static bool riscv_cpu_has_user_properties(Object *cpu_obj)
> -{
> - if (kvm_enabled() &&
> - object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
> - return true;
> - }
> -
> - return riscv_cpu_is_dynamic(cpu_obj);
> -}
> -
> static void riscv_cpu_post_init(Object *obj)
> {
> accel_cpu_instance_init(CPU(obj));
> -
> - if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) {
> - riscv_cpu_add_user_properties(obj);
> - }
> -
> - if (riscv_cpu_has_max_extensions(obj)) {
> - riscv_init_max_cpu_extensions(obj);
> - }
> }
>
> static void riscv_cpu_init(Object *obj)
> @@ -1244,8 +1209,6 @@ static void riscv_cpu_init(Object *obj)
> qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> #endif /* CONFIG_USER_ONLY */
> -
> - multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> }
>
> typedef struct RISCVCPUMisaExtConfig {
> @@ -1531,119 +1494,6 @@ Property riscv_cpu_options[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
> - bool value;
> -
> - if (!visit_type_bool(v, name, &value, errp)) {
> - return;
> - }
> -
> - isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
> -
> - g_hash_table_insert(multi_ext_user_opts,
> - GUINT_TO_POINTER(multi_ext_cfg->offset),
> - (gpointer)value);
> -}
> -
> -static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
> - bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
> -
> - visit_type_bool(v, name, &value, errp);
> -}
> -
> -static void cpu_add_multi_ext_prop(Object *cpu_obj,
> - const RISCVCPUMultiExtConfig *multi_cfg)
> -{
> - object_property_add(cpu_obj, multi_cfg->name, "bool",
> - cpu_get_multi_ext_cfg,
> - cpu_set_multi_ext_cfg,
> - NULL, (void *)multi_cfg);
> -
> - /*
> - * Set def val directly instead of using
> - * object_property_set_bool() to save the set()
> - * callback hash for user inputs.
> - */
> - isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
> - multi_cfg->enabled);
> -}
> -
> -static void riscv_cpu_add_multiext_prop_array(Object *obj,
> - const RISCVCPUMultiExtConfig *array)
> -{
> - const RISCVCPUMultiExtConfig *prop;
> -
> - g_assert(array);
> -
> - for (prop = array; prop && prop->name; prop++) {
> - cpu_add_multi_ext_prop(obj, prop);
> - }
> -}
> -
> -/*
> - * Add CPU properties with user-facing flags.
> - *
> - * This will overwrite existing env->misa_ext values with the
> - * defaults set via riscv_cpu_add_misa_properties().
> - */
> -static void riscv_cpu_add_user_properties(Object *obj)
> -{
> -#ifndef CONFIG_USER_ONLY
> - riscv_add_satp_mode_properties(obj);
> -#endif
> -
> - riscv_cpu_add_misa_properties(obj);
> -
> - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
> - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
> - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
> -
> - for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> - qdev_property_add_static(DEVICE(obj), prop);
> - }
> -}
> -
> -/*
> - * The 'max' type CPU will have all possible ratified
> - * non-vendor extensions enabled.
> - */
> -static void riscv_init_max_cpu_extensions(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - const RISCVCPUMultiExtConfig *prop;
> -
> - /* Enable RVG, RVJ and RVV that are disabled by default */
> - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
> -
> - for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
> - isa_ext_update_enabled(cpu, prop->offset, true);
> - }
> -
> - /* set vector version */
> - env->vext_ver = VEXT_VERSION_1_00_0;
> -
> - /* Zfinx is not compatible with F. Disable it */
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
> -
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
> -
> - if (env->misa_mxl != MXL_RV32) {
> - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
> - }
> -}
> -
> static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9ec0805596..01cbcbe119 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -710,7 +710,6 @@ enum riscv_pmu_event_idx {
>
> /* used by tcg/tcg-cpu.c*/
> void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index e480b9f726..5d71ff2cce 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -24,6 +24,7 @@
> #include "pmu.h"
> #include "time_helper.h"
> #include "qapi/error.h"
> +#include "qapi/visitor.h"
> #include "qemu/accel.h"
> #include "qemu/error-report.h"
> #include "qemu/log.h"
> @@ -31,6 +32,15 @@
> #include "hw/core/tcg-cpu-ops.h"
> #include "tcg/tcg.h"
>
> +/* Hash that stores user set extensions */
> +static GHashTable *multi_ext_user_opts;
> +
> +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> +{
> + return g_hash_table_contains(multi_ext_user_opts,
> + GUINT_TO_POINTER(ext_offset));
> +}
> +
> static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> @@ -570,6 +580,144 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
> return true;
> }
>
> +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
> + bool value;
> +
> + if (!visit_type_bool(v, name, &value, errp)) {
> + return;
> + }
> +
> + isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
> +
> + g_hash_table_insert(multi_ext_user_opts,
> + GUINT_TO_POINTER(multi_ext_cfg->offset),
> + (gpointer)value);
> +}
> +
> +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
> + bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
> +
> + visit_type_bool(v, name, &value, errp);
> +}
> +
> +static void cpu_add_multi_ext_prop(Object *cpu_obj,
> + const RISCVCPUMultiExtConfig *multi_cfg)
> +{
> + object_property_add(cpu_obj, multi_cfg->name, "bool",
> + cpu_get_multi_ext_cfg,
> + cpu_set_multi_ext_cfg,
> + NULL, (void *)multi_cfg);
> +
> + /*
> + * Set def val directly instead of using
> + * object_property_set_bool() to save the set()
> + * callback hash for user inputs.
> + */
> + isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
> + multi_cfg->enabled);
> +}
> +
> +static void riscv_cpu_add_multiext_prop_array(Object *obj,
> + const RISCVCPUMultiExtConfig *array)
> +{
> + const RISCVCPUMultiExtConfig *prop;
> +
> + g_assert(array);
> +
> + for (prop = array; prop && prop->name; prop++) {
> + cpu_add_multi_ext_prop(obj, prop);
> + }
> +}
> +
> +/*
> + * Add CPU properties with user-facing flags.
> + *
> + * This will overwrite existing env->misa_ext values with the
> + * defaults set via riscv_cpu_add_misa_properties().
> + */
> +static void riscv_cpu_add_user_properties(Object *obj)
> +{
> +#ifndef CONFIG_USER_ONLY
> + riscv_add_satp_mode_properties(obj);
> +#endif
> +
> + riscv_cpu_add_misa_properties(obj);
> +
> + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
> + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
> + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
> +
> + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> + qdev_property_add_static(DEVICE(obj), prop);
> + }
> +}
> +
> +/*
> + * The 'max' type CPU will have all possible ratified
> + * non-vendor extensions enabled.
> + */
> +static void riscv_init_max_cpu_extensions(Object *obj)
> +{
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + CPURISCVState *env = &cpu->env;
> + const RISCVCPUMultiExtConfig *prop;
> +
> + /* Enable RVG, RVJ and RVV that are disabled by default */
> + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
> +
> + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
> + isa_ext_update_enabled(cpu, prop->offset, true);
> + }
> +
> + /* set vector version */
> + env->vext_ver = VEXT_VERSION_1_00_0;
> +
> + /* Zfinx is not compatible with F. Disable it */
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
> +
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
> +
> + if (env->misa_mxl != MXL_RV32) {
> + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
> + }
> +}
> +
> +static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
> +{
> + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
> +}
> +
> +static bool riscv_cpu_has_user_properties(Object *cpu_obj)
> +{
> + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
> +}
> +
> +static void tcg_cpu_instance_init(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + Object *obj = OBJECT(cpu);
> +
> + if (riscv_cpu_has_user_properties(obj)) {
> + multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> + riscv_cpu_add_user_properties(obj);
> + }
> +
> + if (riscv_cpu_has_max_extensions(obj)) {
> + riscv_init_max_cpu_extensions(obj);
> + }
> +}
> +
> static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
> {
> /*
> @@ -588,6 +736,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
> AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
>
> acc->cpu_class_init = tcg_cpu_class_init;
> + acc->cpu_instance_init = tcg_cpu_instance_init;
> acc->cpu_realizefn = tcg_cpu_realizefn;
> }
>
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
2023-09-20 11:20 ` [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
@ 2023-09-25 1:57 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 1:57 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 10:58 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> All code related to MISA TCG properties is also moved.
>
> At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
> properties handling is done in kvm-cpu.c.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 90 --------------------------------------
> target/riscv/cpu.h | 1 -
> target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 90 insertions(+), 91 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4875feded7..46263e55d5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj)
> #endif /* CONFIG_USER_ONLY */
> }
>
> -typedef struct RISCVCPUMisaExtConfig {
> - target_ulong misa_bit;
> - bool enabled;
> -} RISCVCPUMisaExtConfig;
> -
> -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> - target_ulong misa_bit = misa_ext_cfg->misa_bit;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - bool value;
> -
> - if (!visit_type_bool(v, name, &value, errp)) {
> - return;
> - }
> -
> - if (value) {
> - env->misa_ext |= misa_bit;
> - env->misa_ext_mask |= misa_bit;
> - } else {
> - env->misa_ext &= ~misa_bit;
> - env->misa_ext_mask &= ~misa_bit;
> - }
> -}
> -
> -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> - target_ulong misa_bit = misa_ext_cfg->misa_bit;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - bool value;
> -
> - value = env->misa_ext & misa_bit;
> -
> - visit_type_bool(v, name, &value, errp);
> -}
> -
> typedef struct misa_ext_info {
> const char *name;
> const char *description;
> @@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
> return val;
> }
>
> -#define MISA_CFG(_bit, _enabled) \
> - {.misa_bit = _bit, .enabled = _enabled}
> -
> -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> - MISA_CFG(RVA, true),
> - MISA_CFG(RVC, true),
> - MISA_CFG(RVD, true),
> - MISA_CFG(RVF, true),
> - MISA_CFG(RVI, true),
> - MISA_CFG(RVE, false),
> - MISA_CFG(RVM, true),
> - MISA_CFG(RVS, true),
> - MISA_CFG(RVU, true),
> - MISA_CFG(RVH, true),
> - MISA_CFG(RVJ, false),
> - MISA_CFG(RVV, false),
> - MISA_CFG(RVG, false),
> -};
> -
> -/*
> - * We do not support user choice tracking for MISA
> - * extensions yet because, so far, we do not silently
> - * change MISA bits during realize() (RVG enables MISA
> - * bits but the user is warned about it).
> - */
> -void riscv_cpu_add_misa_properties(Object *cpu_obj)
> -{
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> - const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
> - int bit = misa_cfg->misa_bit;
> - const char *name = riscv_get_misa_ext_name(bit);
> - const char *desc = riscv_get_misa_ext_description(bit);
> -
> - /* Check if KVM already created the property */
> - if (object_property_find(cpu_obj, name)) {
> - continue;
> - }
> -
> - object_property_add(cpu_obj, name, "bool",
> - cpu_get_misa_ext_cfg,
> - cpu_set_misa_ext_cfg,
> - NULL, (void *)misa_cfg);
> - object_property_set_description(cpu_obj, name, desc);
> - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> - }
> -}
> -
> #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
> .enabled = _defval}
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 01cbcbe119..aba8192c74 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
> extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
> extern Property riscv_cpu_options[];
>
> -void riscv_cpu_add_misa_properties(Object *cpu_obj);
> void riscv_add_satp_mode_properties(Object *obj);
>
> /* CSR function table */
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 5d71ff2cce..c326ab37a2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -580,6 +580,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
> return true;
> }
>
> +typedef struct RISCVCPUMisaExtConfig {
> + target_ulong misa_bit;
> + bool enabled;
> +} RISCVCPUMisaExtConfig;
> +
> +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> + target_ulong misa_bit = misa_ext_cfg->misa_bit;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + CPURISCVState *env = &cpu->env;
> + bool value;
> +
> + if (!visit_type_bool(v, name, &value, errp)) {
> + return;
> + }
> +
> + if (value) {
> + env->misa_ext |= misa_bit;
> + env->misa_ext_mask |= misa_bit;
> + } else {
> + env->misa_ext &= ~misa_bit;
> + env->misa_ext_mask &= ~misa_bit;
> + }
> +}
> +
> +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> + target_ulong misa_bit = misa_ext_cfg->misa_bit;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + CPURISCVState *env = &cpu->env;
> + bool value;
> +
> + value = env->misa_ext & misa_bit;
> +
> + visit_type_bool(v, name, &value, errp);
> +}
> +
> +#define MISA_CFG(_bit, _enabled) \
> + {.misa_bit = _bit, .enabled = _enabled}
> +
> +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> + MISA_CFG(RVA, true),
> + MISA_CFG(RVC, true),
> + MISA_CFG(RVD, true),
> + MISA_CFG(RVF, true),
> + MISA_CFG(RVI, true),
> + MISA_CFG(RVE, false),
> + MISA_CFG(RVM, true),
> + MISA_CFG(RVS, true),
> + MISA_CFG(RVU, true),
> + MISA_CFG(RVH, true),
> + MISA_CFG(RVJ, false),
> + MISA_CFG(RVV, false),
> + MISA_CFG(RVG, false),
> +};
> +
> +/*
> + * We do not support user choice tracking for MISA
> + * extensions yet because, so far, we do not silently
> + * change MISA bits during realize() (RVG enables MISA
> + * bits but the user is warned about it).
> + */
> +static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> + const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
> + int bit = misa_cfg->misa_bit;
> + const char *name = riscv_get_misa_ext_name(bit);
> + const char *desc = riscv_get_misa_ext_description(bit);
> +
> + /* Check if KVM already created the property */
> + if (object_property_find(cpu_obj, name)) {
> + continue;
> + }
> +
> + object_property_add(cpu_obj, name, "bool",
> + cpu_get_misa_ext_cfg,
> + cpu_set_misa_ext_cfg,
> + NULL, (void *)misa_cfg);
> + object_property_set_description(cpu_obj, name, desc);
> + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> + }
> +}
> +
> static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> void *opaque, Error **errp)
> {
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[]
2023-09-20 11:20 ` [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
@ 2023-09-25 2:00 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 2:00 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This array will be read by the TCG accel class, allowing it to handle
> priv spec verifications on its own. The array will remain here in cpu.c
> because it's also used by the riscv,isa string function.
>
> To export it we'll finish it with an empty element since ARRAY_SIZE()
> won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
> alleviate the changes for the next patch.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
> target/riscv/cpu.h | 7 +++++++
> 2 files changed, 28 insertions(+), 26 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 46263e55d5..e97ba3df93 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
> const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
> RVC, RVS, RVU, RVH, RVJ, RVG, 0};
>
> -struct isa_ext_data {
> - const char *name;
> - int min_version;
> - int ext_enable_offset;
> -};
> -
> -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
> -
> /*
> * From vector_helper.c
> * Note that vector data is stored in host-endian 64-bit chunks,
> @@ -61,6 +52,9 @@ struct isa_ext_data {
> #define BYTE(x) (x)
> #endif
>
> +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
> +
> /*
> * Here are the ordering rules of extension naming defined by RISC-V
> * specification :
> @@ -81,7 +75,7 @@ struct isa_ext_data {
> * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
> * instead.
> */
> -static const struct isa_ext_data isa_edata_arr[] = {
> +const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
> ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
> ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
> @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
> ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
> ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
> +
> + DEFINE_PROP_END_OF_LIST(),
> };
>
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
>
> int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> {
> - int i;
> + const RISCVIsaExtData *edata;
>
> - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> - if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
> + for (edata = isa_edata_arr; edata && edata->name; edata++) {
> + if (edata->ext_enable_offset != ext_offset) {
> continue;
> }
>
> - return isa_edata_arr[i].min_version;
> + return edata->min_version;
> }
>
> g_assert_not_reached();
> @@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> {
> CPURISCVState *env = &cpu->env;
> - int i;
> + const RISCVIsaExtData *edata;
>
> /* Force disable extensions if priv spec version does not match */
> - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
> - (env->priv_ver < isa_edata_arr[i].min_version)) {
> - isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
> - false);
> + for (edata = isa_edata_arr; edata && edata->name; edata++) {
> + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
> + (env->priv_ver < edata->min_version)) {
> + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
> #ifndef CONFIG_USER_ONLY
> warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> " because privilege spec version does not match",
> - isa_edata_arr[i].name, env->mhartid);
> + edata->name, env->mhartid);
> #else
> warn_report("disabling %s extension because "
> "privilege spec version does not match",
> - isa_edata_arr[i].name);
> + edata->name);
> #endif
> }
> }
> @@ -1619,13 +1614,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
> int max_str_len)
> {
> + const RISCVIsaExtData *edata;
> char *old = *isa_str;
> char *new = *isa_str;
> - int i;
>
> - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
> - new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> + for (edata = isa_edata_arr; edata && edata->name; edata++) {
> + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
> + new = g_strconcat(old, "_", edata->name, NULL);
> g_free(old);
> old = new;
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index aba8192c74..3dfcd0732f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
> extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
> extern Property riscv_cpu_options[];
>
> +typedef struct isa_ext_data {
> + const char *name;
> + int min_version;
> + int ext_enable_offset;
> +} RISCVIsaExtData;
> +extern const RISCVIsaExtData isa_edata_arr[];
> +
> void riscv_add_satp_mode_properties(Object *obj);
>
> /* CSR function table */
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c
2023-09-20 11:20 ` [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
2023-09-22 10:55 ` Philippe Mathieu-Daudé
@ 2023-09-25 2:00 ` Alistair Francis
1 sibling, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 2:00 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Priv spec validation is TCG specific. Move it to the TCG accel class.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 38 --------------------------------------
> target/riscv/cpu.h | 2 --
> target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 38 insertions(+), 40 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e97ba3df93..eeeb08a35a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
> *ext_enabled = en;
> }
>
> -int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> -{
> - const RISCVIsaExtData *edata;
> -
> - for (edata = isa_edata_arr; edata && edata->name; edata++) {
> - if (edata->ext_enable_offset != ext_offset) {
> - continue;
> - }
> -
> - return edata->min_version;
> - }
> -
> - g_assert_not_reached();
> -}
> -
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> }
> }
>
> -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> -{
> - CPURISCVState *env = &cpu->env;
> - const RISCVIsaExtData *edata;
> -
> - /* Force disable extensions if priv spec version does not match */
> - for (edata = isa_edata_arr; edata && edata->name; edata++) {
> - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
> - (env->priv_ver < edata->min_version)) {
> - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
> -#ifndef CONFIG_USER_ONLY
> - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> - " because privilege spec version does not match",
> - edata->name, env->mhartid);
> -#else
> - warn_report("disabling %s extension because "
> - "privilege spec version does not match",
> - edata->name);
> -#endif
> - }
> - }
> -}
> -
> #ifndef CONFIG_USER_ONLY
> static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
> {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3dfcd0732f..219fe2e9b5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx {
> /* used by tcg/tcg-cpu.c*/
> void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> -int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
> -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
>
> typedef struct RISCVCPUMultiExtConfig {
> const char *name;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c326ab37a2..8c052d6fcd 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -99,6 +99,21 @@ static const struct TCGCPUOps riscv_tcg_ops = {
> #endif /* !CONFIG_USER_ONLY */
> };
>
> +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> +{
> + const RISCVIsaExtData *edata;
> +
> + for (edata = isa_edata_arr; edata && edata->name; edata++) {
> + if (edata->ext_enable_offset != ext_offset) {
> + continue;
> + }
> +
> + return edata->min_version;
> + }
> +
> + g_assert_not_reached();
> +}
> +
> static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> bool value)
> {
> @@ -226,6 +241,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> }
> }
>
> +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> +{
> + CPURISCVState *env = &cpu->env;
> + const RISCVIsaExtData *edata;
> +
> + /* Force disable extensions if priv spec version does not match */
> + for (edata = isa_edata_arr; edata && edata->name; edata++) {
> + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
> + (env->priv_ver < edata->min_version)) {
> + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
> +#ifndef CONFIG_USER_ONLY
> + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> + " because privilege spec version does not match",
> + edata->name, env->mhartid);
> +#else
> + warn_report("disabling %s extension because "
> + "privilege spec version does not match",
> + edata->name);
> +#endif
> + }
> + }
> +}
> +
> /*
> * Check consistency between chosen extensions while setting
> * cpu->cfg accordingly.
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
` (18 preceding siblings ...)
2023-09-20 11:20 ` [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
@ 2023-09-25 3:30 ` Alistair Francis
19 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 3:30 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Wed, Sep 20, 2023 at 9:26 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> In this version we changed patch 10 (remove kvm-stub.c) as suggested by
> Phil to not include non-KVM stubs in kvm_riscv.h. A change in patch 05
> requested by Zhiwei was also made.
>
> Patches based on Alistair's riscv-to-apply.next.
>
> Patches missing acks: patch 10
>
> Changes from v2:
> - patch 05:
> - remove riscv_cpu_add_user_properties() from riscv_host_cpu_init()
> - patch 10:
> - do not add non-KVM stubs in kvm_riscv.h
> - v2 link: https://lore.kernel.org/qemu-riscv/20230906091647.1667171-1-dbarboza@ventanamicro.com/
>
> Daniel Henrique Barboza (19):
> target/riscv: introduce TCG AccelCPUClass
> target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
> target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
> target/riscv: move riscv_tcg_ops to tcg-cpu.c
> target/riscv/cpu.c: add .instance_post_init()
> target/riscv: move 'host' CPU declaration to kvm.c
> target/riscv/cpu.c: mark extensions arrays as 'const'
> target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
> target/riscv: make riscv_add_satp_mode_properties() public
> target/riscv: remove kvm-stub.c
> target/riscv: introduce KVM AccelCPUClass
> target/riscv: move KVM only files to kvm subdir
> target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
> target/riscv/cpu.c: export set_misa()
> target/riscv/tcg: introduce tcg_cpu_instance_init()
> target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
> target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
> target/riscv/cpu.c: export isa_edata_arr[]
> target/riscv/cpu: move priv spec functions to tcg-cpu.c
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/intc/riscv_aplic.c | 2 +-
> hw/riscv/virt.c | 2 +-
> target/riscv/cpu.c | 988 ++------------------------
> target/riscv/cpu.h | 30 +-
> target/riscv/csr.c | 1 +
> target/riscv/kvm-stub.c | 30 -
> target/riscv/{kvm.c => kvm/kvm-cpu.c} | 120 +++-
> target/riscv/{ => kvm}/kvm_riscv.h | 4 -
> target/riscv/kvm/meson.build | 1 +
> target/riscv/meson.build | 4 +-
> target/riscv/tcg/meson.build | 2 +
> target/riscv/tcg/tcg-cpu.c | 883 +++++++++++++++++++++++
> target/riscv/tcg/tcg-cpu.h | 27 +
> 13 files changed, 1113 insertions(+), 981 deletions(-)
> delete mode 100644 target/riscv/kvm-stub.c
> rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (91%)
> rename target/riscv/{ => kvm}/kvm_riscv.h (89%)
> create mode 100644 target/riscv/kvm/meson.build
> create mode 100644 target/riscv/tcg/meson.build
> create mode 100644 target/riscv/tcg/tcg-cpu.c
> create mode 100644 target/riscv/tcg/tcg-cpu.h
>
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
2023-09-22 5:29 ` Alistair Francis
@ 2023-09-25 9:17 ` Daniel Henrique Barboza
2023-09-25 10:33 ` Alistair Francis
0 siblings, 1 reply; 43+ messages in thread
From: Daniel Henrique Barboza @ 2023-09-25 9:17 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On 9/22/23 02:29, Alistair Francis wrote:
> On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
>> realize() path during the common riscv_cpu_realize(), making it a good
>> choice to start moving TCG exclusive code to tcg-cpu.c.
>>
>> Rename it to tcg_cpu_realizefn() and assign it as a implementation of
>> accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
>> riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
>> approach with KVM in the near future.
>>
>> riscv_cpu_validate_set_extensions() is too big and with too many
>> dependencies to be moved in this same patch. We'll do that next.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>> ---
>> target/riscv/cpu.c | 128 -----------------------------------
>> target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
>> 2 files changed, 133 insertions(+), 128 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index e72c49c881..030629294f 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -23,9 +23,7 @@
>> #include "qemu/log.h"
>> #include "cpu.h"
>> #include "cpu_vendorid.h"
>> -#include "pmu.h"
>> #include "internals.h"
>> -#include "time_helper.h"
>> #include "exec/exec-all.h"
>> #include "qapi/error.h"
>> #include "qapi/visitor.h"
>> @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
>> }
>> }
>>
>> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
>> -{
>> - CPURISCVState *env = &cpu->env;
>> - int priv_version = -1;
>> -
>> - if (cpu->cfg.priv_spec) {
>> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
>> - priv_version = PRIV_VERSION_1_12_0;
>> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
>> - priv_version = PRIV_VERSION_1_11_0;
>> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
>> - priv_version = PRIV_VERSION_1_10_0;
>> - } else {
>> - error_setg(errp,
>> - "Unsupported privilege spec version '%s'",
>> - cpu->cfg.priv_spec);
>> - return;
>> - }
>> -
>> - env->priv_ver = priv_version;
>> - }
>> -}
>> -
>> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>> {
>> CPURISCVState *env = &cpu->env;
>> @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>> }
>> }
>>
>> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
>> -{
>> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
>> - CPUClass *cc = CPU_CLASS(mcc);
>> - CPURISCVState *env = &cpu->env;
>> -
>> - /* Validate that MISA_MXL is set properly. */
>> - switch (env->misa_mxl_max) {
>> -#ifdef TARGET_RISCV64
>> - case MXL_RV64:
>> - case MXL_RV128:
>> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
>> - break;
>> -#endif
>> - case MXL_RV32:
>> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
>> - break;
>> - default:
>> - g_assert_not_reached();
>> - }
>> -
>> - if (env->misa_mxl_max != env->misa_mxl) {
>> - error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
>> - return;
>> - }
>> -}
>> -
>> /*
>> * Check consistency between chosen extensions while setting
>> * cpu->cfg accordingly.
>> @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
>> #endif
>> }
>>
>> -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
>> -{
>> - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
>> - error_setg(errp, "H extension requires priv spec 1.12.0");
>> - return;
>> - }
>> -}
>> -
>> -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
>> -{
>> - RISCVCPU *cpu = RISCV_CPU(dev);
>> - CPURISCVState *env = &cpu->env;
>> - Error *local_err = NULL;
>> -
>> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
>> - error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
>> - return;
>> - }
>> -
>> - riscv_cpu_validate_misa_mxl(cpu, &local_err);
>> - if (local_err != NULL) {
>> - error_propagate(errp, local_err);
>> - return;
>> - }
>> -
>> - riscv_cpu_validate_priv_spec(cpu, &local_err);
>> - if (local_err != NULL) {
>> - error_propagate(errp, local_err);
>> - return;
>> - }
>> -
>> - riscv_cpu_validate_misa_priv(env, &local_err);
>> - if (local_err != NULL) {
>> - error_propagate(errp, local_err);
>> - return;
>> - }
>> -
>> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>> - /*
>> - * Enhanced PMP should only be available
>> - * on harts with PMP support
>> - */
>> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
>> - return;
>> - }
>> -
>> - riscv_cpu_validate_set_extensions(cpu, &local_err);
>> - if (local_err != NULL) {
>> - error_propagate(errp, local_err);
>> - return;
>> - }
>> -
>> -#ifndef CONFIG_USER_ONLY
>> - CPU(dev)->tcg_cflags |= CF_PCREL;
>> -
>> - if (cpu->cfg.ext_sstc) {
>> - riscv_timer_init(cpu);
>> - }
>> -
>> - if (cpu->cfg.pmu_num) {
>> - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
>> - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
>> - riscv_pmu_timer_cb, cpu);
>> - }
>> - }
>> -#endif
>> -}
>> -
>> static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> {
>> CPUState *cs = CPU(dev);
>> @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> return;
>> }
>>
>> - if (tcg_enabled()) {
>> - riscv_cpu_realize_tcg(dev, &local_err);
>> - if (local_err != NULL) {
>> - error_propagate(errp, local_err);
>> - return;
>> - }
>> - }
>> -
>> riscv_cpu_finalize_features(cpu, &local_err);
>> if (local_err != NULL) {
>> error_propagate(errp, local_err);
>> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
>> index 0326cead0d..f47dc2064f 100644
>> --- a/target/riscv/tcg/tcg-cpu.c
>> +++ b/target/riscv/tcg/tcg-cpu.c
>> @@ -18,10 +18,142 @@
>> */
>
> I do think we should keep the Copyright statements from cpu.c in this
> new file as you are now copying across the majority of code from there
I don't mind keeping the copyright statements from cpu.c here. Feel free to change it
in tree (or let me know if you want me to re-send).
Thanks,
Daniel
>
> Alistair
>
>>
>> #include "qemu/osdep.h"
>> +#include "exec/exec-all.h"
>> #include "cpu.h"
>> +#include "pmu.h"
>> +#include "time_helper.h"
>> +#include "qapi/error.h"
>> #include "qemu/accel.h"
>> #include "hw/core/accel-cpu.h"
>>
>> +
>> +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
>> +{
>> + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
>> + error_setg(errp, "H extension requires priv spec 1.12.0");
>> + return;
>> + }
>> +}
>> +
>> +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
>> +{
>> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
>> + CPUClass *cc = CPU_CLASS(mcc);
>> + CPURISCVState *env = &cpu->env;
>> +
>> + /* Validate that MISA_MXL is set properly. */
>> + switch (env->misa_mxl_max) {
>> +#ifdef TARGET_RISCV64
>> + case MXL_RV64:
>> + case MXL_RV128:
>> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
>> + break;
>> +#endif
>> + case MXL_RV32:
>> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
>> + break;
>> + default:
>> + g_assert_not_reached();
>> + }
>> +
>> + if (env->misa_mxl_max != env->misa_mxl) {
>> + error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
>> + return;
>> + }
>> +}
>> +
>> +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
>> +{
>> + CPURISCVState *env = &cpu->env;
>> + int priv_version = -1;
>> +
>> + if (cpu->cfg.priv_spec) {
>> + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
>> + priv_version = PRIV_VERSION_1_12_0;
>> + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
>> + priv_version = PRIV_VERSION_1_11_0;
>> + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
>> + priv_version = PRIV_VERSION_1_10_0;
>> + } else {
>> + error_setg(errp,
>> + "Unsupported privilege spec version '%s'",
>> + cpu->cfg.priv_spec);
>> + return;
>> + }
>> +
>> + env->priv_ver = priv_version;
>> + }
>> +}
>> +
>> +/*
>> + * We'll get here via the following path:
>> + *
>> + * riscv_cpu_realize()
>> + * -> cpu_exec_realizefn()
>> + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn())
>> + */
>> +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
>> +{
>> + RISCVCPU *cpu = RISCV_CPU(cs);
>> + CPURISCVState *env = &cpu->env;
>> + Error *local_err = NULL;
>> +
>> + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
>> + error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
>> + return false;
>> + }
>> +
>> + riscv_cpu_validate_misa_mxl(cpu, &local_err);
>> + if (local_err != NULL) {
>> + error_propagate(errp, local_err);
>> + return false;
>> + }
>> +
>> + riscv_cpu_validate_priv_spec(cpu, &local_err);
>> + if (local_err != NULL) {
>> + error_propagate(errp, local_err);
>> + return false;
>> + }
>> +
>> + riscv_cpu_validate_misa_priv(env, &local_err);
>> + if (local_err != NULL) {
>> + error_propagate(errp, local_err);
>> + return false;
>> + }
>> +
>> + if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>> + /*
>> + * Enhanced PMP should only be available
>> + * on harts with PMP support
>> + */
>> + error_setg(errp, "Invalid configuration: EPMP requires PMP support");
>> + return false;
>> + }
>> +
>> + riscv_cpu_validate_set_extensions(cpu, &local_err);
>> + if (local_err != NULL) {
>> + error_propagate(errp, local_err);
>> + return false;
>> + }
>> +
>> +#ifndef CONFIG_USER_ONLY
>> + CPU(cs)->tcg_cflags |= CF_PCREL;
>> +
>> + if (cpu->cfg.ext_sstc) {
>> + riscv_timer_init(cpu);
>> + }
>> +
>> + if (cpu->cfg.pmu_num) {
>> + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
>> + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
>> + riscv_pmu_timer_cb, cpu);
>> + }
>> + }
>> +#endif
>> +
>> + return true;
>> +}
>> +
>> static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
>> {
>> /*
>> @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
>> AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
>>
>> acc->cpu_class_init = tcg_cpu_class_init;
>> + acc->cpu_realizefn = tcg_cpu_realizefn;
>> }
>>
>> static const TypeInfo tcg_cpu_accel_type_info = {
>> --
>> 2.41.0
>>
>>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
2023-09-25 9:17 ` Daniel Henrique Barboza
@ 2023-09-25 10:33 ` Alistair Francis
0 siblings, 0 replies; 43+ messages in thread
From: Alistair Francis @ 2023-09-25 10:33 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liweiwei,
zhiwei_liu, palmer, philmd, ajones
On Mon, Sep 25, 2023 at 7:17 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 9/22/23 02:29, Alistair Francis wrote:
> > On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
> > <dbarboza@ventanamicro.com> wrote:
> >>
> >> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different
> >> realize() path during the common riscv_cpu_realize(), making it a good
> >> choice to start moving TCG exclusive code to tcg-cpu.c.
> >>
> >> Rename it to tcg_cpu_realizefn() and assign it as a implementation of
> >> accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during
> >> riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar
> >> approach with KVM in the near future.
> >>
> >> riscv_cpu_validate_set_extensions() is too big and with too many
> >> dependencies to be moved in this same patch. We'll do that next.
> >>
> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> >> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> >> ---
> >> target/riscv/cpu.c | 128 -----------------------------------
> >> target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++
> >> 2 files changed, 133 insertions(+), 128 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index e72c49c881..030629294f 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -23,9 +23,7 @@
> >> #include "qemu/log.h"
> >> #include "cpu.h"
> >> #include "cpu_vendorid.h"
> >> -#include "pmu.h"
> >> #include "internals.h"
> >> -#include "time_helper.h"
> >> #include "exec/exec-all.h"
> >> #include "qapi/error.h"
> >> #include "qapi/visitor.h"
> >> @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> >> }
> >> }
> >>
> >> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
> >> -{
> >> - CPURISCVState *env = &cpu->env;
> >> - int priv_version = -1;
> >> -
> >> - if (cpu->cfg.priv_spec) {
> >> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> >> - priv_version = PRIV_VERSION_1_12_0;
> >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> >> - priv_version = PRIV_VERSION_1_11_0;
> >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> >> - priv_version = PRIV_VERSION_1_10_0;
> >> - } else {
> >> - error_setg(errp,
> >> - "Unsupported privilege spec version '%s'",
> >> - cpu->cfg.priv_spec);
> >> - return;
> >> - }
> >> -
> >> - env->priv_ver = priv_version;
> >> - }
> >> -}
> >> -
> >> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> >> {
> >> CPURISCVState *env = &cpu->env;
> >> @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> >> }
> >> }
> >>
> >> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> >> -{
> >> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> >> - CPUClass *cc = CPU_CLASS(mcc);
> >> - CPURISCVState *env = &cpu->env;
> >> -
> >> - /* Validate that MISA_MXL is set properly. */
> >> - switch (env->misa_mxl_max) {
> >> -#ifdef TARGET_RISCV64
> >> - case MXL_RV64:
> >> - case MXL_RV128:
> >> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> >> - break;
> >> -#endif
> >> - case MXL_RV32:
> >> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> >> - break;
> >> - default:
> >> - g_assert_not_reached();
> >> - }
> >> -
> >> - if (env->misa_mxl_max != env->misa_mxl) {
> >> - error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
> >> - return;
> >> - }
> >> -}
> >> -
> >> /*
> >> * Check consistency between chosen extensions while setting
> >> * cpu->cfg accordingly.
> >> @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> >> #endif
> >> }
> >>
> >> -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> >> -{
> >> - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
> >> - error_setg(errp, "H extension requires priv spec 1.12.0");
> >> - return;
> >> - }
> >> -}
> >> -
> >> -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
> >> -{
> >> - RISCVCPU *cpu = RISCV_CPU(dev);
> >> - CPURISCVState *env = &cpu->env;
> >> - Error *local_err = NULL;
> >> -
> >> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) {
> >> - error_setg(errp, "'host' CPU is not compatible with TCG acceleration");
> >> - return;
> >> - }
> >> -
> >> - riscv_cpu_validate_misa_mxl(cpu, &local_err);
> >> - if (local_err != NULL) {
> >> - error_propagate(errp, local_err);
> >> - return;
> >> - }
> >> -
> >> - riscv_cpu_validate_priv_spec(cpu, &local_err);
> >> - if (local_err != NULL) {
> >> - error_propagate(errp, local_err);
> >> - return;
> >> - }
> >> -
> >> - riscv_cpu_validate_misa_priv(env, &local_err);
> >> - if (local_err != NULL) {
> >> - error_propagate(errp, local_err);
> >> - return;
> >> - }
> >> -
> >> - if (cpu->cfg.epmp && !cpu->cfg.pmp) {
> >> - /*
> >> - * Enhanced PMP should only be available
> >> - * on harts with PMP support
> >> - */
> >> - error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> >> - return;
> >> - }
> >> -
> >> - riscv_cpu_validate_set_extensions(cpu, &local_err);
> >> - if (local_err != NULL) {
> >> - error_propagate(errp, local_err);
> >> - return;
> >> - }
> >> -
> >> -#ifndef CONFIG_USER_ONLY
> >> - CPU(dev)->tcg_cflags |= CF_PCREL;
> >> -
> >> - if (cpu->cfg.ext_sstc) {
> >> - riscv_timer_init(cpu);
> >> - }
> >> -
> >> - if (cpu->cfg.pmu_num) {
> >> - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
> >> - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> >> - riscv_pmu_timer_cb, cpu);
> >> - }
> >> - }
> >> -#endif
> >> -}
> >> -
> >> static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> {
> >> CPUState *cs = CPU(dev);
> >> @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> return;
> >> }
> >>
> >> - if (tcg_enabled()) {
> >> - riscv_cpu_realize_tcg(dev, &local_err);
> >> - if (local_err != NULL) {
> >> - error_propagate(errp, local_err);
> >> - return;
> >> - }
> >> - }
> >> -
> >> riscv_cpu_finalize_features(cpu, &local_err);
> >> if (local_err != NULL) {
> >> error_propagate(errp, local_err);
> >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> >> index 0326cead0d..f47dc2064f 100644
> >> --- a/target/riscv/tcg/tcg-cpu.c
> >> +++ b/target/riscv/tcg/tcg-cpu.c
> >> @@ -18,10 +18,142 @@
> >> */
> >
> > I do think we should keep the Copyright statements from cpu.c in this
> > new file as you are now copying across the majority of code from there
>
> I don't mind keeping the copyright statements from cpu.c here. Feel free to change it
> in tree (or let me know if you want me to re-send).
Whoops. I missed this comment. Do you mind sending a v4 then I will apply that
Alistair
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2023-09-25 10:33 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-20 11:20 [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-20 11:20 ` [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-09-22 5:24 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-09-22 5:29 ` Alistair Francis
2023-09-25 9:17 ` Daniel Henrique Barboza
2023-09-25 10:33 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-09-22 5:32 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
2023-09-22 5:34 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-09-22 5:51 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-09-22 5:53 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
2023-09-22 5:54 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-09-22 5:55 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
2023-09-22 6:03 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
2023-09-22 6:06 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-09-22 6:08 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-09-25 1:26 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-09-25 1:32 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
2023-09-25 1:36 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-09-25 1:56 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
2023-09-25 1:37 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-09-25 1:57 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-09-25 2:00 ` Alistair Francis
2023-09-20 11:20 ` [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
2023-09-22 10:55 ` Philippe Mathieu-Daudé
2023-09-25 2:00 ` Alistair Francis
2023-09-25 3:30 ` [PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c Alistair Francis
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