From: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Fabien Portas <fabien.portas@grenoble-inp.org>
Subject: Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions
Date: Tue, 31 Aug 2021 18:00:54 +0200 [thread overview]
Message-ID: <2c8e43c4-6edb-947f-95f6-49d08fa23005@univ-grenoble-alpes.fr> (raw)
In-Reply-To: <d494ea6e-4eed-7d74-b9f7-130201a8294f@linaro.org>
Hello Richard,
Le 31/08/2021 à 04:24, Richard Henderson a écrit :
> On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
>> +#if defined(TARGET_RISCV128)
>> +/*
>> + * Accessing signed 64-bit or 128-bit values should be part of MemOp in
>> + * include/exec/memop.h
>> + * Unfortunately, this requires to change the defines there, as MO_SIGN is 4,
>> + * and values 0 to 3 are usual types sizes.
>> + * Note that an assert is triggered when MemOp is MO_SIGN|MO_TEQ, this value
>> + * being some kind of sentinel.
>
> https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
Thanks for the pointer,
Frédéric
>
>
>
> r~
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
next prev parent reply other threads:[~2021-08-31 16:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-30 17:16 [PATCH 1/8] target/riscv: Settings for 128-bit extension support Frédéric Pétrot
2021-08-30 17:16 ` [PATCH 2/8] target/riscv: 128-bit registers creation and access Frédéric Pétrot
2021-08-30 21:34 ` Philippe Mathieu-Daudé
2021-08-30 17:16 ` [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions Frédéric Pétrot
2021-08-30 21:35 ` Philippe Mathieu-Daudé
2021-08-31 2:24 ` Richard Henderson
2021-08-31 16:00 ` Frédéric Pétrot [this message]
2021-08-31 2:30 ` Richard Henderson
2021-08-30 17:16 ` [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions Frédéric Pétrot
2021-08-30 21:38 ` Philippe Mathieu-Daudé
2021-08-30 21:40 ` Philippe Mathieu-Daudé
2021-08-31 15:57 ` Frédéric Pétrot
2021-08-31 3:32 ` Richard Henderson
2021-08-31 3:30 ` Richard Henderson
2021-08-30 17:16 ` [PATCH 5/8] target/riscv: 128-bit multiply and divide Frédéric Pétrot
2021-08-30 17:16 ` [PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types Frédéric Pétrot
2021-08-31 3:38 ` Richard Henderson
2021-08-30 17:16 ` [PATCH 7/8] target/riscv: 128-bit support for some csrs Frédéric Pétrot
2021-08-31 3:43 ` Richard Henderson
2021-08-30 17:16 ` [PATCH 8/8] target/riscv: Support for 128-bit satp Frédéric Pétrot
2021-08-31 3:13 ` [PATCH 1/8] target/riscv: Settings for 128-bit extension support Alistair Francis
2021-08-31 16:20 ` Frédéric Pétrot
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