* [PATCH v3 0/5] target/arm: Use tcg_constant_*
@ 2021-10-29 23:18 Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 1/5] target/arm: Use tcg_constant_i32() in op_smlad() Philippe Mathieu-Daudé
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Richard Henderson, Philippe Mathieu-Daudé
Missing review: patches #2 & #5 (new)
Introduce store_cpu_field_constant() helper to avoid using temporary
when the value is constant (and read-only).
Since v2:
- Simplify store_cpu_field_constant(), do not modify store_cpu_field()
- Added another use in gen_rev16()
Philippe Mathieu-Daudé (5):
target/arm: Use tcg_constant_i32() in op_smlad()
target/arm: Introduce store_cpu_field_constant() helper
target/arm: Use the constant variant of store_cpu_field() when
possible
target/arm: Use tcg_constant_i64() in do_sat_addsub_64()
target/arm: Use tcg_constant_i32() in gen_rev16()
target/arm/translate-a32.h | 3 +++
target/arm/translate-sve.c | 17 ++++++++---------
target/arm/translate.c | 27 ++++++++-------------------
3 files changed, 19 insertions(+), 28 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/5] target/arm: Use tcg_constant_i32() in op_smlad()
2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
@ 2021-10-29 23:18 ` Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 2/5] target/arm: Introduce store_cpu_field_constant() helper Philippe Mathieu-Daudé
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Richard Henderson, Philippe Mathieu-Daudé
Avoid using a TCG temporary for a read-only constant.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d6af5b1b039..083a6d6ed77 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7849,10 +7849,9 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
t3 = tcg_temp_new_i32();
tcg_gen_sari_i32(t3, t1, 31);
qf = load_cpu_field(QF);
- one = tcg_const_i32(1);
+ one = tcg_constant_i32(1);
tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf);
store_cpu_field(qf, QF);
- tcg_temp_free_i32(one);
tcg_temp_free_i32(t3);
tcg_temp_free_i32(t2);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/5] target/arm: Introduce store_cpu_field_constant() helper
2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 1/5] target/arm: Use tcg_constant_i32() in op_smlad() Philippe Mathieu-Daudé
@ 2021-10-29 23:18 ` Philippe Mathieu-Daudé
2021-10-30 23:45 ` Richard Henderson
2021-10-29 23:18 ` [PATCH v3 3/5] target/arm: Use the constant variant of store_cpu_field() when possible Philippe Mathieu-Daudé
` (3 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Richard Henderson, Philippe Mathieu-Daudé
Similarly to the store_cpu_field() helper which takes a TCG
temporary, store its value to the CPUState, introduce the
store_cpu_field_constant() helper which store a constant to
CPUState (without using any TCG temporary).
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate-a32.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 88f15df60e8..17af8dc95a8 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -70,6 +70,9 @@ static inline void store_cpu_offset(TCGv_i32 var, int offset)
#define store_cpu_field(var, name) \
store_cpu_offset(var, offsetof(CPUARMState, name))
+#define store_cpu_field_constant(val, name) \
+ tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, offsetof(CPUARMState, name))
+
/* Create a new temporary and set it to the value of a CPU register. */
static inline TCGv_i32 load_reg(DisasContext *s, int reg)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/5] target/arm: Use the constant variant of store_cpu_field() when possible
2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 1/5] target/arm: Use tcg_constant_i32() in op_smlad() Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 2/5] target/arm: Introduce store_cpu_field_constant() helper Philippe Mathieu-Daudé
@ 2021-10-29 23:18 ` Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 4/5] target/arm: Use tcg_constant_i64() in do_sat_addsub_64() Philippe Mathieu-Daudé
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Richard Henderson, Philippe Mathieu-Daudé
When using a constant variable, we can replace the store_cpu_field()
call by store_cpu_field_constant() which avoid using TCG temporaries.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate.c | 21 ++++++---------------
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 083a6d6ed77..52ba562c96b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -364,8 +364,7 @@ void clear_eci_state(DisasContext *s)
* multiple insn executes.
*/
if (s->eci) {
- TCGv_i32 tmp = tcg_const_i32(0);
- store_cpu_field(tmp, condexec_bits);
+ store_cpu_field_constant(0, condexec_bits);
s->eci = 0;
}
}
@@ -740,9 +739,8 @@ void gen_set_condexec(DisasContext *s)
{
if (s->condexec_mask) {
uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
- store_cpu_field(tmp, condexec_bits);
+
+ store_cpu_field_constant(val, condexec_bits);
}
}
@@ -8362,8 +8360,6 @@ static bool trans_BL(DisasContext *s, arg_i *a)
static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{
- TCGv_i32 tmp;
-
/*
* BLX <imm> would be useless on M-profile; the encoding space
* is used for other insns from v8.1M onward, and UNDEFs before that.
@@ -8377,8 +8373,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return false;
}
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
- tmp = tcg_const_i32(!s->thumb);
- store_cpu_field(tmp, thumb);
+ store_cpu_field_constant(!s->thumb, thumb);
gen_jmp(s, (read_pc(s) & ~3) + a->imm);
return true;
}
@@ -8677,7 +8672,6 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
* doesn't cache branch information, all we need to do is reset
* FPSCR.LTPSIZE to 4.
*/
- TCGv_i32 ltpsize;
if (!dc_isar_feature(aa32_lob, s) ||
!dc_isar_feature(aa32_mve, s)) {
@@ -8688,8 +8682,7 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
return true;
}
- ltpsize = tcg_const_i32(4);
- store_cpu_field(ltpsize, v7m.ltpsize);
+ store_cpu_field_constant(4, v7m.ltpsize);
return true;
}
@@ -9487,9 +9480,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
/* Reset the conditional execution bits immediately. This avoids
complications trying to do it at the end of the block. */
if (dc->condexec_mask || dc->condexec_cond) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- store_cpu_field(tmp, condexec_bits);
+ store_cpu_field_constant(0, condexec_bits);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 4/5] target/arm: Use tcg_constant_i64() in do_sat_addsub_64()
2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-10-29 23:18 ` [PATCH v3 3/5] target/arm: Use the constant variant of store_cpu_field() when possible Philippe Mathieu-Daudé
@ 2021-10-29 23:18 ` Philippe Mathieu-Daudé
2021-10-29 23:18 ` [PATCH v3 5/5] target/arm: Use tcg_constant_i32() in gen_rev16() Philippe Mathieu-Daudé
2021-11-01 17:41 ` [PATCH v3 0/5] target/arm: Use tcg_constant_* Richard Henderson
5 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Richard Henderson, Philippe Mathieu-Daudé
The immediate value used for comparison is constant and
read-only. Move it to the constant pool. This frees a
TCG temporary for unsigned saturation opcodes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate-sve.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index bc91a641711..76b5fe9f313 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1943,20 +1943,20 @@ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
{
TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2;
if (u) {
if (d) {
tcg_gen_sub_i64(t0, reg, val);
- tcg_gen_movi_i64(t1, 0);
- tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t1, t0);
+ t2 = tcg_constant_i64(0);
+ tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t2, t0);
} else {
tcg_gen_add_i64(t0, reg, val);
- tcg_gen_movi_i64(t1, -1);
- tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t1, t0);
+ t2 = tcg_constant_i64(-1);
+ tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t2, t0);
}
} else {
+ TCGv_i64 t1 = tcg_temp_new_i64();
if (d) {
/* Detect signed overflow for subtraction. */
tcg_gen_xor_i64(t0, reg, val);
@@ -1966,7 +1966,7 @@ static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
/* Bound the result. */
tcg_gen_movi_i64(reg, INT64_MIN);
- t2 = tcg_const_i64(0);
+ t2 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1);
} else {
/* Detect signed overflow for addition. */
@@ -1977,13 +1977,12 @@ static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
/* Bound the result. */
tcg_gen_movi_i64(t1, INT64_MAX);
- t2 = tcg_const_i64(0);
+ t2 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg);
}
- tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
}
tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
}
/* Similarly with a vector and a scalar operand. */
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 5/5] target/arm: Use tcg_constant_i32() in gen_rev16()
2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-10-29 23:18 ` [PATCH v3 4/5] target/arm: Use tcg_constant_i64() in do_sat_addsub_64() Philippe Mathieu-Daudé
@ 2021-10-29 23:18 ` Philippe Mathieu-Daudé
2021-10-30 23:46 ` Richard Henderson
2021-11-01 17:41 ` [PATCH v3 0/5] target/arm: Use tcg_constant_* Richard Henderson
5 siblings, 1 reply; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:18 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Richard Henderson, Philippe Mathieu-Daudé
Since the mask is a constant value, use tcg_constant_i32()
instead of a TCG temporary.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 52ba562c96b..98f59259284 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -388,13 +388,12 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
{
TCGv_i32 tmp = tcg_temp_new_i32();
- TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
+ TCGv_i32 mask = tcg_constant_i32(0x00ff00ff);
tcg_gen_shri_i32(tmp, var, 8);
tcg_gen_and_i32(tmp, tmp, mask);
tcg_gen_and_i32(var, var, mask);
tcg_gen_shli_i32(var, var, 8);
tcg_gen_or_i32(dest, var, tmp);
- tcg_temp_free_i32(mask);
tcg_temp_free_i32(tmp);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/5] target/arm: Introduce store_cpu_field_constant() helper
2021-10-29 23:18 ` [PATCH v3 2/5] target/arm: Introduce store_cpu_field_constant() helper Philippe Mathieu-Daudé
@ 2021-10-30 23:45 ` Richard Henderson
0 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2021-10-30 23:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Peter Maydell, qemu-arm
On 10/29/21 4:18 PM, Philippe Mathieu-Daudé wrote:
> Similarly to the store_cpu_field() helper which takes a TCG
> temporary, store its value to the CPUState, introduce the
> store_cpu_field_constant() helper which store a constant to
> CPUState (without using any TCG temporary).
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/arm/translate-a32.h | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 5/5] target/arm: Use tcg_constant_i32() in gen_rev16()
2021-10-29 23:18 ` [PATCH v3 5/5] target/arm: Use tcg_constant_i32() in gen_rev16() Philippe Mathieu-Daudé
@ 2021-10-30 23:46 ` Richard Henderson
0 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2021-10-30 23:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Peter Maydell, qemu-arm
On 10/29/21 4:18 PM, Philippe Mathieu-Daudé wrote:
> Since the mask is a constant value, use tcg_constant_i32()
> instead of a TCG temporary.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/arm/translate.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/5] target/arm: Use tcg_constant_*
2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-10-29 23:18 ` [PATCH v3 5/5] target/arm: Use tcg_constant_i32() in gen_rev16() Philippe Mathieu-Daudé
@ 2021-11-01 17:41 ` Richard Henderson
5 siblings, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2021-11-01 17:41 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Peter Maydell, qemu-arm
On 10/29/21 7:18 PM, Philippe Mathieu-Daudé wrote:
> Missing review: patches #2 & #5 (new)
>
> Introduce store_cpu_field_constant() helper to avoid using temporary
> when the value is constant (and read-only).
>
> Since v2:
> - Simplify store_cpu_field_constant(), do not modify store_cpu_field()
> - Added another use in gen_rev16()
>
> Philippe Mathieu-Daudé (5):
> target/arm: Use tcg_constant_i32() in op_smlad()
> target/arm: Introduce store_cpu_field_constant() helper
> target/arm: Use the constant variant of store_cpu_field() when
> possible
> target/arm: Use tcg_constant_i64() in do_sat_addsub_64()
> target/arm: Use tcg_constant_i32() in gen_rev16()
>
> target/arm/translate-a32.h | 3 +++
> target/arm/translate-sve.c | 17 ++++++++---------
> target/arm/translate.c | 27 ++++++++-------------------
> 3 files changed, 19 insertions(+), 28 deletions(-)
Thanks, applied to target-arm.next.
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-11-01 19:38 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
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2021-10-29 23:18 [PATCH v3 0/5] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
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2021-10-29 23:18 ` [PATCH v3 2/5] target/arm: Introduce store_cpu_field_constant() helper Philippe Mathieu-Daudé
2021-10-30 23:45 ` Richard Henderson
2021-10-29 23:18 ` [PATCH v3 3/5] target/arm: Use the constant variant of store_cpu_field() when possible Philippe Mathieu-Daudé
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