From: Shashi Mallela <shashi.mallela@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Leif Lindholm <leif@nuviainc.com>,
QEMU Developers <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>,
Radoslaw Biernacki <rad@semihalf.com>
Subject: Re: [PATCH v2 1/8] hw/intc: GICv3 ITS initial framework
Date: Fri, 30 Apr 2021 11:56:00 -0400 [thread overview]
Message-ID: <4B93C023-32E5-468F-80A8-DF58C8CD442F@getmailspring.com> (raw)
In-Reply-To: <CAFEAcA8EXUu8nfqz2Xn_Rke4Nk+cvdOuZOoFSfGkN6FFeTJ=yQ@mail.gmail.com>
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Have taken care of it.please ignore PIDR2 changes in the current patchset ,will update the latest changes in the next patchset version
Thanks
Shashi
On Apr 30 2021, at 6:09 am, Peter Maydell <peter.maydell@linaro.org> wrote:
> On Fri, 30 Apr 2021 at 00:36, <shashi.mallela@linaro.org> wrote:
> >
> > On Fri, 2021-04-16 at 18:21 +0100, Peter Maydell wrote:
> > > On Thu, 1 Apr 2021 at 03:41, Shashi Mallela <
> > > shashi.mallela@linaro.org> wrote:
> > > > +#define GITS_PIDR2 0xFFE8
> > >
> > > You probably don't want an offset for GITS_PIDR2 specifically.
> > > Compare handling of GICD_IDREGS in the distributor emulation.
> > > Tried re-using the GICD_IDREGS offset for GITS_PIDR2,but from testing
> > > observed that the linux kernel driver and kvm-unit-tests both relied
> > > on using the 0xFFE8 offset instead of 0xFFD0 (used by GICD & GICR) to
> > > complete ITS initialization and setup
>
> I didn't mean "just put PIDR2 at the GICD_IDREGS offset", which
> obviously won't work, I meant "implement the whole set of ID registers
> (of which PIDR2 is one in the middle) in the same way we implement that
> set on the other GIC components".
>
> -- PMM
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next prev parent reply other threads:[~2021-04-30 15:57 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 2:41 [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-04-01 2:41 ` [PATCH v2 1/8] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-04-16 17:21 ` Peter Maydell
2021-04-29 23:36 ` shashi.mallela
2021-04-30 10:09 ` Peter Maydell
2021-04-30 15:56 ` Shashi Mallela [this message]
2021-04-01 2:41 ` [PATCH v2 2/8] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-04-16 18:54 ` Peter Maydell
[not found] ` <937a2923445e3ff629c9799a8579c470d2636375.camel@linaro.org>
2021-04-29 23:37 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 3/8] hw/intc: GICv3 ITS command queue framework Shashi Mallela
2021-04-19 10:30 ` Peter Maydell
2021-04-29 23:38 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 4/8] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-04-19 10:39 ` Peter Maydell
2021-04-01 2:41 ` [PATCH v2 5/8] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-04-19 10:51 ` Peter Maydell
2021-04-29 23:39 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 6/8] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-04-19 12:44 ` Peter Maydell
[not found] ` <89852279ad379f2e50563dd47eb67376262355c0.camel@linaro.org>
2021-04-29 23:40 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
2021-04-19 12:44 ` Peter Maydell
2021-04-01 2:41 ` [PATCH v2 8/8] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-04-19 12:46 ` Peter Maydell
2021-04-29 23:40 ` shashi.mallela
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