* [PATCH v2 1/4] hw/sparc: Allow building without the leon3 machine
2021-04-28 14:16 [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Philippe Mathieu-Daudé
@ 2021-04-28 14:16 ` Philippe Mathieu-Daudé
2021-04-28 14:16 ` [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header Philippe Mathieu-Daudé
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-28 14:16 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Mark Cave-Ayland, Richard Henderson,
Philippe Mathieu-Daudé,
Fabien Chouteau, KONRAD Frederic, Artyom Tarasenko
When building without the leon3 machine, we get this link failure:
/usr/bin/ld: target_sparc_int32_helper.c.o: in function `leon3_irq_manager':
target/sparc/int32_helper.c:172: undefined reference to `leon3_irq_ack'
This is because the leon3_irq_ack() is declared in hw/sparc/leon3.c,
which is only build when CONFIG_LEON3 is selected.
Fix by moving the leon3_cache_control_int() / leon3_irq_manager()
(which are specific to the leon3 machine) to hw/sparc/leon3.c.
Move the trace events along (but don't rename them).
leon3_irq_ack() is now locally used, declare it static to reduce
its scope.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/sparc/cpu.h | 6 ------
hw/sparc/leon3.c | 37 ++++++++++++++++++++++++++++++++++++-
target/sparc/int32_helper.c | 37 -------------------------------------
hw/sparc/trace-events | 2 ++
target/sparc/trace-events | 4 ----
5 files changed, 38 insertions(+), 48 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..ff8ae73002a 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
-/* int_helper.c */
-void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
-
/* sun4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
-/* leon3.c */
-void leon3_irq_ack(void *irq_manager, int intno);
-
#if defined (TARGET_SPARC64)
static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 7e16eea9e67..98e3789cf84 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -137,7 +137,36 @@ static void main_cpu_reset(void *opaque)
env->regbase[6] = s->sp;
}
-void leon3_irq_ack(void *irq_manager, int intno)
+static void leon3_cache_control_int(CPUSPARCState *env)
+{
+ uint32_t state = 0;
+
+ if (env->cache_control & CACHE_CTRL_IF) {
+ /* Instruction cache state */
+ state = env->cache_control & CACHE_STATE_MASK;
+ if (state == CACHE_ENABLED) {
+ state = CACHE_FROZEN;
+ trace_int_helper_icache_freeze();
+ }
+
+ env->cache_control &= ~CACHE_STATE_MASK;
+ env->cache_control |= state;
+ }
+
+ if (env->cache_control & CACHE_CTRL_DF) {
+ /* Data cache state */
+ state = (env->cache_control >> 2) & CACHE_STATE_MASK;
+ if (state == CACHE_ENABLED) {
+ state = CACHE_FROZEN;
+ trace_int_helper_dcache_freeze();
+ }
+
+ env->cache_control &= ~(CACHE_STATE_MASK << 2);
+ env->cache_control |= (state << 2);
+ }
+}
+
+static void leon3_irq_ack(void *irq_manager, int intno)
{
grlib_irqmp_ack((DeviceState *)irq_manager, intno);
}
@@ -181,6 +210,12 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
}
}
+static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
+{
+ leon3_irq_ack(irq_manager, intno);
+ leon3_cache_control_int(env);
+}
+
static void leon3_generic_hw_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index 817a463a179..d008dbdb65c 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -136,40 +136,3 @@ void sparc_cpu_do_interrupt(CPUState *cs)
}
#endif
}
-
-#if !defined(CONFIG_USER_ONLY)
-static void leon3_cache_control_int(CPUSPARCState *env)
-{
- uint32_t state = 0;
-
- if (env->cache_control & CACHE_CTRL_IF) {
- /* Instruction cache state */
- state = env->cache_control & CACHE_STATE_MASK;
- if (state == CACHE_ENABLED) {
- state = CACHE_FROZEN;
- trace_int_helper_icache_freeze();
- }
-
- env->cache_control &= ~CACHE_STATE_MASK;
- env->cache_control |= state;
- }
-
- if (env->cache_control & CACHE_CTRL_DF) {
- /* Data cache state */
- state = (env->cache_control >> 2) & CACHE_STATE_MASK;
- if (state == CACHE_ENABLED) {
- state = CACHE_FROZEN;
- trace_int_helper_dcache_freeze();
- }
-
- env->cache_control &= ~(CACHE_STATE_MASK << 2);
- env->cache_control |= (state << 2);
- }
-}
-
-void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
-{
- leon3_irq_ack(irq_manager, intno);
- leon3_cache_control_int(env);
-}
-#endif
diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events
index 355b07ae057..dfb53dc1a24 100644
--- a/hw/sparc/trace-events
+++ b/hw/sparc/trace-events
@@ -19,3 +19,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64
# leon3.c
leon3_set_irq(int intno) "Set CPU IRQ %d"
leon3_reset_irq(int intno) "Reset CPU IRQ %d"
+int_helper_icache_freeze(void) "Instruction cache: freeze"
+int_helper_dcache_freeze(void) "Data cache: freeze"
diff --git a/target/sparc/trace-events b/target/sparc/trace-events
index 6a064e23275..e925ddd1cc0 100644
--- a/target/sparc/trace-events
+++ b/target/sparc/trace-events
@@ -15,10 +15,6 @@ int_helper_set_softint(uint32_t softint) "new 0x%08x"
int_helper_clear_softint(uint32_t softint) "new 0x%08x"
int_helper_write_softint(uint32_t softint) "new 0x%08x"
-# int32_helper.c
-int_helper_icache_freeze(void) "Instruction cache: freeze"
-int_helper_dcache_freeze(void) "Data cache: freeze"
-
# win_helper.c
win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=0x%x new=0x%x"
--
2.26.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header
2021-04-28 14:16 [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Philippe Mathieu-Daudé
2021-04-28 14:16 ` [PATCH v2 1/4] hw/sparc: Allow building without " Philippe Mathieu-Daudé
@ 2021-04-28 14:16 ` Philippe Mathieu-Daudé
2021-04-28 14:34 ` Fred Konrad
2021-04-28 14:49 ` Richard Henderson
2021-04-28 14:16 ` [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
` (3 subsequent siblings)
5 siblings, 2 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-28 14:16 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Mark Cave-Ayland, Richard Henderson,
Philippe Mathieu-Daudé,
Fabien Chouteau, KONRAD Frederic, Artyom Tarasenko
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sparc64/sparc64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index e3f9219a101..cc0b9bd30d3 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -26,7 +26,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/boards.h"
-#include "hw/char/serial.h"
#include "hw/sparc/sparc64.h"
#include "qemu/timer.h"
#include "sysemu/reset.h"
--
2.26.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header
2021-04-28 14:16 ` [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header Philippe Mathieu-Daudé
@ 2021-04-28 14:34 ` Fred Konrad
2021-04-28 14:49 ` Richard Henderson
1 sibling, 0 replies; 12+ messages in thread
From: Fred Konrad @ 2021-04-28 14:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Mark Cave-Ayland, Richard Henderson,
Fabien Chouteau, KONRAD Frederic, Artyom Tarasenko
Le 4/28/21 à 4:16 PM, Philippe Mathieu-Daudé a écrit :
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> hw/sparc64/sparc64.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index e3f9219a101..cc0b9bd30d3 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -26,7 +26,6 @@
> #include "qemu/osdep.h"
> #include "cpu.h"
> #include "hw/boards.h"
> -#include "hw/char/serial.h"
> #include "hw/sparc/sparc64.h"
> #include "qemu/timer.h"
> #include "sysemu/reset.h"
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header
2021-04-28 14:16 ` [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header Philippe Mathieu-Daudé
2021-04-28 14:34 ` Fred Konrad
@ 2021-04-28 14:49 ` Richard Henderson
1 sibling, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2021-04-28 14:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: KONRAD Frederic, Mark Cave-Ayland, Thomas Huth, Fabien Chouteau,
Artyom Tarasenko
On 4/28/21 7:16 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> hw/sparc64/sparc64.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl
2021-04-28 14:16 [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Philippe Mathieu-Daudé
2021-04-28 14:16 ` [PATCH v2 1/4] hw/sparc: Allow building without " Philippe Mathieu-Daudé
2021-04-28 14:16 ` [PATCH v2 2/4] hw/sparc64: Remove unused "hw/char/serial.h" header Philippe Mathieu-Daudé
@ 2021-04-28 14:16 ` Philippe Mathieu-Daudé
2021-04-28 14:35 ` Fred Konrad
2021-04-28 14:49 ` Richard Henderson
2021-04-28 14:16 ` [PATCH v2 4/4] hw/sparc*: Move cpu_check_irqs() to target/sparc/ Philippe Mathieu-Daudé
` (2 subsequent siblings)
5 siblings, 2 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-28 14:16 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Mark Cave-Ayland, Richard Henderson,
Philippe Mathieu-Daudé,
Fabien Chouteau, KONRAD Frederic, Artyom Tarasenko
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sparc64/sparc64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index cc0b9bd30d3..fd29a79edc0 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env)
return;
}
cs = env_cpu(env);
- /* check if TM or SM in SOFTINT are set
- setting these also causes interrupt 14 */
+ /*
+ * check if TM or SM in SOFTINT are set
+ * setting these also causes interrupt 14
+ */
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
pil |= 1 << 14;
}
- /* The bit corresponding to psrpil is (1<< psrpil), the next bit
- is (2 << psrpil). */
+ /*
+ * The bit corresponding to psrpil is (1<< psrpil),
+ * the next bit is (2 << psrpil).
+ */
if (pil < (2 << env->psrpil)) {
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
--
2.26.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl
2021-04-28 14:16 ` [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
@ 2021-04-28 14:35 ` Fred Konrad
2021-04-28 14:49 ` Richard Henderson
1 sibling, 0 replies; 12+ messages in thread
From: Fred Konrad @ 2021-04-28 14:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Mark Cave-Ayland, Richard Henderson,
Fabien Chouteau, KONRAD Frederic, Artyom Tarasenko
Le 4/28/21 à 4:16 PM, Philippe Mathieu-Daudé a écrit :
> We are going to move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> hw/sparc64/sparc64.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index cc0b9bd30d3..fd29a79edc0 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env)
> return;
> }
> cs = env_cpu(env);
> - /* check if TM or SM in SOFTINT are set
> - setting these also causes interrupt 14 */
> + /*
> + * check if TM or SM in SOFTINT are set
> + * setting these also causes interrupt 14
> + */
> if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
> pil |= 1 << 14;
> }
>
> - /* The bit corresponding to psrpil is (1<< psrpil), the next bit
> - is (2 << psrpil). */
> + /*
> + * The bit corresponding to psrpil is (1<< psrpil),
> + * the next bit is (2 << psrpil).
> + */
> if (pil < (2 << env->psrpil)) {
> if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl
2021-04-28 14:16 ` [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
2021-04-28 14:35 ` Fred Konrad
@ 2021-04-28 14:49 ` Richard Henderson
1 sibling, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2021-04-28 14:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: KONRAD Frederic, Mark Cave-Ayland, Thomas Huth, Fabien Chouteau,
Artyom Tarasenko
On 4/28/21 7:16 AM, Philippe Mathieu-Daudé wrote:
> We are going to move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> hw/sparc64/sparc64.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/4] hw/sparc*: Move cpu_check_irqs() to target/sparc/
2021-04-28 14:16 [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-04-28 14:16 ` [PATCH v2 3/4] hw/sparc64: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
@ 2021-04-28 14:16 ` Philippe Mathieu-Daudé
2021-04-28 14:53 ` Richard Henderson
2021-05-02 10:19 ` [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Mark Cave-Ayland
2021-05-04 21:32 ` Mark Cave-Ayland
5 siblings, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-28 14:16 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Mark Cave-Ayland, Richard Henderson,
Philippe Mathieu-Daudé,
Fabien Chouteau, KONRAD Frederic, Artyom Tarasenko
Since cpu_check_irqs() doesn't reference to anything outside
of CPUSPARCState, it better belongs to the architectural code
in target/, rather than the hardware specific code in hw/.
Note: while we moved the trace events, we don't rename them.
Remark: this allows us to build the leon3 machine stand alone,
fixing this link failure (because cpu_check_irqs is defined in
hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected):
/usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr':
target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs'
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sparc/sun4m.c | 32 ------------------
hw/sparc64/sparc64.c | 66 -------------------------------------
target/sparc/int32_helper.c | 33 +++++++++++++++++++
target/sparc/int64_helper.c | 66 +++++++++++++++++++++++++++++++++++++
hw/sparc/trace-events | 2 --
hw/sparc64/trace-events | 4 ---
target/sparc/trace-events | 8 +++++
7 files changed, 107 insertions(+), 104 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 1a00816d9a8..2edf913d945 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -159,38 +159,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr,
}
}
-void cpu_check_irqs(CPUSPARCState *env)
-{
- CPUState *cs;
-
- /* We should be holding the BQL before we mess with IRQs */
- g_assert(qemu_mutex_iothread_locked());
-
- if (env->pil_in && (env->interrupt_index == 0 ||
- (env->interrupt_index & ~15) == TT_EXTINT)) {
- unsigned int i;
-
- for (i = 15; i > 0; i--) {
- if (env->pil_in & (1 << i)) {
- int old_interrupt = env->interrupt_index;
-
- env->interrupt_index = TT_EXTINT | i;
- if (old_interrupt != env->interrupt_index) {
- cs = env_cpu(env);
- trace_sun4m_cpu_interrupt(i);
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- }
- break;
- }
- }
- } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
- cs = env_cpu(env);
- trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
- env->interrupt_index = 0;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- }
-}
-
static void cpu_kick_irq(SPARCCPU *cpu)
{
CPUSPARCState *env = &cpu->env;
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index fd29a79edc0..8654e955eb1 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -34,72 +34,6 @@
#define TICK_MAX 0x7fffffffffffffffULL
-void cpu_check_irqs(CPUSPARCState *env)
-{
- CPUState *cs;
- uint32_t pil = env->pil_in |
- (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
-
- /* We should be holding the BQL before we mess with IRQs */
- g_assert(qemu_mutex_iothread_locked());
-
- /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
- if (env->ivec_status & 0x20) {
- return;
- }
- cs = env_cpu(env);
- /*
- * check if TM or SM in SOFTINT are set
- * setting these also causes interrupt 14
- */
- if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
- pil |= 1 << 14;
- }
-
- /*
- * The bit corresponding to psrpil is (1<< psrpil),
- * the next bit is (2 << psrpil).
- */
- if (pil < (2 << env->psrpil)) {
- if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
- trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
- env->interrupt_index = 0;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- }
- return;
- }
-
- if (cpu_interrupts_enabled(env)) {
-
- unsigned int i;
-
- for (i = 15; i > env->psrpil; i--) {
- if (pil & (1 << i)) {
- int old_interrupt = env->interrupt_index;
- int new_interrupt = TT_EXTINT | i;
-
- if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
- && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
- trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
- cpu_tsptr(env)->tt,
- new_interrupt);
- } else if (old_interrupt != new_interrupt) {
- env->interrupt_index = new_interrupt;
- trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
- new_interrupt);
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- }
- break;
- }
- }
- } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
- trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
- env->interrupt_index);
- env->interrupt_index = 0;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- }
-}
-
static void cpu_kick_irq(SPARCCPU *cpu)
{
CPUState *cs = CPU(cpu);
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index d008dbdb65c..82e8418e465 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "trace.h"
#include "exec/log.h"
@@ -64,6 +65,38 @@ static const char *excp_name_str(int32_t exception_index)
return excp_names[exception_index];
}
+void cpu_check_irqs(CPUSPARCState *env)
+{
+ CPUState *cs;
+
+ /* We should be holding the BQL before we mess with IRQs */
+ g_assert(qemu_mutex_iothread_locked());
+
+ if (env->pil_in && (env->interrupt_index == 0 ||
+ (env->interrupt_index & ~15) == TT_EXTINT)) {
+ unsigned int i;
+
+ for (i = 15; i > 0; i--) {
+ if (env->pil_in & (1 << i)) {
+ int old_interrupt = env->interrupt_index;
+
+ env->interrupt_index = TT_EXTINT | i;
+ if (old_interrupt != env->interrupt_index) {
+ cs = env_cpu(env);
+ trace_sun4m_cpu_interrupt(i);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ break;
+ }
+ }
+ } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
+ cs = env_cpu(env);
+ trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
void sparc_cpu_do_interrupt(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index 7fb8ab211ca..793e57c536d 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -62,6 +62,72 @@ static const char * const excp_names[0x80] = {
};
#endif
+void cpu_check_irqs(CPUSPARCState *env)
+{
+ CPUState *cs;
+ uint32_t pil = env->pil_in |
+ (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
+
+ /* We should be holding the BQL before we mess with IRQs */
+ g_assert(qemu_mutex_iothread_locked());
+
+ /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
+ if (env->ivec_status & 0x20) {
+ return;
+ }
+ cs = env_cpu(env);
+ /*
+ * check if TM or SM in SOFTINT are set
+ * setting these also causes interrupt 14
+ */
+ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
+ pil |= 1 << 14;
+ }
+
+ /*
+ * The bit corresponding to psrpil is (1<< psrpil),
+ * the next bit is (2 << psrpil).
+ */
+ if (pil < (2 << env->psrpil)) {
+ if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+ trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ return;
+ }
+
+ if (cpu_interrupts_enabled(env)) {
+
+ unsigned int i;
+
+ for (i = 15; i > env->psrpil; i--) {
+ if (pil & (1 << i)) {
+ int old_interrupt = env->interrupt_index;
+ int new_interrupt = TT_EXTINT | i;
+
+ if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
+ && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
+ trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
+ cpu_tsptr(env)->tt,
+ new_interrupt);
+ } else if (old_interrupt != new_interrupt) {
+ env->interrupt_index = new_interrupt;
+ trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
+ new_interrupt);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ break;
+ }
+ }
+ } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+ trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
+ env->interrupt_index);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
void sparc_cpu_do_interrupt(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events
index dfb53dc1a24..d3a30a816aa 100644
--- a/hw/sparc/trace-events
+++ b/hw/sparc/trace-events
@@ -1,8 +1,6 @@
# See docs/devel/tracing.txt for syntax documentation.
# sun4m.c
-sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
-sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events
index a0b29987d2b..b85d14c30c8 100644
--- a/hw/sparc64/trace-events
+++ b/hw/sparc64/trace-events
@@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64"
sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
# sparc64.c
-sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
-sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
-sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
-sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d"
sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d"
sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled"
diff --git a/target/sparc/trace-events b/target/sparc/trace-events
index e925ddd1cc0..75e7093d5f3 100644
--- a/target/sparc/trace-events
+++ b/target/sparc/trace-events
@@ -10,10 +10,18 @@ mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, u
mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64
mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64
+# int32_helper.c
+sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
+sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
+
# int64_helper.c
int_helper_set_softint(uint32_t softint) "new 0x%08x"
int_helper_clear_softint(uint32_t softint) "new 0x%08x"
int_helper_write_softint(uint32_t softint) "new 0x%08x"
+sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
+sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
+sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
+sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
# win_helper.c
win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
--
2.26.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/4] hw/sparc*: Move cpu_check_irqs() to target/sparc/
2021-04-28 14:16 ` [PATCH v2 4/4] hw/sparc*: Move cpu_check_irqs() to target/sparc/ Philippe Mathieu-Daudé
@ 2021-04-28 14:53 ` Richard Henderson
0 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2021-04-28 14:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: KONRAD Frederic, Mark Cave-Ayland, Thomas Huth, Fabien Chouteau,
Artyom Tarasenko
On 4/28/21 7:16 AM, Philippe Mathieu-Daudé wrote:
> Since cpu_check_irqs() doesn't reference to anything outside
> of CPUSPARCState, it better belongs to the architectural code
> in target/, rather than the hardware specific code in hw/.
>
> Note: while we moved the trace events, we don't rename them.
>
> Remark: this allows us to build the leon3 machine stand alone,
> fixing this link failure (because cpu_check_irqs is defined in
> hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected):
>
> /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr':
> target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs'
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> hw/sparc/sun4m.c | 32 ------------------
> hw/sparc64/sparc64.c | 66 -------------------------------------
> target/sparc/int32_helper.c | 33 +++++++++++++++++++
> target/sparc/int64_helper.c | 66 +++++++++++++++++++++++++++++++++++++
> hw/sparc/trace-events | 2 --
> hw/sparc64/trace-events | 4 ---
> target/sparc/trace-events | 8 +++++
> 7 files changed, 107 insertions(+), 104 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine
2021-04-28 14:16 [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-04-28 14:16 ` [PATCH v2 4/4] hw/sparc*: Move cpu_check_irqs() to target/sparc/ Philippe Mathieu-Daudé
@ 2021-05-02 10:19 ` Mark Cave-Ayland
2021-05-04 21:32 ` Mark Cave-Ayland
5 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-02 10:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Richard Henderson, KONRAD Frederic, Fabien Chouteau,
Artyom Tarasenko
On 28/04/2021 15:16, Philippe Mathieu-Daudé wrote:
> Missing review: 2-4
>
> Since v1:
> - move cpu_check_irqs() to target/sparc/ (rth)
>
> This series fixes link failure when building either the leon3
> machine or the sun4m ones.
>
> The problem is we have hardware specific code in the architectural
> translation code. Move this code to hw/sparc/.
>
> The link failures can be reproduced doing:
>
> $ echo CONFIG_LEON3=y > default-configs/devices/sparc-softmmu.mak
> $ configure --without-default-devices
> $ ninja qemu-system-sparc
> $ ./qemu-system-sparc -M leon3 -S
>
> or:
>
> $ echo CONFIG_SUN4M=y > default-configs/devices/sparc-softmmu.mak
>
> Philippe Mathieu-Daudé (4):
> hw/sparc: Allow building without the leon3 machine
> hw/sparc64: Remove unused "hw/char/serial.h" header
> hw/sparc64: Fix code style for checkpatch.pl
> hw/sparc*: Move cpu_check_irqs() to target/sparc/
>
> target/sparc/cpu.h | 6 ----
> hw/sparc/leon3.c | 37 +++++++++++++++++++-
> hw/sparc/sun4m.c | 32 -----------------
> hw/sparc64/sparc64.c | 63 ---------------------------------
> target/sparc/int32_helper.c | 70 +++++++++++++++++--------------------
> target/sparc/int64_helper.c | 66 ++++++++++++++++++++++++++++++++++
> hw/sparc/trace-events | 4 +--
> hw/sparc64/trace-events | 4 ---
> target/sparc/trace-events | 12 ++++---
> 9 files changed, 145 insertions(+), 149 deletions(-)
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
ATB,
Mark.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine
2021-04-28 14:16 [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-05-02 10:19 ` [PATCH v2 0/4] hw/sparc: Kconfig fixes to build with/without the leon3 machine Mark Cave-Ayland
@ 2021-05-04 21:32 ` Mark Cave-Ayland
5 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-04 21:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Richard Henderson, KONRAD Frederic, Fabien Chouteau,
Artyom Tarasenko
On 28/04/2021 15:16, Philippe Mathieu-Daudé wrote:
> Missing review: 2-4
>
> Since v1:
> - move cpu_check_irqs() to target/sparc/ (rth)
>
> This series fixes link failure when building either the leon3
> machine or the sun4m ones.
>
> The problem is we have hardware specific code in the architectural
> translation code. Move this code to hw/sparc/.
>
> The link failures can be reproduced doing:
>
> $ echo CONFIG_LEON3=y > default-configs/devices/sparc-softmmu.mak
> $ configure --without-default-devices
> $ ninja qemu-system-sparc
> $ ./qemu-system-sparc -M leon3 -S
>
> or:
>
> $ echo CONFIG_SUN4M=y > default-configs/devices/sparc-softmmu.mak
>
> Philippe Mathieu-Daudé (4):
> hw/sparc: Allow building without the leon3 machine
> hw/sparc64: Remove unused "hw/char/serial.h" header
> hw/sparc64: Fix code style for checkpatch.pl
> hw/sparc*: Move cpu_check_irqs() to target/sparc/
>
> target/sparc/cpu.h | 6 ----
> hw/sparc/leon3.c | 37 +++++++++++++++++++-
> hw/sparc/sun4m.c | 32 -----------------
> hw/sparc64/sparc64.c | 63 ---------------------------------
> target/sparc/int32_helper.c | 70 +++++++++++++++++--------------------
> target/sparc/int64_helper.c | 66 ++++++++++++++++++++++++++++++++++
> hw/sparc/trace-events | 4 +--
> hw/sparc64/trace-events | 4 ---
> target/sparc/trace-events | 12 ++++---
> 9 files changed, 145 insertions(+), 149 deletions(-)
Thanks. I've queued this to my qemu-sparc branch.
ATB,
Mark.
^ permalink raw reply [flat|nested] 12+ messages in thread