Re: [PATCH 1/1] target/riscv: Convert env->virt to a bool env->virt_enabled

[liweiwei <liweiwei@iscas.ac.cn>]

On 2023/3/25 22:53, LIU Zhiwei wrote:
> Currently we only use the env->virt to encode the virtual mode enabled
> status. Let's make it a bool type.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---

I'm not quite sure the original reason to use a int for virt.

However, this change is acceptable to me.

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Weiwei Li

>   target/riscv/cpu.h        | 2 +-
>   target/riscv/cpu_bits.h   | 3 ---
>   target/riscv/cpu_helper.c | 6 +++---
>   target/riscv/machine.c    | 6 +++---
>   target/riscv/translate.c  | 4 ++--
>   5 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..3c8041c5a4 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -183,7 +183,7 @@ struct CPUArchState {
>   #ifndef CONFIG_USER_ONLY
>       target_ulong priv;
>       /* This contains QEMU specific information about the virt state. */
> -    target_ulong virt;
> +    bool virt_enabled;
>       target_ulong geilen;
>       uint64_t resetvec;
>   
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fca7ef0cef..45ddb00aa5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -607,9 +607,6 @@ typedef enum {
>   #define PRV_H 2 /* Reserved */
>   #define PRV_M 3
>   
> -/* Virtulisation Register Fields */
> -#define VIRT_ONOFF          1
> -
>   /* RV32 satp CSR field masks */
>   #define SATP32_MODE         0x80000000
>   #define SATP32_ASID         0x7fc00000
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..56f4ff9ccc 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -564,7 +564,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env)
>           return false;
>       }
>   
> -    return get_field(env->virt, VIRT_ONOFF);
> +    return env->virt_enabled;
>   }
>   
>   void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
> @@ -574,11 +574,11 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
>       }
>   
>       /* Flush the TLB on all virt mode changes. */
> -    if (get_field(env->virt, VIRT_ONOFF) != enable) {
> +    if (env->virt_enabled != enable) {
>           tlb_flush(env_cpu(env));
>       }
>   
> -    env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> +    env->virt_enabled = enable;
>   
>       if (enable) {
>           /*
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 9c455931d8..0fb3ddda06 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
>   
>   const VMStateDescription vmstate_riscv_cpu = {
>       .name = "cpu",
> -    .version_id = 7,
> -    .minimum_version_id = 7,
> +    .version_id = 8,
> +    .minimum_version_id = 8,
>       .post_load = riscv_cpu_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -352,7 +352,7 @@ const VMStateDescription vmstate_riscv_cpu = {
>           VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
>           VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
>           VMSTATE_UINTTL(env.priv, RISCVCPU),
> -        VMSTATE_UINTTL(env.virt, RISCVCPU),
> +        VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
>           VMSTATE_UINT64(env.resetvec, RISCVCPU),
>           VMSTATE_UINTTL(env.mhartid, RISCVCPU),
>           VMSTATE_UINT64(env.mstatus, RISCVCPU),
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0ee8ee147d..c3adf30b54 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1255,8 +1255,8 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
>   
>       fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
>   #ifndef CONFIG_USER_ONLY
> -    fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n",
> -            env->priv, env->virt);
> +    fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n",
> +            env->priv, env->virt_enabled);
>   #endif
>       target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
>   }