From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-devel@nongnu.org, Alistair.Francis@wdc.com,
palmer@dabbelt.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/1] target/riscv: Convert env->virt to a bool env->virt_enabled
Date: Wed, 5 Apr 2023 15:15:56 +1000 [thread overview]
Message-ID: <CAKmqyKMh4LhmQFSo86cWzXLEkhx4aFULsYA=+yXJRBEf8ko1Uw@mail.gmail.com> (raw)
In-Reply-To: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com>
On Sun, Mar 26, 2023 at 12:55 AM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> Currently we only use the env->virt to encode the virtual mode enabled
> status. Let's make it a bool type.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu_bits.h | 3 ---
> target/riscv/cpu_helper.c | 6 +++---
> target/riscv/machine.c | 6 +++---
> target/riscv/translate.c | 4 ++--
> 5 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..3c8041c5a4 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -183,7 +183,7 @@ struct CPUArchState {
> #ifndef CONFIG_USER_ONLY
> target_ulong priv;
> /* This contains QEMU specific information about the virt state. */
> - target_ulong virt;
> + bool virt_enabled;
> target_ulong geilen;
> uint64_t resetvec;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fca7ef0cef..45ddb00aa5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -607,9 +607,6 @@ typedef enum {
> #define PRV_H 2 /* Reserved */
> #define PRV_M 3
>
> -/* Virtulisation Register Fields */
> -#define VIRT_ONOFF 1
> -
> /* RV32 satp CSR field masks */
> #define SATP32_MODE 0x80000000
> #define SATP32_ASID 0x7fc00000
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..56f4ff9ccc 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -564,7 +564,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env)
> return false;
> }
>
> - return get_field(env->virt, VIRT_ONOFF);
> + return env->virt_enabled;
> }
>
> void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
> @@ -574,11 +574,11 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
> }
>
> /* Flush the TLB on all virt mode changes. */
> - if (get_field(env->virt, VIRT_ONOFF) != enable) {
> + if (env->virt_enabled != enable) {
> tlb_flush(env_cpu(env));
> }
>
> - env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> + env->virt_enabled = enable;
>
> if (enable) {
> /*
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 9c455931d8..0fb3ddda06 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 7,
> - .minimum_version_id = 7,
> + .version_id = 8,
> + .minimum_version_id = 8,
> .post_load = riscv_cpu_post_load,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -352,7 +352,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
> VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> - VMSTATE_UINTTL(env.virt, RISCVCPU),
> + VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
> VMSTATE_UINT64(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0ee8ee147d..c3adf30b54 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1255,8 +1255,8 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase,
>
> fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
> #ifndef CONFIG_USER_ONLY
> - fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n",
> - env->priv, env->virt);
> + fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n",
> + env->priv, env->virt_enabled);
> #endif
> target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
> }
> --
> 2.17.1
>
>
prev parent reply other threads:[~2023-04-05 5:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-25 14:53 [PATCH 1/1] target/riscv: Convert env->virt to a bool env->virt_enabled LIU Zhiwei
2023-03-26 14:50 ` liweiwei
2023-04-05 5:15 ` Alistair Francis
2023-04-05 5:15 ` Alistair Francis [this message]
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