Re: [Qemu-devel] [PATCH 00/14] target-i386: Implement MPX extension

[Paolo Bonzini <pbonzini@redhat.com>]

On 18/11/2015 10:43, Richard Henderson wrote:
>> 1) pester Intel some more so that they disclose the format of the SMM
>> state save area;
> 
> They have done so, and relatively well.  Section 34.4.1.1 of the
> software developer's manual (I'm looking at 325462-055, June 2015).

Relatively well unfortunately is not enough.  Unlike AMD, they do not
document where the descriptor cache is, which we need to implement SMM
save and restore.

> The issue, perhaps, is that the Intel and AMD layouts are totally
> different. Now, given that we've been using the AMD layout with Intel
> emulations maybe that means that it really doesn't matter what layout we
> use, so long as we're self-consistent.
> 
> Is there anything besides BIOS code that runs in SMM anyway?  Do we have
> to be compatible with anything besides SeaBIOS in this area?

There's OVMF, whose maintainers would really like the SMM state save
area to be a superset of the documented format.  They have grudgingly
accepted that we used AMD's format, which is completely different.  But
if we used Intel's format and did not put the descriptor cache at the
right place, then the next field Intel adds may overlap our descriptor
cache fields; we would be back with the same problem.

I would just place BNDCFGS at a random offset that is left as reserved
in AMD's manual.  Since we are at it, we might also find a home for EFER
in the 32-bit case, because it is used when LM is 0 but NX is 1.

Paolo