[Qemu-devel] [PATCH 0/3] ohci reset improvements

[Qemu-devel] [PATCH 0/3] ohci reset improvements

[Hervé Poussineau]

Hi,

This small patchset adds different reset levels to OHCI USB controller.
The idea is from Benjamin Herrenschmidt.
Most significant change is that MacOS 9 doesn't try anymore to do some
DMA transfer to address 0, and boots a little bit further.

Hervé

Hervé Poussineau (3):
  ohci: split reset method in 3 parts
  ohci: fix Host Controller USBRESET
  ohci: fix command HostControllerReset

 hw/usb/hcd-ohci.c | 64 ++++++++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 27 deletions(-)

-- 
2.1.4

[Qemu-devel] [PATCH 1/3] ohci: split reset method in 3 parts

[Hervé Poussineau]

The three parts are:
- root hub reset (ohci_roothub_reset)
- host controller soft reset (ohci_soft_reset)
- host controller hard reset (ohci_hard_reset)

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
 hw/usb/hcd-ohci.c | 64 ++++++++++++++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 27 deletions(-)

diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 7d65818..0661804 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -439,15 +439,37 @@ static void ohci_stop_endpoints(OHCIState *ohci)
     }
 }
 
-/* Reset the controller */
-static void ohci_reset(void *opaque)
+static void ohci_roothub_reset(OHCIState *ohci)
 {
-    OHCIState *ohci = opaque;
     OHCIPort *port;
     int i;
 
     ohci_bus_stop(ohci);
-    ohci->ctl = 0;
+    ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
+    ohci->rhdesc_b = 0x0; /* Impl. specific */
+    ohci->rhstatus = 0;
+
+    for (i = 0; i < ohci->num_ports; i++) {
+        port = &ohci->rhport[i];
+        port->ctrl = 0;
+        if (port->port.dev && port->port.dev->attached) {
+            usb_port_reset(&port->port);
+        }
+    }
+    if (ohci->async_td) {
+        usb_cancel_packet(&ohci->usb_packet);
+        ohci->async_td = 0;
+    }
+    ohci_stop_endpoints(ohci);
+}
+
+/* Reset the controller */
+static void ohci_soft_reset(OHCIState *ohci)
+{
+    trace_usb_ohci_reset(ohci->name);
+
+    ohci_bus_stop(ohci);
+    ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND;
     ohci->old_ctl = 0;
     ohci->status = 0;
     ohci->intr_status = 0;
@@ -470,25 +492,13 @@ static void ohci_reset(void *opaque)
     ohci->frame_number = 0;
     ohci->pstart = 0;
     ohci->lst = OHCI_LS_THRESH;
+}
 
-    ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
-    ohci->rhdesc_b = 0x0; /* Impl. specific */
-    ohci->rhstatus = 0;
-
-    for (i = 0; i < ohci->num_ports; i++)
-      {
-        port = &ohci->rhport[i];
-        port->ctrl = 0;
-        if (port->port.dev && port->port.dev->attached) {
-            usb_port_reset(&port->port);
-        }
-      }
-    if (ohci->async_td) {
-        usb_cancel_packet(&ohci->usb_packet);
-        ohci->async_td = 0;
-    }
-    ohci_stop_endpoints(ohci);
-    trace_usb_ohci_reset(ohci->name);
+static void ohci_hard_reset(OHCIState *ohci)
+{
+    ohci_soft_reset(ohci);
+    ohci->ctl = 0;
+    ohci_roothub_reset(ohci);
 }
 
 /* Get an array of dwords from main memory */
@@ -1441,7 +1451,7 @@ static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
         trace_usb_ohci_resume(ohci->name);
         break;
     case OHCI_USB_RESET:
-        ohci_reset(ohci);
+        ohci_hard_reset(ohci);
         break;
     }
 }
@@ -1704,7 +1714,7 @@ static void ohci_mem_write(void *opaque,
         ohci->status |= val;
 
         if (ohci->status & OHCI_STATUS_HCR)
-            ohci_reset(ohci);
+            ohci_hard_reset(ohci);
         break;
 
     case 3: /* HcInterruptStatus */
@@ -1783,7 +1793,7 @@ static void ohci_mem_write(void *opaque,
     case 25: /* HcHReset */
         ohci->hreset = val & ~OHCI_HRESET_FSBIR;
         if (val & OHCI_HRESET_FSBIR)
-            ohci_reset(ohci);
+            ohci_hard_reset(ohci);
         break;
 
     case 26: /* HcHInterruptEnable */
@@ -1960,7 +1970,7 @@ static void usb_ohci_reset_pci(DeviceState *d)
     OHCIPCIState *ohci = PCI_OHCI(dev);
     OHCIState *s = &ohci->state;
 
-    ohci_reset(s);
+    ohci_hard_reset(s);
 }
 
 #define TYPE_SYSBUS_OHCI "sysbus-ohci"
@@ -1993,7 +2003,7 @@ static void usb_ohci_reset_sysbus(DeviceState *dev)
     OHCISysBusState *s = SYSBUS_OHCI(dev);
     OHCIState *ohci = &s->ohci;
 
-    ohci_reset(ohci);
+    ohci_hard_reset(ohci);
 }
 
 static Property ohci_pci_properties[] = {
-- 
2.1.4

[Qemu-devel] [PATCH 2/3] ohci: fix Host Controller USBRESET

[Hervé Poussineau]

Specification says that, when entering this state, "the contents of the registers
(except Root Hub registers) are preserved by the HC. [...] The Root Hub is being reset,
which causes the Root Hub's downstream ports to be reset and possibly powered off."

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
 hw/usb/hcd-ohci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 0661804..24c62b4 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -1451,7 +1451,7 @@ static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
         trace_usb_ohci_resume(ohci->name);
         break;
     case OHCI_USB_RESET:
-        ohci_hard_reset(ohci);
+        ohci_roothub_reset(ohci);
         break;
     }
 }
-- 
2.1.4

[Qemu-devel] [PATCH 3/3] ohci: fix command HostControllerReset

[Hervé Poussineau]

Specification says that: "This bit is set by HCD to initiate a software reset of HC."

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
 hw/usb/hcd-ohci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 24c62b4..d225ebb 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -1714,7 +1714,7 @@ static void ohci_mem_write(void *opaque,
         ohci->status |= val;
 
         if (ohci->status & OHCI_STATUS_HCR)
-            ohci_hard_reset(ohci);
+            ohci_soft_reset(ohci);
         break;
 
     case 3: /* HcInterruptStatus */
-- 
2.1.4

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ohci reset improvements

[Mark Cave-Ayland]

On 19/12/15 23:23, Hervé Poussineau wrote:

> Hi,
> 
> This small patchset adds different reset levels to OHCI USB controller.
> The idea is from Benjamin Herrenschmidt.
> Most significant change is that MacOS 9 doesn't try anymore to do some
> DMA transfer to address 0, and boots a little bit further.
> 
> Hervé
> 
> Hervé Poussineau (3):
>   ohci: split reset method in 3 parts
>   ohci: fix Host Controller USBRESET
>   ohci: fix command HostControllerReset
> 
>  hw/usb/hcd-ohci.c | 64 ++++++++++++++++++++++++++++++++-----------------------
>  1 file changed, 37 insertions(+), 27 deletions(-)

I've given this patchset a test against my GSOC OS 9 images and it seems
to help against USB crashes (although there are still other extensions
that crash on boot) while not regressing my other images, so:

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


ATB,

Mark.

Re: [Qemu-devel] [PATCH 0/3] ohci reset improvements

[Gerd Hoffmann]

On So, 2015-12-20 at 00:23 +0100, Hervé Poussineau wrote:
> Hi,
> 
> This small patchset adds different reset levels to OHCI USB controller.
> The idea is from Benjamin Herrenschmidt.
> Most significant change is that MacOS 9 doesn't try anymore to do some
> DMA transfer to address 0, and boots a little bit further.
> 
> Hervé
> 
> Hervé Poussineau (3):
>   ohci: split reset method in 3 parts
>   ohci: fix Host Controller USBRESET
>   ohci: fix command HostControllerReset
> 
>  hw/usb/hcd-ohci.c | 64 ++++++++++++++++++++++++++++++++-----------------------
>  1 file changed, 37 insertions(+), 27 deletions(-)

Added to usb patch queue.

thanks,
  Gerd