From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
Date: Tue, 20 Apr 2021 07:17:39 -0700 [thread overview]
Message-ID: <639de1d9-294e-9fd9-14b3-5268d45e71e0@linaro.org> (raw)
In-Reply-To: <20210420013150.21992-1-frank.chang@sifive.com>
On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> From: Frank Chang<frank.chang@sifive.com>
>
> In IEEE 754-2008 spec:
> Invalid operation exception is signaled when doing:
> fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
> unless c is a quiet NaN; if c is a quiet NaN then it is
> implementation defined whether the invalid operation exception
> is signaled.
>
> In RISC-V Unprivileged ISA spec:
> The fused multiply-add instructions must set the invalid
> operation exception flag when the multiplicands are Inf and
> zero, even when the addend is a quiet NaN.
>
> This commit set invalid operation execption flag for RISC-V when
> multiplicands of muladd instructions are Inf and zero.
>
> Signed-off-by: Frank Chang<frank.chang@sifive.com>
> ---
> fpu/softfloat-specialize.c.inc | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, will you take this via your riscv queue?
r~
next prev parent reply other threads:[~2021-04-20 14:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-20 1:31 [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions frank.chang
2021-04-20 14:17 ` Richard Henderson [this message]
2021-04-22 0:05 ` Alistair Francis
2021-04-22 1:06 ` Richard Henderson
2021-04-22 1:42 ` Alistair Francis
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