From: Richard Henderson <richard.henderson@linaro.org>
To: "ishii.shuuichir@fujitsu.com" <ishii.shuuichir@fujitsu.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [RFC] Adding the A64FX's HPC funtions.
Date: Thu, 3 Jun 2021 13:08:15 -0700 [thread overview]
Message-ID: <65323e52-789c-567a-3446-ccb7709877e2@linaro.org> (raw)
In-Reply-To: <TYCPR01MB6160998DCE40866CDC3134BBE93C9@TYCPR01MB6160.jpnprd01.prod.outlook.com>
On 6/3/21 1:17 AM, ishii.shuuichir@fujitsu.com wrote:
> Hi, Richard.
>
> Thank you for your comment.
>
>> My first thought is that -cpu max can simply enable the extensions, without
>> extra flags. The max cpu has all of the features that we can enable, and as I
>> see it this is just one more.
>
> Let me confirm a few things about the above comment.
> Does it mean that I don't need to explicitly enable individual extensions
> such as a64fx-hpc-sec, a64fx-hpc-hwpf, and a64fx-hpc-hwb,
> since all extensions can be enabled by specifying -cpu max?
Well, Peter disagreed with having them enabled by default in -cpu max, so we
might need at least one extra property. I see no reason to have three
properties -- one property a64fx-hpc should be sufficient. But we might not
want any command-line properties, see below...
>
>> The microarchitectural document provided does not list all of the system
>> register reset values for the A64FX, and I would be surprised if there were an
>> architectural id register that specified a non-standard extension like this.
>> Thus I would expect to add ARM_FEATURE_A64FX with which to enable these
>> extensions in helper.c.
>
> As you said,
> some of the published specifications do not describe the reset values of the registers.
> I would like to implement this in QEMU by referring to a real machine with A64FX.
I presume there exists some documentation for this somewhere, though possibly
only internal to Fujitsu so far.
For comparison, in the Arm Cortex-A76 manual,
https://developer.arm.com/documentation/100798/0301/
section B2.4 "AArch64 registers by functional group", there is a concise
listing of all of the system registers and their reset values.
The most important of these for QEMU to create '-cpu a64fx' are the
ID_AA64{ISAR,MMFR,PFR} and MIDR values. These values determine all of the
standard architectural features, and from them we can tell what QEMU may (or
may not) be missing for proper emulation of the cpu. For comparison, look at
aarch64_a72_initfn in target/arm/cpu64.c.
Peter is suggesting that if full support for -cpu a64fx apart from the hpc
extensions is close, then we shouldn't implementing a property for -cpu max,
but only implement -cpu a64fx. (Because how does the OS detect the hpc
feature, apart from the MIDR value?)
r~
next prev parent reply other threads:[~2021-06-03 20:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <OS3PR01MB61515F08F0709D9E22B8DDDFE9249@OS3PR01MB6151.jpnprd01.prod.outlook.com>
[not found] ` <TYCPR01MB6160FB4A9712F3F5E14D8BBAE93E9@TYCPR01MB6160.jpnprd01.prod.outlook.com>
2021-06-01 15:21 ` [RFC] Adding the A64FX's HPC funtions Peter Maydell
2021-06-02 19:02 ` Richard Henderson
2021-06-02 19:10 ` Peter Maydell
2021-06-03 8:49 ` ishii.shuuichir
2021-06-03 8:17 ` ishii.shuuichir
2021-06-03 20:08 ` Richard Henderson [this message]
2021-06-04 8:29 ` ishii.shuuichir
2021-06-04 9:00 ` Peter Maydell
2021-06-07 8:52 ` ishii.shuuichir
2021-06-07 10:14 ` Alex Bennée
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