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From: "ishii.shuuichir@fujitsu.com" <ishii.shuuichir@fujitsu.com>
To: 'Peter Maydell' <peter.maydell@linaro.org>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"ishii.shuuichir@fujitsu.com" <ishii.shuuichir@fujitsu.com>
Subject: RE: [RFC] Adding the A64FX's HPC funtions.
Date: Mon, 7 Jun 2021 08:52:19 +0000	[thread overview]
Message-ID: <TYCPR01MB6160FA8EC9A7FC23CDE67166E9389@TYCPR01MB6160.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAFEAcA9vttSZRRX_DS7p6Hgo-4zbhDfkSd0jb-+LJZUOLrumAA@mail.gmail.com>

> If somebody has access to A64 hardware they could write a minor kernel
> patch to just print the values...

Yes, it's an ARM standard system register, so it's information that
users can find by checking. As you said, it is possible to check it that way,
and we would like to consider implementing the "-cpu a64fx" option based on
that information.

Thank you for your advice.

Best regards.


> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Friday, June 4, 2021 6:00 PM
> To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>;
> qemu-arm@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [RFC] Adding the A64FX's HPC funtions.
> Importance: High
> 
> On Fri, 4 Jun 2021 at 09:29, ishii.shuuichir@fujitsu.com
> <ishii.shuuichir@fujitsu.com> wrote:
> >
> > Hi, Richard.
> >
> > > Well, Peter disagreed with having them enabled by default in -cpu max, so
> we
> > > might need at least one extra property.  I see no reason to have three
> > > properties -- one property a64fx-hpc should be sufficient.  But we might
> not
> > > want any command-line properties, see below...
> >
> > I understood.
> >
> > > For comparison, in the Arm Cortex-A76 manual,
> > >    https://developer.arm.com/documentation/100798/0301/
> > > section B2.4 "AArch64 registers by functional group", there is a concise
> > > listing of all of the system registers and their reset values.
> >
> > Thank you for the information.
> >
> > > The most important of these for QEMU to create '-cpu a64fx' are the
> > > ID_AA64{ISAR,MMFR,PFR} and MIDR values.  These values determine all
> of
> > > the
> > > standard architectural features,
> >
> > The values of ID_AA64{ISAR,MMFR,PFR} and MIDR are not listed in the
> specifications published at this time.
> > Of course, they are listed in the A64FX specification document managed
> within Fujitsu,
> > but we cannot tell how far these setting values can be disclosed
> > without checking with the A64FX specification staff within Fujitsu.
> 
> If somebody has access to A64 hardware they could write a minor kernel
> patch to just print the values...
> 
> -- PMM


  reply	other threads:[~2021-06-07 13:06 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <OS3PR01MB61515F08F0709D9E22B8DDDFE9249@OS3PR01MB6151.jpnprd01.prod.outlook.com>
     [not found] ` <TYCPR01MB6160FB4A9712F3F5E14D8BBAE93E9@TYCPR01MB6160.jpnprd01.prod.outlook.com>
2021-06-01 15:21   ` [RFC] Adding the A64FX's HPC funtions Peter Maydell
2021-06-02 19:02     ` Richard Henderson
2021-06-02 19:10       ` Peter Maydell
2021-06-03  8:49         ` ishii.shuuichir
2021-06-03  8:17       ` ishii.shuuichir
2021-06-03 20:08         ` Richard Henderson
2021-06-04  8:29           ` ishii.shuuichir
2021-06-04  9:00             ` Peter Maydell
2021-06-07  8:52               ` ishii.shuuichir [this message]
2021-06-07 10:14               ` Alex Bennée

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