* [PATCH] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
@ 2021-04-21 18:50 Philippe Mathieu-Daudé
2021-04-21 20:03 ` Richard Henderson
2021-04-27 19:34 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-21 18:50 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Petar Jovanovic, Filip Vidojevic, Aurelien Jarno,
Vince Del Vecchio
Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":
The Read/Write Previous GPR opcodes "require CP0 privilege".
Add the missing CP0 checks.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5dad75cdf37..8a0a2197426 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18969,9 +18969,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_RDPGPR:
+ check_cp0_enabled(ctx);
gen_load_srsgpr(rs, rt);
break;
case NM_WRPGPR:
+ check_cp0_enabled(ctx);
gen_store_srsgpr(rs, rt);
break;
case NM_WAIT:
--
2.26.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
2021-04-21 18:50 [PATCH] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes Philippe Mathieu-Daudé
@ 2021-04-21 20:03 ` Richard Henderson
2021-04-27 19:34 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2021-04-21 20:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Petar Jovanovic, Vince Del Vecchio,
Aurelien Jarno, Filip Vidojevic
On 4/21/21 11:50 AM, Philippe Mathieu-Daudé wrote:
> Per the nanoMIPS32 Instruction Set Technical Reference Manual,
> Revision 01.01, Chapter 3. "Instruction Definitions":
>
> The Read/Write Previous GPR opcodes "require CP0 privilege".
>
> Add the missing CP0 checks.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/translate.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
2021-04-21 18:50 [PATCH] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes Philippe Mathieu-Daudé
2021-04-21 20:03 ` Richard Henderson
@ 2021-04-27 19:34 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-27 19:34 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Petar Jovanovic,
Filip Vidojevic, Aurelien Jarno, Vince Del Vecchio
On 4/21/21 8:50 PM, Philippe Mathieu-Daudé wrote:
> Per the nanoMIPS32 Instruction Set Technical Reference Manual,
> Revision 01.01, Chapter 3. "Instruction Definitions":
>
> The Read/Write Previous GPR opcodes "require CP0 privilege".
>
> Add the missing CP0 checks.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 2 ++
> 1 file changed, 2 insertions(+)
Thanks, applied to mips-next.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-04-21 18:50 [PATCH] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes Philippe Mathieu-Daudé
2021-04-21 20:03 ` Richard Henderson
2021-04-27 19:34 ` Philippe Mathieu-Daudé
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