* [PATCH v2 0/7] RISC-V: Add more machine memory
@ 2019-09-27 0:44 Alistair Francis
2019-09-27 0:44 ` [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory Alistair Francis
` (6 more replies)
0 siblings, 7 replies; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
This series aims to improve the use of QEMU for developing boot code. It
does a few things:
- sifive_u machine:
- Adds a chunk of memory in the Flash area. This allows boot loaders
to use this memory. I can't find details on the QSPI flash used on
the real board, so this is the best bet at the moment.
- Adds a chunk of memory in the L2-LIM area. This is actualy the L2
cache and should shrink as the L2 cache is enalbed. Unfortunatley I
don't see a nice way to shrink this memory.
- Adds a property that allows users to specify if QEMU should jump to
flash or DRAM after the ROM code.
- virt machine:
- Add the pflash_cfi01 flash device. This is based on the ARM virt
board implementation
- Adjusts QEMU to jump to the flash if a user has speciefied any
pflash.
Both machines have been tested with oreboot, but this should also help
the coreboot developers.
v2:
- Address comments
- Fixup addresses
- Don't use macro for machine definition of RISC-V virt machine
Alistair Francis (7):
riscv/sifive_u: Add L2-LIM cache memory
riscv/sifive_u: Add QSPI memory region
riscv/sifive_u: Manually define the machine
riscv/sifive_u: Add the start-in-flash property
riscv/virt: Manually define the machine
riscv/virt: Add the PFlash CFI01 device
riscv/virt: Jump to pflash if specified
hw/riscv/Kconfig | 1 +
hw/riscv/sifive_u.c | 95 +++++++++++++++++++++++----
hw/riscv/virt.c | 127 ++++++++++++++++++++++++++++++++++--
include/hw/riscv/sifive_u.h | 11 +++-
include/hw/riscv/virt.h | 10 ++-
5 files changed, 222 insertions(+), 22 deletions(-)
--
2.23.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:56 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region Alistair Francis
` (5 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
On reset only a single L2 cache way is enabled, the others are exposed
as memory that can be used by early boot firmware. This L2 region is
generally disabled using the WayEnable register at a later stage in the
boot process. To allow firmware to target QEMU and the HiFive Unleashed
let's add the L2 LIM (LooselyIntegrated Memory).
Ideally we would want to adjust the size of this chunk of memory as the
L2 Cache Controller WayEnable register is incremented. Unfortunately I
don't see a nice way to handle reducing or blocking out the L2 LIM while
still allowing it be re returned to all enabled from a reset.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 16 ++++++++++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9f8e84bf2e..1d255ad13e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -65,6 +65,7 @@ static const struct MemmapEntry {
[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
@@ -431,6 +432,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
const struct MemmapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
char *plic_hart_config;
size_t plic_hart_config_len;
@@ -459,6 +461,20 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
mask_rom);
+ /*
+ * Add L2-LIM at reset size.
+ * This should be reduced in size as the L2 Cache Controller WayEnable
+ * register is incremented. Unfortunately I don't see a nice (or any) way
+ * to handle reducing or blocking out the L2 LIM while still allowing it
+ * be re returned to all enabled after a reset. For the time being, just
+ * leave it enabled all the time. This won't break anything, but will be
+ * too generous to misbehaving guests.
+ */
+ memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
+ memmap[SIFIVE_U_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ l2lim_mem);
+
/* create PLIC hart topology configuration string */
plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
ms->smp.cpus;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e4df298c23..50e3620c02 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -58,6 +58,7 @@ enum {
SIFIVE_U_DEBUG,
SIFIVE_U_MROM,
SIFIVE_U_CLINT,
+ SIFIVE_U_L2LIM,
SIFIVE_U_PLIC,
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
2019-09-27 0:44 ` [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:56 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 3/7] riscv/sifive_u: Manually define the machine Alistair Francis
` (4 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no
model of this in QEMU, so to allow boot firmware developers to use QEMU
to target the Unleashed let's add a chunk of memory to represent the QSPI0
memory mapped flash. This can be targeted using QEMU's -device loader
command line option.
In the future we can look at adding a model for the is25wp256 flash.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 8 ++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1d255ad13e..bc0e01242b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -71,6 +71,7 @@ static const struct MemmapEntry {
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
+ [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
@@ -313,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine)
SiFiveUState *s = g_new0(SiFiveUState, 1);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *flash0 = g_new(MemoryRegion, 1);
int i;
/* Initialize SoC */
@@ -328,6 +330,12 @@ static void riscv_sifive_u_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
main_mem);
+ /* register QSPI0 Flash */
+ memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
+ memmap[SIFIVE_U_FLASH0].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+ flash0);
+
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 50e3620c02..2a08e2a5db 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -64,6 +64,7 @@ enum {
SIFIVE_U_UART0,
SIFIVE_U_UART1,
SIFIVE_U_OTP,
+ SIFIVE_U_FLASH0,
SIFIVE_U_DRAM,
SIFIVE_U_GEM,
SIFIVE_U_GEM_MGMT
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/7] riscv/sifive_u: Manually define the machine
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
2019-09-27 0:44 ` [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory Alistair Francis
2019-09-27 0:44 ` [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:56 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property Alistair Francis
` (3 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to specify machine properties.
This patch is no functional change.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++-----------
include/hw/riscv/sifive_u.h | 7 +++++-
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index bc0e01242b..f5741e9a38 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
static void riscv_sifive_u_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
-
- SiFiveUState *s = g_new0(SiFiveUState, 1);
+ SiFiveUState *s = RISCV_U_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
@@ -433,6 +432,10 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
+static void riscv_sifive_u_machine_instance_init(Object *obj)
+{
+}
+
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -546,17 +549,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
-static void riscv_sifive_u_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
- mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
- mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
- mc->default_cpus = mc->min_cpus;
-}
-
-DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
-
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -580,3 +572,29 @@ static void riscv_sifive_u_soc_register_types(void)
}
type_init(riscv_sifive_u_soc_register_types)
+
+static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive U SDK";
+ mc->init = riscv_sifive_u_init;
+ mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
+ mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
+ mc->default_cpus = mc->min_cpus;
+}
+
+static const TypeInfo riscv_sifive_u_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_u"),
+ .parent = TYPE_MACHINE,
+ .class_init = riscv_sifive_u_machine_class_init,
+ .instance_init = riscv_sifive_u_machine_instance_init,
+ .instance_size = sizeof(SiFiveUState),
+};
+
+static void riscv_sifive_u_machine_init_register_types(void)
+{
+ type_register_static(&riscv_sifive_u_machine_typeinfo);
+}
+
+type_init(riscv_sifive_u_machine_init_register_types)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 2a08e2a5db..a921079fbe 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState {
CadenceGEMState gem;
} SiFiveUSoCState;
+#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
+#define RISCV_U_MACHINE(obj) \
+ OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
+
typedef struct SiFiveUState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
SiFiveUSoCState soc;
+
void *fdt;
int fdt_size;
} SiFiveUState;
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
` (2 preceding siblings ...)
2019-09-27 0:44 ` [PATCH v2 3/7] riscv/sifive_u: Manually define the machine Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:57 ` Bin Meng
2019-10-08 20:12 ` Palmer Dabbelt
2019-09-27 0:44 ` [PATCH v2 5/7] riscv/virt: Manually define the machine Alistair Francis
` (2 subsequent siblings)
6 siblings, 2 replies; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 29 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f5741e9a38..33b55d0d5b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine)
/* dtb: */
};
+ if (s->start_in_flash) {
+ reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */
+ }
+
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
reset_vec[i] = cpu_to_le32(reset_vec[i]);
@@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
+static bool virt_get_start_in_flash(Object *obj, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ return s->start_in_flash;
+}
+
+static void virt_set_start_in_flash(Object *obj, bool value, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = value;
+}
+
static void riscv_sifive_u_machine_instance_init(Object *obj)
{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = false;
+ object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash,
+ virt_set_start_in_flash, NULL);
+ object_property_set_description(obj, "start-in-flash",
+ "Set on to tell QEMU's ROM to jump to " \
+ "flash. Otherwise QEMU will jump to DRAM",
+ NULL);
}
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a921079fbe..2656b43c58 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -57,6 +57,8 @@ typedef struct SiFiveUState {
void *fdt;
int fdt_size;
+
+ bool start_in_flash;
} SiFiveUState;
enum {
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 5/7] riscv/virt: Manually define the machine
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
` (3 preceding siblings ...)
2019-09-27 0:44 ` [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:57 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device Alistair Francis
2019-09-27 0:44 ` [PATCH v2 7/7] riscv/virt: Jump to pflash if specified Alistair Francis
6 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to use the machine object to create
RISCVVirtState. This is required to add children and aliases to the
machine.
This patch is no functional change.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 30 ++++++++++++++++++++++++------
include/hw/riscv/virt.h | 7 ++++++-
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d36f5625ec..e4dcbadcb5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -362,8 +362,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
static void riscv_virt_board_init(MachineState *machine)
{
const struct MemmapEntry *memmap = virt_memmap;
-
- RISCVVirtState *s = g_new0(RISCVVirtState, 1);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
@@ -499,12 +498,31 @@ static void riscv_virt_board_init(MachineState *machine)
g_free(plic_hart_config);
}
-static void riscv_virt_board_machine_init(MachineClass *mc)
+static void riscv_virt_machine_instance_init(Object *obj)
{
- mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
+}
+
+static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V VirtIO board";
mc->init = riscv_virt_board_init;
- mc->max_cpus = 8; /* hardcoded limit in BBL */
+ mc->max_cpus = 8;
mc->default_cpu_type = VIRT_CPU;
}
-DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
+static const TypeInfo riscv_virt_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("virt"),
+ .parent = TYPE_MACHINE,
+ .class_init = riscv_virt_machine_class_init,
+ .instance_init = riscv_virt_machine_instance_init,
+ .instance_size = sizeof(RISCVVirtState),
+};
+
+static void riscv_virt_machine_init_register_types(void)
+{
+ type_register_static(&riscv_virt_machine_typeinfo);
+}
+
+type_init(riscv_virt_machine_init_register_types)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 6e5fbe5d3b..ffcdcc6dcc 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -22,13 +22,18 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
+#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
+#define RISCV_VIRT_MACHINE(obj) \
+ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
+
typedef struct {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent;
/*< public >*/
RISCVHartArrayState soc;
DeviceState *plic;
+
void *fdt;
int fdt_size;
} RISCVVirtState;
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
` (4 preceding siblings ...)
2019-09-27 0:44 ` [PATCH v2 5/7] riscv/virt: Manually define the machine Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:57 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 7/7] riscv/virt: Jump to pflash if specified Alistair Francis
6 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
from the ARM Virt board and the implementation is based on the ARM Virt
board. This allows users to specify flash files from the command line.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c | 86 +++++++++++++++++++++++++++++++++++++++++
include/hw/riscv/virt.h | 3 ++
3 files changed, 90 insertions(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index fb19b2df3a..b12660b9f8 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -36,4 +36,5 @@ config RISCV_VIRT
select SERIAL
select VIRTIO_MMIO
select PCI_EXPRESS_GENERIC_BRIDGE
+ select PFLASH_CFI01
select SIFIVE
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e4dcbadcb5..ad29e14d5f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -26,6 +26,7 @@
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
@@ -61,12 +62,77 @@ static const struct MemmapEntry {
[VIRT_PLIC] = { 0xc000000, 0x4000000 },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
+ [VIRT_FLASH] = { 0x20000000, 0x2000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
};
+#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
+
+static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
+ const char *name,
+ const char *alias_prop_name)
+{
+ /*
+ * Create a single flash device. We use the same parameters as
+ * the flash devices on the ARM virt board.
+ */
+ DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
+
+ qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
+ qdev_prop_set_uint8(dev, "width", 4);
+ qdev_prop_set_uint8(dev, "device-width", 2);
+ qdev_prop_set_bit(dev, "big-endian", false);
+ qdev_prop_set_uint16(dev, "id0", 0x89);
+ qdev_prop_set_uint16(dev, "id1", 0x18);
+ qdev_prop_set_uint16(dev, "id2", 0x00);
+ qdev_prop_set_uint16(dev, "id3", 0x00);
+ qdev_prop_set_string(dev, "name", name);
+
+ object_property_add_child(OBJECT(s), name, OBJECT(dev),
+ &error_abort);
+ object_property_add_alias(OBJECT(s), alias_prop_name,
+ OBJECT(dev), "drive", &error_abort);
+
+ return PFLASH_CFI01(dev);
+}
+
+static void virt_flash_create(RISCVVirtState *s)
+{
+ s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
+ s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
+}
+
+static void virt_flash_map1(PFlashCFI01 *flash,
+ hwaddr base, hwaddr size,
+ MemoryRegion *sysmem)
+{
+ DeviceState *dev = DEVICE(flash);
+
+ assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
+ assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
+ qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
+ qdev_init_nofail(dev);
+
+ memory_region_add_subregion(sysmem, base,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
+ 0));
+}
+
+static void virt_flash_map(RISCVVirtState *s,
+ MemoryRegion *sysmem)
+{
+ hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+ hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+
+ virt_flash_map1(s->flash[0], flashbase, flashsize,
+ sysmem);
+ virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
+ sysmem);
+}
+
static void create_pcie_irq_map(void *fdt, char *nodename,
uint32_t plic_phandle)
{
@@ -121,6 +187,8 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
char *nodename;
uint32_t plic_phandle, phandle = 1;
int i;
+ hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+ hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
@@ -316,6 +384,15 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
g_free(nodename);
+
+ nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
+ qemu_fdt_add_subnode(s->fdt, nodename);
+ qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
+ qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
+ 2, flashbase, 2, flashsize,
+ 2, flashbase + flashsize, 2, flashsize);
+ qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
+ g_free(nodename);
}
@@ -495,6 +572,15 @@ static void riscv_virt_board_init(MachineState *machine)
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ virt_flash_create(s);
+
+ for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
+ /* Map legacy -drive if=pflash to machine properties */
+ pflash_cfi01_legacy_drive(s->flash[i],
+ drive_get(IF_PFLASH, 0, i));
+ }
+ virt_flash_map(s, system_memory);
+
g_free(plic_hart_config);
}
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index ffcdcc6dcc..8630f84592 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
+#include "hw/block/flash.h"
#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
#define RISCV_VIRT_MACHINE(obj) \
@@ -33,6 +34,7 @@ typedef struct {
/*< public >*/
RISCVHartArrayState soc;
DeviceState *plic;
+ PFlashCFI01 *flash[2];
void *fdt;
int fdt_size;
@@ -46,6 +48,7 @@ enum {
VIRT_PLIC,
VIRT_UART0,
VIRT_VIRTIO,
+ VIRT_FLASH,
VIRT_DRAM,
VIRT_PCIE_MMIO,
VIRT_PCIE_PIO,
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 7/7] riscv/virt: Jump to pflash if specified
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
` (5 preceding siblings ...)
2019-09-27 0:44 ` [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device Alistair Francis
@ 2019-09-27 0:44 ` Alistair Francis
2019-09-27 7:57 ` Bin Meng
6 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 0:44 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
If the user supplied pflash to QEMU then change the reset code to jump
to the pflash base address instead of the DRAM base address.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/riscv/virt.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ad29e14d5f..a79d16d99a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -445,6 +445,7 @@ static void riscv_virt_board_init(MachineState *machine)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
char *plic_hart_config;
size_t plic_hart_config_len;
+ target_ulong start_addr = memmap[VIRT_DRAM].base;
int i;
unsigned int smp_cpus = machine->smp.cpus;
@@ -491,6 +492,14 @@ static void riscv_virt_board_init(MachineState *machine)
}
}
+ if (drive_get(IF_PFLASH, 0, 0)) {
+ /*
+ * Pflash was supplied, let's overwrite the address we jump to after
+ * reset to the base of the flash.
+ */
+ start_addr = virt_memmap[VIRT_FLASH].base;
+ }
+
/* reset vector */
uint32_t reset_vec[8] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
@@ -503,7 +512,7 @@ static void riscv_virt_board_init(MachineState *machine)
#endif
0x00028067, /* jr t0 */
0x00000000,
- memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */
+ start_addr, /* start: .dword */
0x00000000,
/* dtb: */
};
--
2.23.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
2019-09-27 0:44 ` [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory Alistair Francis
@ 2019-09-27 7:56 ` Bin Meng
2019-09-27 21:47 ` Alistair Francis
0 siblings, 1 reply; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:56 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:52 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> On reset only a single L2 cache way is enabled, the others are exposed
> as memory that can be used by early boot firmware. This L2 region is
> generally disabled using the WayEnable register at a later stage in the
> boot process. To allow firmware to target QEMU and the HiFive Unleashed
> let's add the L2 LIM (LooselyIntegrated Memory).
>
> Ideally we would want to adjust the size of this chunk of memory as the
> L2 Cache Controller WayEnable register is incremented. Unfortunately I
> don't see a nice way to handle reducing or blocking out the L2 LIM while
> still allowing it be re returned to all enabled from a reset.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
Please include a changelog in the future. otherwise it's hard to track
what is changed between patch versions.
> hw/riscv/sifive_u.c | 16 ++++++++++++++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 17 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region
2019-09-27 0:44 ` [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region Alistair Francis
@ 2019-09-27 7:56 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:56 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:51 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no
> model of this in QEMU, so to allow boot firmware developers to use QEMU
> to target the Unleashed let's add a chunk of memory to represent the QSPI0
> memory mapped flash. This can be targeted using QEMU's -device loader
> command line option.
>
> In the future we can look at adding a model for the is25wp256 flash.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 8 ++++++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 9 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/7] riscv/sifive_u: Manually define the machine
2019-09-27 0:44 ` [PATCH v2 3/7] riscv/sifive_u: Manually define the machine Alistair Francis
@ 2019-09-27 7:56 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:56 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:48 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Instead of using the DEFINE_MACHINE() macro to define the machine let's
> do it manually. This allows us to specify machine properties.
>
> This patch is no functional change.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++-----------
> include/hw/riscv/sifive_u.h | 7 +++++-
> 2 files changed, 37 insertions(+), 14 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
2019-09-27 0:44 ` [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property Alistair Francis
@ 2019-09-27 7:57 ` Bin Meng
2019-09-30 18:04 ` Alistair Francis
2019-10-08 20:12 ` Palmer Dabbelt
1 sibling, 1 reply; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:57 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DRAM which is the default
> behaviour.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++
> include/hw/riscv/sifive_u.h | 2 ++
> 2 files changed, 29 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f5741e9a38..33b55d0d5b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine)
> /* dtb: */
> };
>
> + if (s->start_in_flash) {
> + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */
> + }
Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to
pflash if specified" does for consistency, ie:
if (s->start_in_flash) {
start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword
FLASH0_BASE */
}
> +
> /* copy in the reset vector in little_endian byte order */
> for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> reset_vec[i] = cpu_to_le32(reset_vec[i]);
> @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
> TYPE_CADENCE_GEM);
> }
>
> +static bool virt_get_start_in_flash(Object *obj, Error **errp)
sifive_u_get_start_in_flash()
> +{
> + SiFiveUState *s = RISCV_U_MACHINE(obj);
> +
> + return s->start_in_flash;
> +}
> +
> +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp)
sifive_u_set_start_in_flash()
> +{
> + SiFiveUState *s = RISCV_U_MACHINE(obj);
> +
> + s->start_in_flash = value;
> +}
> +
> static void riscv_sifive_u_machine_instance_init(Object *obj)
> {
> + SiFiveUState *s = RISCV_U_MACHINE(obj);
> +
> + s->start_in_flash = false;
> + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash,
> + virt_set_start_in_flash, NULL);
> + object_property_set_description(obj, "start-in-flash",
> + "Set on to tell QEMU's ROM to jump to " \
> + "flash. Otherwise QEMU will jump to DRAM",
> + NULL);
> }
>
> static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index a921079fbe..2656b43c58 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -57,6 +57,8 @@ typedef struct SiFiveUState {
>
> void *fdt;
> int fdt_size;
> +
> + bool start_in_flash;
> } SiFiveUState;
>
Regards,
Bin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 5/7] riscv/virt: Manually define the machine
2019-09-27 0:44 ` [PATCH v2 5/7] riscv/virt: Manually define the machine Alistair Francis
@ 2019-09-27 7:57 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:57 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:51 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Instead of using the DEFINE_MACHINE() macro to define the machine let's
> do it manually. This allows us to use the machine object to create
> RISCVVirtState. This is required to add children and aliases to the
> machine.
>
> This patch is no functional change.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 30 ++++++++++++++++++++++++------
> include/hw/riscv/virt.h | 7 ++++++-
> 2 files changed, 30 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device
2019-09-27 0:44 ` [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device Alistair Francis
@ 2019-09-27 7:57 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:57 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:57 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
> from the ARM Virt board and the implementation is based on the ARM Virt
> board. This allows users to specify flash files from the command line.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/Kconfig | 1 +
> hw/riscv/virt.c | 86 +++++++++++++++++++++++++++++++++++++++++
> include/hw/riscv/virt.h | 3 ++
> 3 files changed, 90 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 7/7] riscv/virt: Jump to pflash if specified
2019-09-27 0:44 ` [PATCH v2 7/7] riscv/virt: Jump to pflash if specified Alistair Francis
@ 2019-09-27 7:57 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2019-09-27 7:57 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 8:57 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> If the user supplied pflash to QEMU then change the reset code to jump
> to the pflash base address instead of the DRAM base address.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/riscv/virt.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
2019-09-27 7:56 ` Bin Meng
@ 2019-09-27 21:47 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2019-09-27 21:47 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Sep 27, 2019 at 8:52 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > On reset only a single L2 cache way is enabled, the others are exposed
> > as memory that can be used by early boot firmware. This L2 region is
> > generally disabled using the WayEnable register at a later stage in the
> > boot process. To allow firmware to target QEMU and the HiFive Unleashed
> > let's add the L2 LIM (LooselyIntegrated Memory).
> >
> > Ideally we would want to adjust the size of this chunk of memory as the
> > L2 Cache Controller WayEnable register is incremented. Unfortunately I
> > don't see a nice way to handle reducing or blocking out the L2 LIM while
> > still allowing it be re returned to all enabled from a reset.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
>
> Please include a changelog in the future. otherwise it's hard to track
> what is changed between patch versions.
I normally just include one in the cover letter, individual patch
change logs can be a bit of a pain to maintain. I'll try to do a
better job in the future.
Alistair
>
> > hw/riscv/sifive_u.c | 16 ++++++++++++++++
> > include/hw/riscv/sifive_u.h | 1 +
> > 2 files changed, 17 insertions(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
2019-09-27 7:57 ` Bin Meng
@ 2019-09-30 18:04 ` Alistair Francis
2019-10-08 20:12 ` Palmer Dabbelt
0 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2019-09-30 18:04 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Add a property that when set to true QEMU will jump from the ROM code to
> > the start of flash memory instead of DRAM which is the default
> > behaviour.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++
> > include/hw/riscv/sifive_u.h | 2 ++
> > 2 files changed, 29 insertions(+)
> >
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index f5741e9a38..33b55d0d5b 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine)
> > /* dtb: */
> > };
> >
> > + if (s->start_in_flash) {
> > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */
> > + }
>
> Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to
> pflash if specified" does for consistency, ie:
>
> if (s->start_in_flash) {
> start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword
> FLASH0_BASE */
> }
>
> > +
> > /* copy in the reset vector in little_endian byte order */
> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> > reset_vec[i] = cpu_to_le32(reset_vec[i]);
> > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
> > TYPE_CADENCE_GEM);
> > }
> >
> > +static bool virt_get_start_in_flash(Object *obj, Error **errp)
>
> sifive_u_get_start_in_flash()
>
> > +{
> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
> > +
> > + return s->start_in_flash;
> > +}
> > +
> > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp)
>
> sifive_u_set_start_in_flash()
Yep, I have fixed all of these.
Alistair
>
> > +{
> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
> > +
> > + s->start_in_flash = value;
> > +}
> > +
> > static void riscv_sifive_u_machine_instance_init(Object *obj)
> > {
> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
> > +
> > + s->start_in_flash = false;
> > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash,
> > + virt_set_start_in_flash, NULL);
> > + object_property_set_description(obj, "start-in-flash",
> > + "Set on to tell QEMU's ROM to jump to " \
> > + "flash. Otherwise QEMU will jump to DRAM",
> > + NULL);
> > }
> >
> > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> > index a921079fbe..2656b43c58 100644
> > --- a/include/hw/riscv/sifive_u.h
> > +++ b/include/hw/riscv/sifive_u.h
> > @@ -57,6 +57,8 @@ typedef struct SiFiveUState {
> >
> > void *fdt;
> > int fdt_size;
> > +
> > + bool start_in_flash;
> > } SiFiveUState;
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
2019-09-27 0:44 ` [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property Alistair Francis
2019-09-27 7:57 ` Bin Meng
@ 2019-10-08 20:12 ` Palmer Dabbelt
1 sibling, 0 replies; 20+ messages in thread
From: Palmer Dabbelt @ 2019-10-08 20:12 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, qemu-riscv, qemu-devel, alistair23
On Thu, 26 Sep 2019 17:44:28 PDT (-0700), Alistair Francis wrote:
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DRAM which is the default
> behaviour.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++
> include/hw/riscv/sifive_u.h | 2 ++
> 2 files changed, 29 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f5741e9a38..33b55d0d5b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine)
> /* dtb: */
> };
>
> + if (s->start_in_flash) {
> + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */
> + }
> +
> /* copy in the reset vector in little_endian byte order */
> for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> reset_vec[i] = cpu_to_le32(reset_vec[i]);
> @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
> TYPE_CADENCE_GEM);
> }
>
> +static bool virt_get_start_in_flash(Object *obj, Error **errp)
> +{
> + SiFiveUState *s = RISCV_U_MACHINE(obj);
> +
> + return s->start_in_flash;
> +}
> +
> +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp)
> +{
> + SiFiveUState *s = RISCV_U_MACHINE(obj);
> +
> + s->start_in_flash = value;
> +}
> +
> static void riscv_sifive_u_machine_instance_init(Object *obj)
> {
> + SiFiveUState *s = RISCV_U_MACHINE(obj);
> +
> + s->start_in_flash = false;
> + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash,
> + virt_set_start_in_flash, NULL);
> + object_property_set_description(obj, "start-in-flash",
> + "Set on to tell QEMU's ROM to jump to " \
> + "flash. Otherwise QEMU will jump to DRAM",
> + NULL);
> }
>
> static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index a921079fbe..2656b43c58 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -57,6 +57,8 @@ typedef struct SiFiveUState {
>
> void *fdt;
> int fdt_size;
> +
> + bool start_in_flash;
> } SiFiveUState;
>
> enum {
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
2019-09-30 18:04 ` Alistair Francis
@ 2019-10-08 20:12 ` Palmer Dabbelt
2019-10-08 20:33 ` Alistair Francis
0 siblings, 1 reply; 20+ messages in thread
From: Palmer Dabbelt @ 2019-10-08 20:12 UTC (permalink / raw)
To: alistair23; +Cc: qemu-riscv, bmeng.cn, Alistair Francis, qemu-devel
On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistair23@gmail.com wrote:
> On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
>> <alistair.francis@wdc.com> wrote:
>> >
>> > Add a property that when set to true QEMU will jump from the ROM code to
>> > the start of flash memory instead of DRAM which is the default
>> > behaviour.
>> >
>> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> > ---
>> > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++
>> > include/hw/riscv/sifive_u.h | 2 ++
>> > 2 files changed, 29 insertions(+)
>> >
>> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
>> > index f5741e9a38..33b55d0d5b 100644
>> > --- a/hw/riscv/sifive_u.c
>> > +++ b/hw/riscv/sifive_u.c
>> > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine)
>> > /* dtb: */
>> > };
>> >
>> > + if (s->start_in_flash) {
>> > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */
>> > + }
>>
>> Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to
>> pflash if specified" does for consistency, ie:
>>
>> if (s->start_in_flash) {
>> start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword
>> FLASH0_BASE */
>> }
>>
>> > +
>> > /* copy in the reset vector in little_endian byte order */
>> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
>> > reset_vec[i] = cpu_to_le32(reset_vec[i]);
>> > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
>> > TYPE_CADENCE_GEM);
>> > }
>> >
>> > +static bool virt_get_start_in_flash(Object *obj, Error **errp)
>>
>> sifive_u_get_start_in_flash()
>>
>> > +{
>> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
>> > +
>> > + return s->start_in_flash;
>> > +}
>> > +
>> > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp)
>>
>> sifive_u_set_start_in_flash()
>
> Yep, I have fixed all of these.
Did I miss the v3?
>
> Alistair
>
>>
>> > +{
>> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
>> > +
>> > + s->start_in_flash = value;
>> > +}
>> > +
>> > static void riscv_sifive_u_machine_instance_init(Object *obj)
>> > {
>> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
>> > +
>> > + s->start_in_flash = false;
>> > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash,
>> > + virt_set_start_in_flash, NULL);
>> > + object_property_set_description(obj, "start-in-flash",
>> > + "Set on to tell QEMU's ROM to jump to " \
>> > + "flash. Otherwise QEMU will jump to DRAM",
>> > + NULL);
>> > }
>> >
>> > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>> > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
>> > index a921079fbe..2656b43c58 100644
>> > --- a/include/hw/riscv/sifive_u.h
>> > +++ b/include/hw/riscv/sifive_u.h
>> > @@ -57,6 +57,8 @@ typedef struct SiFiveUState {
>> >
>> > void *fdt;
>> > int fdt_size;
>> > +
>> > + bool start_in_flash;
>> > } SiFiveUState;
>> >
>>
>> Regards,
>> Bin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
2019-10-08 20:12 ` Palmer Dabbelt
@ 2019-10-08 20:33 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2019-10-08 20:33 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Tue, Oct 8, 2019 at 1:12 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistair23@gmail.com wrote:
> > On Fri, Sep 27, 2019 at 12:57 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
> >> <alistair.francis@wdc.com> wrote:
> >> >
> >> > Add a property that when set to true QEMU will jump from the ROM code to
> >> > the start of flash memory instead of DRAM which is the default
> >> > behaviour.
> >> >
> >> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> > ---
> >> > hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++++++
> >> > include/hw/riscv/sifive_u.h | 2 ++
> >> > 2 files changed, 29 insertions(+)
> >> >
> >> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> >> > index f5741e9a38..33b55d0d5b 100644
> >> > --- a/hw/riscv/sifive_u.c
> >> > +++ b/hw/riscv/sifive_u.c
> >> > @@ -373,6 +373,10 @@ static void riscv_sifive_u_init(MachineState *machine)
> >> > /* dtb: */
> >> > };
> >> >
> >> > + if (s->start_in_flash) {
> >> > + reset_vec[6] = memmap[SIFIVE_U_FLASH0].base; /* start: .dword FLASH0_BASE */
> >> > + }
> >>
> >> Please change to use the way that patch "[v2,7/7] riscv/virt: Jump to
> >> pflash if specified" does for consistency, ie:
> >>
> >> if (s->start_in_flash) {
> >> start_addr = memmap[SIFIVE_U_FLASH0].base; /* start: .dword
> >> FLASH0_BASE */
> >> }
> >>
> >> > +
> >> > /* copy in the reset vector in little_endian byte order */
> >> > for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
> >> > reset_vec[i] = cpu_to_le32(reset_vec[i]);
> >> > @@ -432,8 +436,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
> >> > TYPE_CADENCE_GEM);
> >> > }
> >> >
> >> > +static bool virt_get_start_in_flash(Object *obj, Error **errp)
> >>
> >> sifive_u_get_start_in_flash()
> >>
> >> > +{
> >> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
> >> > +
> >> > + return s->start_in_flash;
> >> > +}
> >> > +
> >> > +static void virt_set_start_in_flash(Object *obj, bool value, Error **errp)
> >>
> >> sifive_u_set_start_in_flash()
> >
> > Yep, I have fixed all of these.
>
> Did I miss the v3?
Nope, I'll send it today.
Alistair
>
> >
> > Alistair
> >
> >>
> >> > +{
> >> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
> >> > +
> >> > + s->start_in_flash = value;
> >> > +}
> >> > +
> >> > static void riscv_sifive_u_machine_instance_init(Object *obj)
> >> > {
> >> > + SiFiveUState *s = RISCV_U_MACHINE(obj);
> >> > +
> >> > + s->start_in_flash = false;
> >> > + object_property_add_bool(obj, "start-in-flash", virt_get_start_in_flash,
> >> > + virt_set_start_in_flash, NULL);
> >> > + object_property_set_description(obj, "start-in-flash",
> >> > + "Set on to tell QEMU's ROM to jump to " \
> >> > + "flash. Otherwise QEMU will jump to DRAM",
> >> > + NULL);
> >> > }
> >> >
> >> > static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> >> > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> >> > index a921079fbe..2656b43c58 100644
> >> > --- a/include/hw/riscv/sifive_u.h
> >> > +++ b/include/hw/riscv/sifive_u.h
> >> > @@ -57,6 +57,8 @@ typedef struct SiFiveUState {
> >> >
> >> > void *fdt;
> >> > int fdt_size;
> >> > +
> >> > + bool start_in_flash;
> >> > } SiFiveUState;
> >> >
> >>
> >> Regards,
> >> Bin
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-10-08 20:39 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-27 0:44 [PATCH v2 0/7] RISC-V: Add more machine memory Alistair Francis
2019-09-27 0:44 ` [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory Alistair Francis
2019-09-27 7:56 ` Bin Meng
2019-09-27 21:47 ` Alistair Francis
2019-09-27 0:44 ` [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region Alistair Francis
2019-09-27 7:56 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 3/7] riscv/sifive_u: Manually define the machine Alistair Francis
2019-09-27 7:56 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property Alistair Francis
2019-09-27 7:57 ` Bin Meng
2019-09-30 18:04 ` Alistair Francis
2019-10-08 20:12 ` Palmer Dabbelt
2019-10-08 20:33 ` Alistair Francis
2019-10-08 20:12 ` Palmer Dabbelt
2019-09-27 0:44 ` [PATCH v2 5/7] riscv/virt: Manually define the machine Alistair Francis
2019-09-27 7:57 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device Alistair Francis
2019-09-27 7:57 ` Bin Meng
2019-09-27 0:44 ` [PATCH v2 7/7] riscv/virt: Jump to pflash if specified Alistair Francis
2019-09-27 7:57 ` Bin Meng
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).